CN101221980B - Power semiconductor device - Google Patents
Power semiconductor device Download PDFInfo
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- CN101221980B CN101221980B CN2008100034337A CN200810003433A CN101221980B CN 101221980 B CN101221980 B CN 101221980B CN 2008100034337 A CN2008100034337 A CN 2008100034337A CN 200810003433 A CN200810003433 A CN 200810003433A CN 101221980 B CN101221980 B CN 101221980B
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Abstract
The present invention provides an electric power semiconductor device, including a field plate which uses thin metallic film in edge termination structure, and capable of allowing the width of the edge termination structure to reduce even though there is large profile etching quantity or changed etching quantity, and showing excellent reliability of forward direction breaking voltage ability for a long time, as well as minimizing the change of the forward direction breaking voltage ability. The edge termination structure includes a plurality of p type guard rings, first insulating films for covering the surfaces of a plurality of annular p type guard rings, and annular field plate setting on the top of the guard ring by the first insulating film. The field plate includes multicrystal silicon film and metallic film which thickness is more than that of the multicrystal silicon film. The guard ring includes a first guard ring and a second guard ring, the multicrystal silicon film is set on the first guard ring by the first insulating film, and a twolayer field plate composed of the multicrystal silicon film and the metallic film stacked by the second insulating films, is set on the second gurad ring, the first and the second guard rings are set alternately.
Description
Technical field
The present invention relates to be used in the power semiconductor device in power converter etc.
Background technology
Fig. 9 show principal current in the active region of the central flows of conventional electric power semiconductor device (active region) 20 and be positioned at edge termination (edge termination) structural portion 30 on the periphery of active region 20 want the cross section view.Edge termination structure portion 30 is arranged to top electrode of n N-type semiconductor N substrate 100 that will device and the part that this OFF of-state voltage between the bottom electrode (bottom electrode is not shown) remains on the OFF state reliably.When the OFF of-state voltage increases, need to increase the width (width of edge termination structure portion 30 on the direction that the outward flange from the border of active region 20 towards semiconductor substrate 1 extends) of edge termination structure portion 30.Yet, because the width of edge termination structure portion 30 becomes big and its surface area that occupies also becomes greatly, so the surface area of the active region 20 that the principal current of device flows therein can experience relative reducing.Edge termination structure portion 30 is therefore as far as possible little ideally.
Under the situation of the edge termination structure portion 30 of conventional planar semiconductor device; not only to prevent the concentration of local of internal electric field so that guarantee specified forward blocking voltage ability, and border relaxation (boundary relaxation) structure such as guard ring 40 and field plate 80 etc. will be set sometimes to be used to improve the purpose of forward blocking voltage ability.In the middle of these border relaxation structures, for the purpose of the efficient in making processing, field plate 80 usually adopts the metal film with the same type that forms simultaneously such as the metal electrode 90 of emitter, negative electrode etc., and the P type trap 70 that forms on the face side of wherein said metal electrode 90 and the active region 20 of semiconductor device contacts.Such metal film comprises Al film that has wherein added micro-Si for example etc.Because the thickness of metal film is from 3 μ m to 5 μ m in power semiconductor device, so required emitter and field plate pattern are not by dry ecthing, but handle by the wet etching that utilizes the processing of taking a picture.Other operable field plate material is conduction silicon fiml and semi-insulating film etc.
Except the forward blocking voltage ability that produces owing to the electric field relaxation effect is improved, adopt the field plate 80 of this metal film also to have the harmful unwanted electric charge (hereinafter being called external charge) that is applied to the lip-deep dielectric film of edge termination structure from external environment condition, device atmosphere outside by shielding, keep the function of the long-term reliability of forward blocking voltage ability.
Enumerate the known document relevant with the field plate techniques that is used for power semiconductor device, such semiconductor device is known: edge termination structure alternately comprises conductive field plate and semi-insulating field plate, to generate semiconductor device, even when the occupied surface area of edge termination structure is very little, also can obtain stable high forward blocking voltage ability (patent No. 3591301) thus.
Yet such as previously mentioned, because required pattern is to handle by the metal film with big relatively film thickness is carried out wet etching, for the field plate that is applied to electric power semiconductor element routinely, the side etching amount of metal film is bigger.Because be necessary that being taken as design margin by the bigger corresponding width of side etching amount of handle and this expects each width by the arrow among Fig. 9 indication in design, so be difficult to shorten edge termination structure.In addition, because compare with dry ecthing, therefore wet etching also exists the problem that scattering takes place easily owing to the big scattering (scatter) in etch quantity etc. has low etching precision in the initial characteristic of device forward blocking voltage ability.
Summary of the invention
The present invention conceives in view of the above problems, and the object of the present invention is to provide a kind of power semiconductor device, even when the edge termination structure of power semiconductor device comprises the field plate of the metal film that the thick relatively metal electrode of employing is used, by being carried out, the metal film that is attached to whole surface occurring under the situation of big side etching amount or etch quantity scattering when wet etching is handled the field plate of predetermined pattern, also can allow the width of edge termination structure to be reduced, represent good long-term forward blocking voltage capacity reliability, and allow to make the scattering of forward blocking voltage ability characteristics to minimize.
According to the present invention of claim 1, the objective of the invention is to realize that by such power semiconductor device it comprises: the zone of another conductivity type in the semiconductor substrate surface layer of first conductivity type; Active region with the metal electrode in the zone that contacts another conductivity type; And the edge termination structure that centers on the active region, described edge termination structure has another conductivity type guard ring of a plurality of ring-types, cover first dielectric film on the surface of edge termination structure, and ring-type field plate, each ring-type field plate is set up via first dielectric film on the top that is positioned at another conductivity type guard ring of a plurality of ring-types, and wherein the ring-type field plate comprises: first field plate and second field plate that comprises metal film that comprise conductive film; And another conductivity type guard ring of a plurality of ring-types comprises: another conductivity type guard ring of first kind ring-type, and first field plate is arranged on another conductivity type guard ring of described first kind ring-type via first dielectric film; And second another conductivity type guard ring of class ring-type, it is provided with the double-deck field plate that comprises first field plate and second field plate, and described second field plate is arranged on the top of first field plate via second dielectric film.
The present invention of claim 2 is the power semiconductor device according to claim 1, and first field plate in the wherein double-deck field plate has the width bigger than second field plate on the direction with the annular shape of right angle crosscut field plate.
The present invention of claim 3 is the power semiconductor device according to claim 1; wherein between another conductivity type guard ring of a plurality of ring-types, first field plate and second field plate, set up the contact site of contact, be set in each at least one position in another conductivity type guard ring of a plurality of ring-types with same potential.
The present invention of claim 4 is the power semiconductor device according to claim 3; wherein contact site is by forming by second field plate is embedded in the structure that covers second field plate on the etch-hole; described etch-hole penetrates second dielectric film, first field plate and first dielectric film and arrives the surface of another conductivity type guard ring of ring-type, makes etching aperture in second dielectric film greater than the etching aperture of first field plate.
The present invention of claim 5 is the power semiconductor device according to claim 4, wherein contact site is arranged in the corner part of edge termination structure, described edge termination structure centers on the active region, and comprises four straight lines and the corner part that is connected four straight lines with arcuation.
The present invention of claim 6 is the power semiconductor device according to claim 5, and the width of arcuation part of another conductivity type guard ring of a plurality of ring-types of corner part that wherein is arranged in edge termination structure is greater than the width of four straight lines parts of edge termination structure.
The present invention of claim 7 is the power semiconductor device according to claim 6, wherein contact site is made of in first contact site or second contact site at least one, described first contact site covers second field plate by second field plate is embedded on the etch-hole, described etch-hole penetrates second dielectric film, first field plate and first dielectric film and arrives the surface of another conductivity type guard ring of ring-type, makes etching aperture in second dielectric film less than the etching aperture of first field plate; Described second contact site comprises lip-deep first dielectric film, first field plate and second dielectric film of another conductivity type guard ring of ring-type, and second dielectric film covers second field plate on the etch-hole of opening by it by being embedded in second field plate only.
The present invention of claim 8 is the power semiconductor device according to claim 7, and wherein first field plate forms by the low-resistance polysilicon that provides by ion injection or gas doping is provided.
The present invention of claim 9 is the power semiconductor device according to claim 7, and wherein second field plate forms by the metal film with the metal electrode same type that forms in the active region.
The present invention of claim 10 is the power semiconductor device according to claim 7, and wherein first dielectric film is a heat oxide film.
The present invention of claim 11 is the power semiconductor device according to claim 7, and wherein second dielectric film is the dielectric film that deposits by the chemical vapour deposition (CVD) mode.
The present invention of claim 12 is a power semiconductor device according to Claim 8, and wherein second dielectric film is formed by first field plate that polysilicon forms by oxidation.
The present invention of claim 13 is the power semiconductor device according to claim 4, and the zone of wherein exposing the surface of first field plate is set at the central authorities on the surface of another conductivity type guard ring of ring-type in the etch-hole that forms in the contact site.
The present invention of claim 14 is the power semiconductor device according to claim 13, wherein contact site is arranged in the corner part of edge termination structure, described edge termination structure centers on the active region, and comprises four straight lines and the corner part that is connected four straight lines with arcuation.
The present invention of claim 15 is the power semiconductor device according to claim 14, and the width of arcuation part of another conductivity type guard ring of a plurality of ring-types of corner part that wherein is arranged in edge termination structure is greater than the width of four straight lines parts of edge termination structure.
The present invention of claim 16 is the power semiconductor device according to claim 15, wherein contact site is made of in first contact site or second contact site at least one, described first contact site covers second field plate by second field plate is embedded on the etch-hole, described etch-hole penetrates second dielectric film, first field plate and first dielectric film and arrives the surface of another conductivity type guard ring of ring-type, makes etching aperture in second dielectric film less than the etching aperture of first field plate; Described second contact site comprises lip-deep first dielectric film, first field plate and second dielectric film of another conductivity type guard ring of ring-type, and second dielectric film covers second field plate on the etch-hole of opening by it by being embedded in second field plate only.
The present invention of claim 17 is the power semiconductor device according to claim 16, and wherein first field plate forms by the low-resistance polysilicon that provides by ion injection or gas doping is provided.
The present invention of claim 18 is the power semiconductor device according to claim 16, and wherein second field plate forms by the metal film with the metal electrode same type that forms in the active region.
The present invention of claim 19 is the power semiconductor device according to claim 16, and wherein first dielectric film is a heat oxide film.
The present invention of claim 20 is the power semiconductor device according to claim 16, and wherein second dielectric film is the dielectric film that deposits by the chemical vapour deposition (CVD) mode.
The present invention of claim 21 is the power semiconductor device according to claim 17, and wherein second dielectric film is formed by first field plate that polysilicon forms by oxidation.
The invention enables to provide a kind of power semiconductor device, even when the edge termination structure of power semiconductor device comprises the field plate of the metal film that the thick relatively metal electrode of employing is used, by being carried out, the metal film that is attached to whole surface occurring under the situation of big side etching amount or etch quantity scattering when wet etching is handled the field plate of predetermined pattern, also can allow the width of edge termination structure to be reduced, represent good long-term forward blocking voltage capacity reliability, and allow to make the scattering of initial forward blocking voltage ability characteristics to minimize.
Description of drawings
Fig. 1 be power semiconductor device edge termination structure first want the cross section view;
Fig. 2 be power semiconductor device edge termination structure second want the cross section view;
Fig. 3 be power semiconductor device edge termination structure the 3rd want the cross section view;
Fig. 4 be power semiconductor device edge termination structure the 4th want the cross section view;
Fig. 5-the 1st, the plan view of power semiconductor device of the present invention (a), and (first) plan view (b) of the edge termination structure in the corner part in the circular dashed line (a);
Fig. 5-the 2nd, the plan view of power semiconductor device of the present invention (a), and (second) plan view (b) of the edge termination structure in the corner part in the circular dashed line (a);
Fig. 5-the 3rd, (the 3rd) plan view (a) of the edge termination structure in the corner part of power semiconductor device of the present invention, and (the 4th) plan view (b) of the edge termination structure in the corner part of power semiconductor device of the present invention;
Fig. 6 is the amplification plan view of the edge termination structure in the corner part of power semiconductor device of the present invention;
Fig. 7-the 1st, along (first) viewgraph of cross-section of the line X-X ' intercepting of the edge termination structure of Fig. 5-1 (b), it shows the method for making power semiconductor device of the present invention;
Fig. 7-the 2nd, along (second) viewgraph of cross-section of the line X-X ' intercepting of the edge termination structure of Fig. 5-1 (b), it shows the method for making power semiconductor device of the present invention;
Fig. 7-the 3rd, along (the 3rd) viewgraph of cross-section of the line X-X ' intercepting of the edge termination structure of Fig. 5-1 (b), it shows the method for making power semiconductor device of the present invention;
Fig. 7-the 4th, along (the 4th) viewgraph of cross-section of the line X-X ' intercepting of the edge termination structure of Fig. 5-1 (b), it shows the method for making power semiconductor device of the present invention;
Fig. 8 is the viewgraph of cross-section along the line Y-Y ' of Fig. 5-2 (b) intercepting, and it shows the noncontact portion of the edge termination structure in the corner part of power semiconductor device of the present invention;
Fig. 9 be illustrate the conventional electric power semiconductor device edge termination structure want the cross section view;
Figure 10 is (the 5th) plan view (b) of the edge termination structure in the corner part of power semiconductor device of the present invention;
Figure 11 is (first) viewgraph of cross-section along the line D-D ' intercepting of Figure 10 of the present invention;
Figure 12 is (second) viewgraph of cross-section along the line D-D ' intercepting of Figure 10 of the present invention;
Figure 13 is (the 3rd) viewgraph of cross-section along the line D-D ' intercepting of Figure 10 of the present invention; And
Figure 14 is (the 4th) viewgraph of cross-section along the line D-D ' intercepting of Figure 10 of the present invention.
Embodiment
Hereinafter, describe embodiments of the invention with reference to the accompanying drawings in detail.The present invention not only is confined to the embodiment that hereinafter describes.
Fig. 1 to 4 be power semiconductor device of the present invention different edge termination structures want the cross section view.Fig. 5-1 is the plan view of the different edge termination structures in the corner part of power semiconductor device of the present invention to 5-3.Fig. 6 is the enlarged cross-sectional view of the edge termination structure in the corner part of power semiconductor device of the present invention.Fig. 7-1 is that it is used to illustrate the method for making power semiconductor device of the present invention along the viewgraph of cross-section of the line X-X ' intercepting of the edge termination structure of Fig. 5-1 (b) to 7-4.Fig. 8 is the viewgraph of cross-section along the line Y-Y ' of Fig. 5-1 (b) intercepting, and it shows the noncontact portion of the edge termination structure in the corner part of power semiconductor device of the present invention.Figure 10 is (the 5th) plan view (b) of the edge termination structure in the corner part of power semiconductor device of the present invention.Figure 11 to 14 is along the viewgraph of cross-section according to the intercepting of the line D-D ' among Figure 10 of the present invention.
Fig. 1 be power semiconductor device of the present invention want the cross section view, it illustrates the example that is positioned at around the edge termination structure of the periphery of active region, and described active region is arranged in from the dish type semiconductor substrate central authorities with first first type surface of the square silicon substrate (chip) of the pre-sizing of clathrate cutting.Edge termination structure 3 of the present invention is the diffusion layers that form in the superficial layer of n N-type semiconductor N substrate 1 by with diffusion of impurities; edge termination structure 3 comprises: be configured in around the active region a plurality of p type guard rings 4 in 2 the edge termination structure 3 with the flat shape of a plurality of ring-types; be formed on lip-deep first dielectric film 5 of edge termination structure 3, and be positioned at the field plate that comprises metal film or conductive film 7 and 8 on first dielectric film top.This embodiment illustrates vertical-channel MOSFET structure as active region 2.Channel mosfet comprises raceway groove 14, and it penetrates p type well area 10 and arrives n N-type semiconductor N substrate 1.The gate electrode 16 that is made of polysilicon is provided with via gate insulating film 15 in raceway groove 14.N+ source region 17 is in the upper end of the trap of raceway groove 14 is arranged on p type well area 10.Because the invention is characterized in edge termination structure 3, so omitted the detailed description of active region 2 and n N-type semiconductor N substrate 1.In fact, under the MOSFET situation, the n+ high concentration layer is arranged on the rear side of n N-type semiconductor N substrate 1, and under the IGBT situation, n+ high concentration layer and p type collector layer are arranged on the rear side of n N-type semiconductor N substrate 1.
Edge termination structure has two types field plate, i.e. first field plate 7 and second field plate 8, and they have different materials and different formation methods.The field plate that is arranged on a plurality of p type guard rings 4 of ring plain shape has the component part that first field plate 7 only is installed on it; with and on the component part of the dual stack field plate structure of being made up of first field plate 7 and second field plate 8 is installed, wherein second field plate 8 is layered on first field plate, 7 tops via second dielectric film 6.First field plate 7 is thin conductive films of high etching precision, and second field plate, 8 to the first field plates 7 are thick, and is made up of the metal film that the etching precision is lower than first field plate 7 relatively.Described metal film preferably is made up of the metal film of the same type that forms simultaneously with metal film 9, and described metal film 9 constitutes the main electrode that contacts with the surface of the p type well area 10 of active region 2.Power semiconductor device of the present invention is characterised in that and comprises such edge termination structure 3: in this edge termination structure 3, the ring-type p type guard ring 4 that first field plate 7 is installed on it with its on double- deck field plate 7 and 8 are installed ring-type p type guard ring 4 alternately layering lay (claim 1).Utilize the ring-type p type guard ring 4 of this edge termination structure 3, the spaced surface between second field plate 8 of the thick metal film of face side can be increased to such degree: even when the side etching amount of the material that forms field plate increases, also can ignore its influence.Therefore, can provide leeway, and the effect that can reduce the width of edge termination structure 3 is provided for design margin.
If configuration makes on the direction of the surface of edge termination structure 3 with right angle crosscut ring protection ring 4; the width of second field plate 8 is less than first field plate 7 (claim 2) of dual stack field plate structure, and then the forward blocking voltage ability is mainly determined by first field plate 7.First field plate 7 can be thinner so that reduce the side etching amount, and therefore provide the advantage with stable forward blocking voltage ability characteristics.In this case, second field plate 8 provides the field effect that prevents that the forward blocking voltage ability that caused by external charge from worsening.
Fig. 2 is except the different fact in the position of cross section, the viewgraph of cross-section of the edge termination structure identical with Fig. 1 of power semiconductor device of the present invention.This is to want cross section view (claim 4) in the position cutting that comprises the conduction tie point between field plate and the guard ring.Fig. 2 and the description of the detailed structure of the active region in the accompanying drawing subsequently will be omitted.The part of being irised out by dotted line among Fig. 2 indication is used for conducting electricity the contact site A that connects via small size part 4-1 between the second field plate 8-1, first field plate 7 and p type guard ring surface, is embedded with among the described second field plate 8-1 to penetrate dielectric film 5 and 6 and the etch-hole of field plate 7.The small size part 4-1 of this p type guard ring is illustrated in the interior surface portion of conduction connection mutually that exists of contact site A in the ring-type p type guard ring.
The etch-hole that the method that forms contact site A relates to by using dry ecthing to extend to form from the surface of second dielectric film 6, penetrate first field plate 7 and first dielectric film 5 and arriving the p type guard ring small size part 4-1 the contact site A forms contact hole; and by burying this contact hole underground to generate the second field plate 8-1, to generate the contact site A that connects the second field plate 8-1, first field plate 7 and p type guard ring small size part 4-1 conductively with Al-Si by means of sputter.Therefore, conduction between the second field plate 8-1 and first field plate 7 connects by the aperture of the contact hole that makes second dielectric film (interlayer dielectric) 6 and realizes greater than the aperture of first field plate 7, thereby allows more stable high rim termination structure (claim 4).Contact site A is not arranged on the whole circumference in each p type guard ring 4, but only is arranged on the point of any small size part in the ring.Yet, because there is not the guard ring width of the part of contact site A to be reduced in the edge termination structure, so this contact site A is preferred (claim 3).In Fig. 2, the part except contact site A is all identical with among Fig. 1 those, and will therefore omit the description to it.
Fig. 3 is edge termination structure partly the viewgraph of cross-section identical with Fig. 2 of power semiconductor device of the present invention.Yet this is to have to want the cross section view under the situation of different contact site B.The contact site B that with dashed lines is irised out among Fig. 3 represents such situation: the aperture of the contact hole in second insulation film (interlayer dielectric) 6 is less than the aperture of the contact hole in first field plate 7.For contact site B, only the p type guard ring small size part 4-1 and the second field plate 8-2 are contacted (claims 7).The other parts of Fig. 3 are identical with among Fig. 2 those, and will therefore omit the description to it.
Fig. 4 is the viewgraph of cross-section of the identical edge termination structure part of the Fig. 2 with power semiconductor device of the present invention, but this be have different contact site C want the cross section view.The contact site C that with dashed lines is irised out among Fig. 4 only forms contact hole in second dielectric film (interlayer dielectric) 6, and only first field plate 7 and the second field plate 8-3 are configured to be in contact with one another.When contact site B and contact site C are arranged at least one position in the ring-type p type guard ring; because the p type guard ring small size part 4-1 and first field plate 7 and the second field plate 8-3 are positioned at same potential, produced edge termination structure with stability identical with the situation that contact site A is set.
Because the second field plate 8-1 and 8-2 must be connected to p type guard ring small size part 4-1, so contact site A or contact site B must have the width of certain value.Therefore, in order to allow such connection, the width with p type guard ring part of contact site A or B preferably is provided the width bigger than other guard ring part (with the width on the direction of right angle crosscut ring protection ring).The result; under the situation of the edge termination structure of power semiconductor device of the present invention; by around four straight line 3-1 of active region 2 be connected in the arcuation edge termination structure 3 that partly (corner part) 3-2 forms on these four limits; the increase of the width of the straight line portion 3-1 of edge termination structure 3 can partly be inhibited by generate the guard ring with broad width in the corner part of widening (arcuation part) 3-2, shown in Fig. 5-1A and Fig. 5-2B.Provide the design of the narrow edge termination structure 3 (that is to say to have the device of big active region) of integral body therefore to become possibility.Arc dia by widening arcuation part 3-2 also moves the center of the arc periphery towards device, and only a plurality of ring-type field plates of being broadened of arcuation part 3-2 can form in edge termination structure 3.Configuration with a plurality of ring-type field plates of the arcuation part 3-2 that widens will be described subsequently.
Have by ion injects or gas doping (mixing identical with steam) provides low-resistance polysilicon film (claim 8) as first field plate 7 if adopt, and adopt the Al film that is doped with Trace Silicon in the formation be generally used for formed surface metal electrode 9 in the active region 2 as the second field plate 8-3, then exist to make existing electric semiconductor handle the advantage (claim 9) that is suitable for without change.In addition, because can make the film thickness of first field plate 7 thinner,, has the more edge termination structure of stability characteristic (quality) thereby can design so the scattering in the etching of first field plate 7 is minimized than the film thickness of the second field plate 8-3.
If the dielectric film (claim 11) that first dielectric film 5 adopts the heat oxide film (claim 10) and second dielectric film 6 to adopt by CVD (chemical vapour deposition (CVD)) deposition then exists to make existing electric semiconductor handle the advantage that is suitable for without change.In addition, if second dielectric film 6 forms by thermal oxidation polysilicon film 7, then need not to deposit second dielectric film 6, and can form the dielectric film (claim 12) of uniform films thickness.
Now, will specific embodiment of the present invention be described by utilizing Fig. 5-1,5-2 and 6.Fig. 5-1A and 5-1B and Fig. 5-2A and 5-2B are respectively the plan views (a) of the entire chip of semiconductor device, and four corner parts at four turnings that are arranged in edge termination structure 3 are by the amplification plan view (b) of the edge termination structure 3-2 of broken circle Z indication.In addition, Fig. 5-1B and 5-2B illustrate the adjacent corners part of the part 3-2 of edge termination structure in four turnings.The diagonal angle of the part 3-2 of the edge termination structure in four turnings has identical formation, but adjacent corners has as Fig. 5-1B and the different formations shown in the 5-2B.
Shown in Fig. 5-1B and 5-2B; in the middle of a plurality of p type guard rings in being formed on the edge termination structure of semiconductor device; first field plate is on the surface of the guard ring that begins the odd-numbered counted internally, and second field plate is on the surface of the guard ring that begins the even-numbered counted internally.First and second field plates on surface have identical width in the straight line portion of edge termination structure, but the width of field plate that is provided with contact site is extended in corner part.That is, the narrow field plate that is provided with the wide field plate of contact site and does not have a contact site in its corner part alternately is provided with (claim 5 and 6).
In addition; shown in Fig. 5-1B of a plurality of p type guard rings in the corner part of edge termination structure; some of p type guard ring part that only begin the odd-numbered counted internally have the contact site A that connects metal film field plate (second field plate) 8, polysilicon field plate (first field plate) 7 and p type guard ring small size part conductively; and in Fig. 5-2B, the small size contact site A ' that provides identical conduction to connect only is set in some of the guard ring that begins the even-numbered counted internally.That is, formation can so that: in the edge termination structure of chip surface, be that one group of across corner branch is provided with contact site, and this set of contact portion respectively be offset 90 the degree.In addition; at Fig. 5-1B and Fig. 5-2B in the two; curvature (radius of arc) with arcuation p type guard ring part of contact site makes; because the center of arc has been moved a bit towards the outside of semiconductor device at every turn; so that the width of the arcuation field plate 3-3 of this part or 3-4 is wideer than the width of linear edge termination structure, this means contact site is made easily.The width that does not have field plate 3-3 on the arcuation p type guard ring part of contact site and 3-4 is identical with the width of straight line portion.
Fig. 5-3 is examples of an embodiment, wherein different among the configuration of the required contact site of the wide arcuation p type guard ring part in the edge termination structure and Fig. 5-1 and the 5-2.Fig. 5-3A is such structure: only a contact site A is arranged in the corner part.In this case, because the each skew of contact site A 90 degree ground are provided with, when observing a corner part, three field plate 3-4 are arranged between the field plate 3-3 in the field plate 3-3 and the outside then.Therefore, can further shorten edge termination structure.Fig. 5-3B is such example: the contact site A in the corner part arranges with zigzag, thereby edge termination structure can further be shortened.In the embodiment of Fig. 5-3A and 5-3B, a plurality of field plates that do not have contact site can be arranged between the field plate with contact site.
Fig. 6 comprises the wide arcuation first field plate part 3-3 of the contact site A that is lived by the dotted line square box of Fig. 5-1B and the amplification plan view that does not have the second field plate part 3-4 of contact site.The contact hole 12 that passes first field plate of the contact hole 11 in hole and polysilicon film on interlayer dielectric (second dielectric film) 6 must be covered by metal film (second field plate) 8-1, be similar to the contact site B among Fig. 3.Yet, because metal film (second field plate) 8-1 usually forms by the mode of wet etching, thus consider the etching precision, be necessary for that width provides and the edge of contact hole 11 between the surplus of several μ m.Therefore, because need widen the p type guard ring width 4-1 and the second field plate width 8-1 of the part that is formed with contact site A, the width 3-3 of this part then width than the part that does not have contact site is bigger.Therefore; by such component part is set; promptly; not on all p type guard rings of the corner part of edge termination structure, to form contact site A; but according to edge termination structure 3 of the present invention; on the p type guard ring that replaces, form contact site A; just make that the increase of the width of edge termination structure can be inhibited in the corner part; and because be provided with the structure that not in straight line portion, does not form contact site, being designed to for may of the semiconductor device that the integral width of edge termination structure is reduced.
Metal film except contact site A shown in Fig. 5-1B and the 5-2B and A ' (second field plate) is used to minimize the influence that forward blocking voltage ability characteristics is produced because external charge is attached on the dielectric film, and has the effect of the long-term reliability that improves the forward blocking voltage ability.
To describe semiconductor device of the present invention along the edge termination structure viewgraph of cross-section (Fig. 7-1 is to 7-4) of the cross section of the line X-X ' intercepting of Fig. 5-2B by utilizing expression hereinafter, description will concentrate on the processing that is used to make edge termination structure.Although there is not to describe in detail the processing of the formation that comprises the active region, edge termination structure of the present invention goes for installing widely, such as gate driving semiconductor device and diode apparatus.
Shown in Fig. 7-1; for p type well area 10 that forms active region 2 and the p type guard ring 4 that forms simultaneously with zone 10; field oxide film 5 (first dielectric film) at first is formed on the semiconductor substrate 1; and form ion by the field oxide film 5 of etched edge termination structure 3 optionally and inject window 13, inject so that produce p type guard ring 4 by thermal scattering then with predetermined scattering degree of depth so carry out the ion that utilizes p type impurity such as boron.
Shown in Fig. 7-2, after having formed the thick thin oxide film 5-1 of about 50nm, deposit spathic silicon film (first field plate).Thickness can be about 0.5 μ m.Use photoetching process, remove the polysilicon film of contact site, and produce first field plate 7 of predetermined pattern by dry ecthing.When the polysilicon membrane-coating dry ecthing of contact site, the oxide-film 5-1 of polysilicon film below serves as etch stopper (etching stopper).
Shown in Fig. 7-3, follow afterwards by CVD (chemical vapour deposition (CVD)) deposition interlayer dielectric 6 (second dielectric film), in zone, form the opening in the interlayer dielectric 6 greater than the opening portion of the polysilicon 7 of contact site by utilizing photolithographic etching.Therefore, etching simultaneously the thin oxide-film 5-1 of the about 50nm in the opening portion of polysilicon film 7, to expose the surface in p type guard ring zone 4.
Shown in Fig. 7-4, after the metal film of Al-Si that the formation of the lip-deep metal electrode of the emitter 9 that utilizes sputter formation and active region 2 forms simultaneously etc., metal film as unwanted part in photoetching is removed by etching, to produce the second required field plate 8.
This metal film (second field plate) 8 is thicker, and therefore, usually utilizes wet etching, and the scattering of side etching amount is bigger.Only be retained in first field plate, 7 inboards of making (promptly according to metal film 8 by polysilicon film, the width of second field plate 8 is less than the width of first field plate 7) design, be to determine such as the key property of forward blocking voltage ability by the less polysilicon film of the scattering of side etching amount (first field plate) 7.Therefore, the little advantage of scattering that has characteristic.The metal film of edge termination structure (second field plate) 8 does not influence initial characteristic, and therefore, even when not having metal film in the part except contact site, the function of device does not have problem yet.Yet,, can suppress influence, as previously mentioned from the electric charge of outside by metal film being stayed with ring-type.
Generally speaking, passivating film such as the (not shown) such as polyimide resin that will insulate subsequently are formed on the edge termination structure to finish the face side manufacturing step.
In the zone except contact site, be not used in the window of etching polysilicon film (first field plate 7).Therefore, the oxide-film 5-1 of polysilicon film 7 belows is not etched and enter state of insulation, shown in Figure 8 as along the viewgraph of cross-section of the intercepting of the line Y-Y ' among Fig. 5-2.
Semiconductor device of the present invention makes can work as when comparing with the edge termination structure with identical forward blocking voltage ability, and the width that will be used for the edge termination structure of conventional structure reduces 20% or more.
In addition; Figure 10 shows the amplification plan view; it comprises the position of wide p type guard ring of the part of the edge termination structure with contact site identical with the contact site that forms among Fig. 7-4, and Figure 11 shows along the viewgraph of cross-section of the intercepting of the line D-D ' among Figure 10.According to Figure 11, because surperficial each other in an electrically conductive contact the in metal film (second field plate) 8, polysilicon film (first field plate) 7 and wide p type guard ring zone 4, so also have the current potential that is equal to each other.
Yet,, realized that as described above conduction contact and the current potential that equates have suitably obtained keeping if can suitably remove interlayer dielectric 6 on the polysilicon film 7 by etching.Yet, when the scattering owing to etch processes causes taking place etching when insufficient, will exist as shown in figure 12 polysilicon film 7 not expose and suitably realize the situation of conduction contact, wherein Figure 12 is the viewgraph of cross-section of the line D-D ' intercepting in Figure 10.Therefore, as shown in figure 13,, the polysilicon film 7-1 that does not have interlayer dielectric is stayed the central authorities on the guard ring surface that be exposed exposing in the etching step on guard ring surface by carry out etching in contact site inside.In Figure 13 and 14, polysilicon film 7-1 seems and separates.Yet as shown in figure 10, polysilicon film 7-1 unshowned some place in viewgraph of cross-section is connected to polysilicon film 7.Figure 13 and 14 is the viewgraph of cross-section along the intercepting of the line D-D ' among Figure 10.By on the guard ring surface of contact site, forming this polysilicon film 7-1; although to cause etching occurring in the etching process of interlayer dielectric 6 insufficient owing to the scattering during the pattern etching of interlayer dielectric; and the marginal portion of etched pattern is subjected to the inadequate influence of etching easily, but the interlayer dielectric on the polysilicon film 7-1 of pattern central authorities is not easy to be affected.Therefore, insufficient being not easy of etching taken place, and can guarantee the conduction contact between polysilicon film 7 and the metal film 8.As shown in figure 14, even in the marginal portion of etched pattern, occur under the inadequate situation of etching, owing to the interlayer dielectric of having removed in pattern central authorities on the polysilicon film 7-1, so guaranteed conduction contact (claim 13) via this surface.
It should be understood that the present invention who describes with reference to Figure 10 to 14 can have the formation effect identical with claim 5 to 12 (claim 14 to 21).
Claims (21)
1. a power semiconductor device comprises: the zone of another conductivity type in the semiconductor substrate surface layer of first conductivity type; Active region with the metal electrode in the zone that contacts described another conductivity type; And the edge termination structure that centers on described active region; described edge termination structure has another conductivity type guard ring of a plurality of ring-types; cover first dielectric film on the surface of described edge termination structure; and ring-type field plate; each ring-type field plate is set up via described first dielectric film on the top that is positioned at described another conductivity type guard ring of a plurality of ring-type
Wherein said ring-type field plate comprises:
First field plate and second field plate that comprises metal film that comprise conductive film; And
Another conductivity type guard ring of described a plurality of ring-type comprises:
Another conductivity type guard ring of first kind ring-type, described first field plate is arranged on another conductivity type guard ring of described first kind ring-type via described first dielectric film; And
Another conductivity type guard ring of the second class ring-type comprises that the double-deck field plate of described first field plate and described second field plate is arranged on described another conductivity type guard ring of the second class ring-type, and described second field plate is arranged on the top of described first field plate via second dielectric film.
2. power semiconductor device as claimed in claim 1; wherein on the direction of the surface of described edge termination structure with another conductivity type guard ring of the described ring-type of right angle crosscut, the width of described second field plate in the described double-deck field plate is less than the width of described first field plate.
3. power semiconductor device as claimed in claim 1; wherein between another conductivity type guard ring of described a plurality of ring-types, described first field plate and described second field plate, set up the contact site of contact, be set at each at least one place in another conductivity type guard ring of described a plurality of ring-type with same potential.
4. power semiconductor device as claimed in claim 3; wherein said contact site is by forming by described second field plate is embedded in the structure that covers described second field plate on the etch-hole; described etch-hole penetrates described second dielectric film, described first field plate and described first dielectric film and arrives the surface of another conductivity type guard ring of described ring-type, makes etching aperture in described second dielectric film greater than the etching aperture of described first field plate.
5. power semiconductor device as claimed in claim 4, wherein said contact site is arranged in the corner part of described edge termination structure, described edge termination structure centers on described active region, and comprises four straight lines and the corner part that is connected four straight lines with arcuation.
6. power semiconductor device as claimed in claim 5, the width of arcuation part of another conductivity type guard ring of described a plurality of ring-types of corner part that wherein is arranged in described edge termination structure is greater than the width of four straight lines parts of described edge termination structure.
7. power semiconductor device as claimed in claim 6, wherein said contact site is made of in first contact site and second contact site at least one,
Described first contact site covers described second field plate by described second field plate is embedded on the etch-hole, described etch-hole penetrates described second dielectric film, described first field plate and described first dielectric film and arrives the surface of another conductivity type guard ring of ring-type, makes etching aperture in described second dielectric film less than the etching aperture of described first field plate;
Described second contact site comprises lip-deep described first dielectric film of another conductivity type guard ring of ring-type, described first field plate and described second dielectric film, thereby and covers described second field plate by described second field plate being embedded on the etch-hole that only the described second dielectric film opening is formed.
8. power semiconductor device as claimed in claim 7, wherein said first field plate forms by the low-resistance polysilicon that provides by ion injection or gas doping is provided.
9. power semiconductor device as claimed in claim 7, wherein said second field plate forms by the metal film with the metal electrode same type that forms in described active region.
10. power semiconductor device as claimed in claim 7, wherein said first dielectric film is a heat oxide film.
11. power semiconductor device as claimed in claim 7, wherein said second dielectric film is the dielectric film that deposits by the chemical vapour deposition (CVD) mode.
12. power semiconductor device as claimed in claim 8, wherein said second dielectric film is formed by described first field plate that polysilicon forms by oxidation.
13. power semiconductor device as claimed in claim 4, the zone of wherein exposing the surface of described first field plate is set at the central authorities on the surface of another conductivity type guard ring of ring-type in the etch-hole that forms in the described contact site.
14. power semiconductor device as claimed in claim 13, wherein said contact site is arranged in the corner part of described edge termination structure, described edge termination structure centers on described active region, and comprises four straight lines and the corner part that is connected four straight lines with arcuation.
15. power semiconductor device as claimed in claim 14, the width of arcuation part of another conductivity type guard ring of described a plurality of ring-types of corner part that wherein is arranged in described edge termination structure is greater than the width of four straight lines parts of described edge termination structure.
16. power semiconductor device as claimed in claim 15, wherein said contact site is made of in first contact site and second contact site at least one,
Described first contact site covers described second field plate by described second field plate is embedded on the etch-hole, described etch-hole penetrates described second dielectric film, described first field plate and described first dielectric film and arrives the surface of another conductivity type guard ring of ring-type, makes etching aperture in described second dielectric film less than the etching aperture of described first field plate;
Described second contact site comprises lip-deep described first dielectric film of another conductivity type guard ring of ring-type, described first field plate and described second dielectric film, thereby and covers described second field plate by described second field plate being embedded on the etch-hole that only the described second dielectric film opening is formed.
17. power semiconductor device as claimed in claim 16, wherein said first field plate forms by the low-resistance polysilicon that provides by ion injection or gas doping is provided.
18. power semiconductor device as claimed in claim 16, wherein said second field plate forms by the metal film with the metal electrode same type that forms in described active region.
19. power semiconductor device as claimed in claim 16, wherein said first dielectric film is a heat oxide film.
20. power semiconductor device as claimed in claim 16, wherein said second dielectric film is the dielectric film that deposits by the chemical vapour deposition (CVD) mode.
21. power semiconductor device as claimed in claim 17, wherein said second dielectric film is formed by described first field plate that polysilicon forms by oxidation.
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| Application Number | Priority Date | Filing Date | Title |
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| JP2007-003579 | 2007-01-11 | ||
| JP2007003579 | 2007-01-11 | ||
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| JP2007207560A JP5205856B2 (en) | 2007-01-11 | 2007-08-09 | Power semiconductor device |
| JP2007207560 | 2007-08-09 | ||
| JP2007-207560 | 2007-08-09 |
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