CN107134490B - Vertical power device based on arc-shaped source field plate and arc-shaped drain field plate and manufacturing method thereof - Google Patents

Vertical power device based on arc-shaped source field plate and arc-shaped drain field plate and manufacturing method thereof Download PDF

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CN107134490B
CN107134490B CN201710198230.7A CN201710198230A CN107134490B CN 107134490 B CN107134490 B CN 107134490B CN 201710198230 A CN201710198230 A CN 201710198230A CN 107134490 B CN107134490 B CN 107134490B
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field plate
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毛维
石朋毫
边照科
郝跃
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Xidian University
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    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

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Abstract

The invention discloses a vertical power device based on an arc-shaped source field plate and an arc-shaped drain field plate, which comprises the following components from bottom to top: the Schottky source electrode comprises a Schottky drain electrode (11), a substrate (1), a drift layer (2), a pore diameter layer (3), two current blocking layers (4) of a secondary stepped structure, a pore diameter (5), a channel layer (6), a barrier layer (7) and a grid electrode (10), two source electrodes (9) are deposited on two sides of the barrier layer, two injection regions (8) are injected below the source electrodes, passivation layers (12) are wrapped in all regions except the bottom of the Schottky drain electrode, arc-shaped steps are respectively carved on the upper portion and the lower portion of the left side and the right side of each passivation layer, metal is deposited on the arc-shaped steps to form an arc-shaped source field plate (13) and an arc-shaped drain field plate (14), the arc-shaped source field plate, the arc-shaped drain field plate, the Schottky drain electrode and the passivation layers are all covered with protective.

Description

Vertical power device based on arc-shaped source field plate and arc-shaped drain field plate and manufacturing method thereof
Technical Field
The invention belongs to the technical field of microelectronics, and relates to a semiconductor device, in particular to a vertical power device based on an arc-shaped source field plate and an arc-shaped drain field plate, which can be used for a power electronic system.
Technical Field
The power semiconductor device is a core element of power electronic technology, and with the increasingly prominent energy and environmental problems, the development of a novel high-performance and low-loss power device becomes one of effective ways for improving the utilization rate of electric energy, saving energy and relieving the energy crisis. In the research of power devices, a severe restriction relationship exists between high speed, high voltage and low on-resistance, and the key for improving the overall performance of the device is to reasonably and effectively improve the restriction relationship. With the development of microelectronic technology, the performance of the traditional first-generation Si semiconductor and second-generation GaAs semiconductor power devices is close to the theoretical limit determined by the materials. In order to further reduce the chip area, improve the working frequency, improve the working temperature, reduce the on-resistance, improve the breakdown voltage, reduce the volume of the whole machine and improve the efficiency of the whole machine, the wide-bandgap semiconductor material represented by GaN is distinguished in the aspect of preparing high-performance power devices by virtue of the outstanding advantages of larger forbidden bandwidth, higher critical breakdown electric field, higher electron saturation drift velocity, stable chemical performance, high temperature resistance, radiation resistance and the like, and has huge application potential. Particularly, a lateral High Electron Mobility Transistor (HEMT) adopting a GaN-based heterojunction structure, namely a lateral GaN-based HEMT device, becomes a hot spot and a focus of domestic and foreign research and application due to the characteristics of low on-resistance, high breakdown voltage, high operating frequency and the like.
However, in the lateral GaN-based HEMT device, in order to obtain a higher breakdown voltage, the gate-drain pitch needs to be increased, which increases the device size and on-resistance, reduces the effective current density per chip area and chip performance, thereby resulting in an increase in chip area and development cost. In addition, in the lateral GaN-based HEMT device, the current collapse problem caused by a high electric field and a surface state is serious, and although there are many suppression measures at present, the current collapse problem has not been completely solved. In order to solve the above problems, researchers have proposed a vertical GaN-based current aperture heterojunction field effect Device, which is also a vertical power Device, see AlGaN/GaN current adaptive vertical electron transistors, IEEE Device Research Conference, pp.31-32,2002. The GaN-based current aperture heterojunction field effect device can improve the breakdown voltage by increasing the thickness of the drift layer, and avoid the problems of sacrificing the size and the on-resistance of the device, thereby realizing a high-power-density chip. And in the GaN-based current aperture heterojunction field effect device, a high electric field region is positioned in the semiconductor material body, so that the current collapse problem can be thoroughly eliminated. In 2004, Ilan Ben-Yaacov et al developed an AlGaN/GaN current aperture heterojunction field effect device by using the MOCVD regrowth channel technology after etching, the device did not use a passivation layer, the maximum output current was 750mA/mm, the transconductance was 120mS/mm, the breakdown voltage of the gates at both ends was 65V, and the current collapse effect was significantly suppressed,see AlGaN/GaN current adaptive vertical electron transducers with growth channels, Journal of Applied Physics, Vol.95, No.4, pp.2073-2078,2004. In 2012, Srabanti Chowdhury et al developed a GaN substrate-based current aperture heterojunction field effect device using a 3 μm drift layer with a maximum output current of 4kA · cm using a technique of Mg ion implantation current blocking layer in combination with plasma assisted MBE to regrow AlGaN/GaN heterojunction-2And an on-resistance of 2.2 m.OMEGA.cm2The breakdown voltage is 250V, and the current collapse inhibiting effect is good, see CAVET on Bulk GaN superstrates Achieveedwith MBE-Regrown AlGaN/GaN Layers to super Dispersion, IEEE Electron devices letters, Vol.33, No.1, pp.41-43,2012. In the same year, an enhanced GaN-based current aperture heterojunction field effect device proposed by Masahiro Sugimoto et al was licensed, see Transistor, US8188514B2,2012. In addition, in 2014, Hui Nie et al developed an enhanced GaN-based current aperture heterojunction field effect device based on a GaN substrate, the device had a threshold voltage of 0.5V, a saturation current of more than 2.3A, a breakdown voltage of 1.5kV, and an on-resistance of 2.2m Ω cm2See 1.5-kV and 2.2-m.OMEGA. -cm2Vertical GaN Transistors on Bulk-GaN Substrates,IEEEElectron Device Letters,Vol.35,No.9,pp.939-941,2014。
The traditional GaN-based current aperture heterojunction field effect device is based on a GaN-based wide bandgap semiconductor heterojunction structure, and comprises: the device comprises a substrate 1, a drift layer 2, an aperture layer 3, a left current blocking layer 4, a right current blocking layer 4, an aperture 5, a channel layer 6, a barrier layer 7 and a passivation layer 12, wherein the left current blocking layer and the right current blocking layer are symmetrical; two source electrodes 9 are deposited on two sides of the barrier layer 7, two implantation regions 8 are formed below the two source electrodes 9 through ion implantation, a grid electrode 10 is deposited on the barrier layer 7 between the source electrodes 9, a drain electrode 11 is deposited below the substrate 1, and a passivation layer 12 completely wraps all regions except the bottom of the drain electrode, as shown in fig. 1.
After more than ten years of theoretical and experimental researches, researchers find that inherent defects exist in the structure of the traditional GaN-based current aperture heterojunction field effect device, so that the electric field intensity distribution in the device is extremely uneven, and particularly the electric field intensity distribution near the lower part of the interface between a current blocking layer and an aperture regionThere are extremely high electric field peaks in the semiconductor material, causing premature device breakdown. This makes it difficult to achieve a continuous improvement in the breakdown voltage of the device by increasing the thickness of the n-type GaN drift layer in practical processes. Therefore, the breakdown voltage of the GaN-based current aperture heterojunction field effect device with the traditional structure is generally not high. In 2013, Zhongda Li et al studied a super junction-based enhancement-type GaN-based current aperture heterojunction field effect device by using a numerical simulation technology, and the research result shows that the super junction structure can effectively modulate the electric field distribution in the device, so that the electric field intensity in each part of the device in an off state tends to be uniformly distributed, therefore, the breakdown voltage of the device can reach 5-20 kV, and the breakdown voltage is 12.4kV when a 3-mum half-column width is adopted, while the on-resistance is only 4.2m omega cm2See Design and Simulation of 5-20-kV GaN Enhancement-Mode Vertical Superjunction HEMT, IEEE Transactions on Electron Desciences, Vol.60, No.10, pp.3230-3237,2013. The super-junction GaN-based current aperture heterojunction field effect device can theoretically obtain high breakdown voltage, can realize the continuous improvement of the breakdown voltage along with the increase of the thickness of the n-type GaN drift layer, and is a very effective high-power device structure with the highest breakdown voltage in the reported literature at home and abroad at present. However, the manufacturing process of the super junction structure is very difficult, and especially under the condition of a thick n-type GaN drift layer, the super junction structure with high performance can hardly be manufactured. In addition, in the GaN-based current aperture heterojunction field effect device adopting the super junction structure, when the device is turned on, extra on-resistance is generated near the super junction, and the on-resistance is continuously increased along with the increase of the thickness of the drift layer, so although the breakdown voltage of the device is increased along with the increase of the thickness of the drift layer, the on-resistance of the device is also correspondingly increased, and the contradiction between the breakdown voltage and the on-resistance in the device is not thoroughly solved. Therefore, the method has great significance in exploring, researching and developing a novel GaN-based current aperture heterojunction field effect device with simple manufacturing process, high breakdown voltage and small on-resistance.
With the expansion of the application field, in many technical fields such as electric vehicles, S-class power amplifiers, power management systems, and the like, in order to effectively implement power conversion and control, a high-performance power device with bidirectional blocking capability is urgently needed, i.e., the device not only needs to have strong forward blocking capability, i.e., forward breakdown voltage, but also needs to have strong reverse blocking capability, i.e., the device is expected to have high negative drain breakdown voltage, i.e., reverse breakdown voltage, in an off state.
The field plate structure becomes a mature and effective field termination technology for improving the forward breakdown voltage and reliability of the device in the transverse GaN-based HEMT device, and the technology can realize that the breakdown voltage of the device is continuously increased along with the length and structure change of the field plate. In recent years, the performance of lateral GaN-based HEMT Devices has been improved dramatically by using Field plate structures, see High Breakdown Voltage AlGaN-GaN Power-HEMT Design and High Current sensitivity Switching Behavior, IEEE Transactions on Electron Devices, Vol.50, No.12, pp.2528-2531,2003, and High Breakdown Voltage AlGaN-GaN HEMTs activated by multiple File sites, IEEE Electron Devices Letters, Vol.25, No.4, Electron 161-163,2004, and High Breakdown Voltage operated AlGaN/GaN HEMTs With segmented files, IEEE Electron Devices Letters, Vol.25, IEEE electronic Devices, Vol.27, Vol.713, Vol.3, Vol.25, and High Breakdown Voltage Switching Devices, Vol.27, Vol. 715,2006. Therefore, the field plate structure is introduced into the GaN-based current aperture heterojunction field effect device to improve the forward breakdown voltage of the device, and the GaN-based current aperture heterojunction field effect device has very important advantages. However, the field plate structure has not been successfully applied to the GaN-based current aperture heterojunction field effect device at home and abroad up to now, which is mainly because the inherent defect on the GaN-based current aperture heterojunction field effect device structure causes the strongest electric field peak in the drift layer of the device to be located near the interface between the current blocking layer and the aperture layer, and the electric field peak is far away from the surfaces on both sides of the drift layer, so the field plate structure can hardly play a role of effectively modulating the electric field distribution in the device, and the device performance is hardly improved even if the field plate structure is adopted in the GaN-based current aperture heterojunction field effect device.
In addition, the existing GaN-based current aperture heterojunction field effect devices all adopt ohmic drain electrodes, when a very low reverse voltage is applied to the drain electrode of the device, a current blocking layer in the device fails to work, so that a large drain-source leakage current is formed, and with the increase of the reverse voltage of the drain electrode, a gate of the device is also opened in a forward direction and passes through a large gate current, so that the device finally fails. Therefore, the existing GaN-based current aperture heterojunction field effect device can not realize the reverse blocking function, and even if the field plate structure is applied to the GaN-based current aperture heterojunction field effect device, the field plate structure has no effect on improving the reverse blocking characteristic of the device.
In conclusion, in view of the technical bottleneck, it is necessary and urgent to develop a high-performance vertical GaN-based current aperture heterojunction field effect device with excellent bidirectional blocking capability, and the device has important practical significance.
Disclosure of Invention
The invention aims to provide a vertical power device based on an arc-shaped source field plate and an arc-shaped drain field plate and a manufacturing method thereof, aiming at overcoming the defects of the prior art, so as to reduce the manufacturing difficulty of the device, improve the forward breakdown voltage and the reverse breakdown voltage of the device, realize the sustainable increase of the forward breakdown voltage and the reverse breakdown voltage, relieve the contradiction between the breakdown voltage and the on-resistance of the device and improve the breakdown characteristic and the reliability of the device.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
first, device structure
A vertical power device based on arc source field plate and arc drain field plate includes: the substrate 1, drift layer 2, aperture layer 3, two symmetrical current barrier layers 4, channel layer 6, barrier layer 7 and passivation layer 12, two source electrodes 9 have been deposited to both sides on the barrier layer 7, two injection regions 8 are formed through ion implantation below two source electrodes 9, deposit on the barrier layer 7 between the source electrodes 9 has grid 10, the deposit has schottky drain 11 below the substrate 1, passivation layer 12 wraps up in all areas except that schottky drain 11 bottom completely, form aperture 5 between two current barrier layers 4, its characterized in that:
the two current blocking layers 4 adopt a two-stage stepped structure formed by a first blocking layer 41 and a second blocking layer 42, and the second blocking layer 42 is positioned on the inner side of the first blocking layer 41;
the passivation layer 12, its both sides all adopt double arc step, carve active arc step in the upper portion region on passivation layer both sides promptly, and the lower part region is carved with hourglass arc step, wherein:
metal is deposited on each source arc step to form two symmetrical arc source field plates 13, and the arc source field plates 13 are electrically connected with the source electrode 9;
metal is deposited at each leakage arc step to form two symmetrical arc leakage field plates 14, and the arc leakage field plates 14 are electrically connected with the Schottky drain electrode 11;
the arc-shaped source field plate, the arc-shaped drain field plate, the schottky drain electrode and the passivation layer are all covered with a protective layer 15.
Second, the manufacturing method
The invention discloses a method for manufacturing a vertical power device based on an arc-shaped source field plate and an arc-shaped drain field plate and a manufacturing method thereof, which comprises the following steps:
A. in the presence of n-Epitaxial growth of n on a substrate 1 of GaN type material-A GaN semiconductor material having a thickness of 3 to 50 μm and a doping concentration of 1 × 1015～1×1018cm-3The drift layer 2;
B. an n-type GaN semiconductor material is epitaxially formed on the drift layer 2 to have a thickness of 1.2 to 3 μm and a doping concentration of 1 × 1015～1×1018cm-3The aperture layer 3;
C. a mask is formed on the aperture layer 3, and the implantation dose is 1 × 10 at both side positions in the aperture layer using the mask15～1×1016cm-2The p-type impurity of (1), two first barrier layers 41 having a thickness a of 1.2 to 3 μm and a width c of 0.2 to 1 μm are formed;
D. a mask is formed on the aperture layer 3 and the first barrier layer 41, and the implantation dose is 1X 10 at both sides of the aperture layer between the left and right first barrier layers 41 using the mask15～1×1016cm-2The p-type impurity of (2) is formed by forming two second barrier layers 42 and two first barrier layers with a thickness b of 0.3 to 1 [ mu ] m and a width d of 1.1a41 and two second barrier layers 42 form a current barrier layer 4 with a two-stage stepped structure, and an aperture 5 is formed between the two symmetrical current barrier layers 4;
E. extending GaN semiconductor materials on the two first barrier layers 41, the two second barrier layers 42 and the upper part of the aperture 5to form a channel layer 6 with the thickness of 0.04-0.2 mu m;
F. extending a GaN-based wide bandgap semiconductor material on the upper part of the channel layer 6 to form a barrier layer 7 with the thickness of 5-50 nm;
G. a mask was formed on the upper part of the barrier layer 7, and the implantation dose was 1X 10 on both sides of the barrier layer using the mask15～1×1016cm-2The n-type impurity of (2) to make an implanted region 8, wherein the depth of both implanted regions is greater than the thickness of the barrier layer and less than the total thickness of the channel layer 6 and the barrier layer;
H. a mask is manufactured on the upper parts of the two injection regions 8 and the upper part of the barrier layer 7 between the two injection regions, and metal is deposited on the upper parts of the two injection regions 8 by using the mask to manufacture a source electrode 9;
I. a mask is manufactured on the upper portion of the barrier layer 7 between the source electrode 9 and the two injection regions, metal is deposited on the upper portion of the barrier layer 7 between the two injection regions by using the mask, and a grid electrode 10 is manufactured;
J. depositing metal on the back of the substrate 1 to manufacture a Schottky drain electrode 11;
K. depositing an insulating medium material in all the other areas except the bottom of the Schottky drain electrode 11 to form a wrapped passivation layer 12;
l, manufacturing a mask on the upper part of the passivation layer 12, etching the upper parts of the passivation layer 12 on the left side and the right side by using the mask to the same horizontal height with the lower edge of the current blocking layer, and forming an upper platform;
m, manufacturing a mask on the upper part of the passivation layer 12 with the upper platforms engraved on the left side and the right side, and etching the upper platforms on the left side and the right side of the passivation layer 12 by using the mask to form source arc-shaped steps; the source arc step is positioned at a part below the lower edge of the first barrier layer 41 at the same horizontal height, the vertical distance between any point of the surface of the source arc step and the lower edge of the first barrier layer 41 is f, the horizontal distance between the source arc step and the drift layer 2 is e, and the approximate relation f is 9.5-10.5exp (-0.6 e); the surface of the source arc step and the lower edge of the first barrier layer 41 are at a horizontal height, and the horizontal distance between the source arc step and the drift layer 2 is g;
manufacturing a mask on the upper part of a passivation layer 12 with two source arc-shaped steps, depositing metal on the source arc-shaped steps on the left side and the right side of the passivation layer by using the mask, wherein the height of the upper edge of the deposited metal is higher than or equal to that of the lower edge of a first barrier layer 41, forming two arc-shaped source field plates 13 which are symmetrical left and right, and electrically connecting the arc-shaped source field plates 13 on the two sides with a source electrode 9;
covering an insulating medium material on the upper parts of the arc-shaped source field plate 13 and the passivation layer 12 to protect the arc-shaped source field plate;
p. making a mask on the back of the schottky drain 11 and the back of the passivation layer 12, etching the left and right sides of the back of the passivation layer 12 by using the mask to form a drain arc-shaped step, wherein the lower boundary of the drain arc-shaped step is aligned with the lower boundary of the schottky drain 11, the drain arc-shaped step is positioned on the part of the upper boundary of the schottky drain above the same horizontal height, the vertical distance between the surface of the drain arc-shaped step and the lower boundary of the substrate 1 is q, the horizontal distance between the surface of the drain arc-shaped step and the drift layer 2 is p, the relationship q is approximately satisfied, and is 5.5+2.5ln (p +0.06), and the horizontal distance h between the surface of the drain arc-shaped step and the upper boundary of the schottky drain at the same horizontal height and the drift layer 2 is;
manufacturing masks on the back of the Schottky drain electrode 11 and the back of the arc-shaped leakage step, depositing metal on the arc-shaped leakage step on the left side and the right side by using the masks to form two arc-shaped leakage field plates 14 which are symmetrical left and right, electrically connecting the arc-shaped leakage field plates 14 on the two sides with the Schottky drain electrode 11, and enabling the lower edge of each arc-shaped leakage field plate to be lower than or equal to the upper edge of the Schottky drain electrode 11;
and R, covering an insulating medium material below the arc-shaped drain field plate, the Schottky drain electrode and the passivation layer to protect the arc-shaped drain field plate, wherein the insulating medium material in the step and the insulating medium material covered in the step O jointly form a protective layer 15, and the whole device is manufactured.
Compared with the traditional GaN-based current aperture heterojunction field effect device, the device has the following advantages:
a. a continuous increase in forward breakdown voltage is achieved.
The invention adopts a two-stage step-shaped current blocking layer, so that an electric field peak is generated near the lower part of the interface of a first blocking layer, a second blocking layer and an aperture layer in the device, and the electric field peak value corresponding to the first blocking layer is larger than the electric field peak value corresponding to the second blocking layer; because the electric field peak of the first barrier layer is very close to the surfaces of the two sides of the drift layer, the electric field peaks near the surfaces of the two sides of the drift layer can be effectively modulated by using the arc-shaped source field plate so as to form a continuous and smooth higher electric field region near the surfaces of the two sides of the drift layer at the arc-shaped source field plate;
by adjusting the horizontal distance between the source arc-shaped step and the drift layer, the size and doping of the current blocking layer and the like, the electric field peak value near the lower part of the interface of the current blocking layer and the aperture layer is approximately equal to the electric field value near the surfaces of the two sides of the drift layer corresponding to the arc-shaped source field plate and is smaller than the breakdown electric field of the GaN-based wide bandgap semiconductor material, so that the forward breakdown voltage of the device is improved, and the continuous increase of the forward breakdown voltage can be realized by increasing the length of the arc-shaped source field plate.
b. A continuous increase in reverse breakdown voltage is achieved.
The invention adopts the arc-shaped drain field plate, and effectively modulates the electric field distribution in the drift layer by utilizing the arc-shaped drain field plate, so that the area of a high electric field area in the drift layer of the device is obviously increased, and continuous and smooth higher electric field areas can be formed near the surfaces of two sides of the drift layer area corresponding to the arc-shaped drain field plate;
by adjusting the thickness of the passivation layer between the arc-shaped leakage field plate and the drift layer, the size of the arc-shaped leakage field plate and the like, the electric field values near the surfaces of the two sides of the drift layer corresponding to the arc-shaped leakage field plate are approximately equal and are smaller than the breakdown electric field of the GaN-based wide bandgap semiconductor material, so that the reverse breakdown voltage of the device is improved, and the continuous increase of the breakdown voltage can be realized by increasing the length of the arc-shaped leakage field plate.
c. The on-resistance of the device is almost constant while the breakdown voltage of the device is increased.
According to the invention, the breakdown voltage of the device is improved by adopting the arc-shaped field plates on two sides of the device, and as the field plates do not influence the on-resistance of the device, when the device is switched on, only a depletion region generated by the current blocking layer and a depletion region near the Schottky drain electrode, namely a high-resistance region, exist in the drift layer in the device, and other depletion regions are not introduced, so that the forward breakdown voltage and the reverse breakdown voltage of the device can be continuously increased by adjusting the sizes of the arc-shaped source field plate and the arc-shaped drain field plate, and the on-resistance is almost kept constant.
d. The process is simple and easy to realize, and the yield is improved.
In the device structure, the arc-shaped field plate is manufactured by etching the arc-shaped steps in the passivation layers on the two sides of the drift layer and depositing metal, the process is simple, the semiconductor material in the device cannot be damaged, the problem of process complication caused by the adoption of a super-junction GaN-based current aperture heterojunction field effect device structure is solved, and the yield of the device is greatly improved.
The technical contents and effects of the present invention are further explained below with reference to the drawings and examples.
Drawings
FIG. 1 is a block diagram of a conventional GaN-based current aperture heterojunction field effect device;
fig. 2 is a structural diagram of a vertical power device based on an arc-shaped source field plate and an arc-shaped drain field plate according to the present invention;
FIG. 3 is a flow chart of the present invention for fabricating a vertical power device based on an arc-shaped source field plate and an arc-shaped drain field plate;
FIG. 4 is a diagram of the vertical electric field distribution at the right edge of the drift layer of a device under forward breakdown conditions simulated for a device of the present invention;
fig. 5 is a diagram showing the vertical electric field distribution at the right edge of the drift layer of the device under reverse breakdown conditions simulated for the device of the present invention.
Detailed Description
Referring to fig. 2, the vertical power device based on the arc-shaped source field plate and the arc-shaped drain field plate of the present invention is based on a GaN-based wide bandgap semiconductor heterojunction structure, and includes: the Schottky barrier diode comprises a substrate 1, a drift layer 2, an aperture layer 3, two symmetrical current blocking layers 4, a channel layer 6, a barrier layer 7 and a passivation layer 12, wherein two source electrodes 9 are deposited on two sides of the barrier layer 7, two injection regions 8 are formed below the two source electrodes 9 through ion injection, a grid electrode 10 is deposited on the barrier layer 7 between the source electrodes 9, a Schottky drain electrode 11 is deposited below the substrate 1, and the passivation layer 12 completely wraps all regions except the bottom of the Schottky drain electrode 11, wherein:
the substrate 1 is n-A type GaN material;
the drift layer 2 is positioned on the upper part of the substrate 1, and has the thickness of 3-50 mu m and the doping concentration of 1 multiplied by 1015～1×1018cm-3；
The aperture layer 3 is positioned on the upper part of the drift layer 2, the thickness of the aperture layer is 1.2-3 mu m, and the doping concentration is 1 multiplied by 1015～1×1018cm-3；
The current blocking layer 4 is a two-step structure formed by a first blocking layer 41 and a second blocking layer 42, wherein: the two first barrier layers 41 are positioned at the left side and the right side in the aperture layer 3, the two second barrier layers 42 are positioned at the inner sides of the two first barrier layers 41, and each barrier layer is doped in a p type manner; the thickness a of the first barrier layer 41 is 1.2-3 μm, the width c is 0.2-1 μm, the thickness b of the second barrier layer 42 is 0.3-1 μm, the width d is 1.1a, and an aperture 5 is formed between the two symmetrical current barrier layers 4;
the channel layer 6 is positioned above the two current blocking layers 4 and the aperture 5, and the thickness of the channel layer is 0.04-0.2 mu m;
the barrier layer 7 is positioned on the upper part of the channel layer 6 and is composed of a plurality of layers of same or different GaN-based wide bandgap semiconductor materials, and the thickness of the barrier layer is 5-50 nm;
the depth of the two injection regions 8 is larger than the thickness of the barrier layer and smaller than the total thickness of the channel layer 6 and the barrier layer;
the overlapping length of the grid electrode 10 and the two current blocking layers 4 in the horizontal direction is more than 0 μm;
the Schottky drain electrode 11 adopts a Schottky structure;
the passivation layer 12 on both sides of the device adopts double arc steps on both sides, i.e. an active arc step is carved on the upper region on both sides of the passivation layer, and a leaky arc step is carved on the lower region, wherein:
metal is deposited on each source arc step to form two symmetrical arc source field plates 13, and the arc source field plates 13 are electrically connected with the source electrode 9; the source arc-shaped step is positioned at the part below the lower edge of the first barrier layer 41 at the same horizontal height, the vertical distance between any point of the surface of the source arc-shaped step and the lower edge of the first barrier layer 41 is f, the horizontal distance between the source arc-shaped step and the drift layer 2 is e, and approximately satisfies the relation that f is 9.5-10.5exp (-0.6e), and f is more than 0 mu m and less than or equal to 9 mu m; the horizontal distance g between the source arc step surface and the lower edge of the first barrier layer 41 at the same level is 0.18 μm.
Metal is deposited at each leakage arc-shaped step to form two symmetrical arc-shaped leakage field plates 14, the arc-shaped leakage field plates 14 are electrically connected with the Schottky drain electrode 11, the lower boundary of each leakage arc-shaped step is aligned with the lower boundary of the Schottky drain electrode 11, the leakage arc-shaped steps are positioned on the part of the upper boundary of the Schottky drain electrode above the same horizontal height, the vertical distance between any point of the surface of each leakage arc-shaped step and the lower boundary of the substrate 1 is q, the horizontal distance between the leakage arc-shaped step and the drift layer 2 is p, the relation q is approximately satisfied, wherein the q is 5.5+2.5ln (p +0.06), and the q is more than 0 mu m and less than or equal to; the surface of the arc-shaped step of the drain and the upper boundary of the Schottky drain are positioned at the same horizontal height, the horizontal distance from the surface of the arc-shaped step of the drain to the drift layer 2 is h, and h is 0.05 mu m;
the height of the upper edge of the arc-shaped source field plate 13 is equal to or higher than that of the lower edge of the first barrier layer 41, and the height of the lower boundary of the arc-shaped drain field plate 14 is equal to or lower than that of the upper boundary of the Schottky drain electrode 11;
the arc-shaped source field plate, the arc-shaped drain field plate, the Schottky drain electrode and the passivation layer are covered with a protective layer 15;
the passivation layer 12 and the protective layer 15 are made of SiO2、SiN、Al2O3、Sc2O3、HfO2、TiO2Or other insulating dielectric material.
Referring to fig. 3, the process of manufacturing a vertical power device based on an arc-shaped source field plate and an arc-shaped drain field plate according to the present invention provides the following three embodiments:
the first embodiment is as follows: by means of SiO2The material is used as a passivation layer and a protective layer to manufacture the arc-shaped source field plate and arc-shaped drain field plate-based vertical power device.
Step 1. epitaxial n on a substrate 1-Type GaN, forming a drift layer 2, as shown in fig. 3 a.
By using n-GaN type substrate 1 is prepared by epitaxial growing on substrate 1 with thickness of 3 μm and doping concentration of 1 × 10 by using metal organic chemical vapor deposition15cm-3N of (A) to (B)-A GaN semiconductor material of type forming a drift layer 2, wherein:
the epitaxial process conditions are as follows: the temperature was 950 ℃ and the pressure was 40Torr, as SiH4The hydrogen flow is 4000sccm, the ammonia flow is 4000sccm, and the gallium source flow is 100 mu mol/min.
And 2, extending n-type GaN on the drift layer to form an aperture layer 3, as shown in figure 3 b.
The drift layer 2 is epitaxially grown to a thickness of 1.2 μm and a doping concentration of 1 × 10 by using MOCVD15cm-3Forming the aperture layer 3, wherein:
the epitaxial process conditions are as follows: the temperature was 950 ℃ and the pressure was 40Torr, as SiH4The hydrogen flow is 4000sccm, the ammonia flow is 4000sccm, and the gallium source flow is 100 mu mol/min.
Step 3, a first barrier layer 41 is fabricated, as shown in fig. 3 c.
3a) Making a mask on the aperture layer 3;
3b) using ion implantation technique, the implantation dose is 1 × 10 at two side positions in the aperture layer15cm-2The two first barrier layers 41 having a thickness a of 1.2 μm and a width c of 0.2 μm were prepared as the p-type impurity Mg of (1).
Step 4. make the second barrier layer 42, as shown in fig. 3 d.
4a) A mask is made on the aperture layer 3 and the two first barrier layers 41;
4b) using ion implantation technique to form first barrier layers on left and rightThe implantation dose on both sides in the aperture layer 3 between 41 is 1 × 1015cm-2The two second barrier layers 42 with the thickness b of 0.3 μm and the width d of 1.32 μm are manufactured, the two first barrier layers and the two second barrier layers form two symmetrical current barrier layers 4 with a two-stage step structure, and the aperture 5 is formed between the left current barrier layer 4 and the right current barrier layer 4.
And 5, manufacturing a channel layer 6 by epitaxial GaN material, as shown in figure 3 e.
Forming a channel layer 6 by epitaxially growing a GaN material having a thickness of 0.04 μm on the upper portions of the two first barrier layers 41, the two second barrier layers 42, and the aperture 5 using a molecular beam epitaxy technique;
the molecular beam epitaxy technology comprises the following process conditions: vacuum degree of 1.0X 10 or less-10mbar, radio frequency power of 400W, and N as reactant2And a high purity Ga source.
Step 6, extending Al0.5Ga0.5N, the barrier layer 7 is produced, as shown in fig. 3 f.
Epitaxial growth of 5nm thick Al on the channel layer 6 using molecular beam epitaxy0.5Ga0.5N material forming barrier layer 7, wherein:
the process conditions of molecular beam epitaxy are as follows: vacuum degree of 1.0X 10 or less-10mbar, radio frequency power of 400W, and N as reactant2A high-purity Ga source and a high-purity Al source;
step 7, manufacturing a left injection region 8 and a right injection region 8, as shown in fig. 3 g.
7a) A mask is made on the barrier layer 7;
7b) the implantation dose is 1 × 10 on both sides in the barrier layer by using ion implantation technique15cm-2Forming an implantation region 8 having a depth of 0.01 μm;
7c) the rapid thermal annealing was performed at a temperature of 1200 ℃.
And 8, manufacturing a source electrode 9, as shown in fig. 3 h.
8a) A mask is made on the upper parts of the two implantation regions 8 and the upper part of the barrier layer 7 between the two implantation regions;
8b) using electron beam evaporation techniques, a Ti/Au/Ni combination metal is deposited on top of the two implanted regions, forming the source 9, wherein: the metals deposited from bottom to top are respectively 0.02 μm of Ti, 0.3 μm of Au and 0.05 μm of Ni;
the process conditions of the electron beam evaporation are as follows: vacuum degree less than 1.8X 10-3Pa, power range of 200-1000W, evaporation rate less than
Figure BDA0001257932340000111
Step 9, manufacturing the grid 10, as shown in fig. 3 i.
9a) A mask is made on the upper part of the source electrode 9 and the upper part of the barrier layer 7 between the two injection regions;
9b) using electron beam evaporation techniques, a Ni/Au/Ni combination metal is deposited on the barrier layer 7 between the two implanted regions, forming a gate 10, in which: ni is 0.02 mu m, Au is 0.2 mu m, Ni is 0.04 mu m respectively deposited from bottom to top, and the overlapping length of the grid 10 and the two second barrier layers 42 in the horizontal direction is 0.3 mu m;
the process conditions of the electron beam evaporation are as follows: vacuum degree less than 1.8X 10-3Pa, power range of 200-1000W, evaporation rate less than
Figure BDA0001257932340000112
Step 10, manufacturing the schottky drain 11, as shown in fig. 3 j.
Using an electron beam evaporation technology to sequentially deposit W, Au and Ni on the back of the whole substrate 1 to form W/Au/Ni combined metal, and finishing the manufacture of the Schottky drain electrode 11, wherein the thickness of W is 0.02 mu m, the thickness of Au is 0.7 mu m, and the thickness of Ni is 0.05 mu m;
the process conditions adopted for depositing the metal are as follows: vacuum degree less than 1.8X 10-3Pa, power range of 200-1000W, evaporation rate less than
Figure BDA0001257932340000113
Step 11. depositing SiO2Insulating dielectric material forming an encapsulating passivation layer 12, fig. 3 k.
Using plasma enhanced chemical vapor deposition techniques except for SchottkySiO is deposited in all regions except the bottom of the drain electrode 112An insulating dielectric material forming an encapsulated passivation layer 12, wherein:
the process conditions for depositing the passivation layer are as follows: n is a radical of2O flow rate of 850sccm, SiH4The flow rate was 200sccm, the temperature was 250 ℃, the radio frequency power was 25W, and the pressure was 1100 mTorr.
And step 12, etching upper platforms on the left side and the right side in the passivation layer, as shown in figure 3 l.
12a) A mask is manufactured on the upper part of the passivation layer 12;
12b) by using the reactive ion etching technology, etching is carried out in the passivation layer on the upper parts of the left side and the right side of the passivation layer 12, the etching is carried out to the same horizontal height with the lower edge of the current barrier layer 4, and a left upper platform and a right upper platform are formed, wherein:
the process conditions of the reactive ion etching are as follows: CF (compact flash)4The flow rate was 45sccm, O2The flow rate is 5sccm, the pressure is 15mTorr, and the power is 250W.
And step 13, manufacturing a source arc-shaped step as shown in figure 3 m.
13a) A mask is manufactured on the upper part of the passivation layer 12 with the upper platforms carved on the left side and the right side;
13b) etching in the upper platforms on the left and right sides of the passivation layer 12 by using a reactive ion etching technology to form a source arc-shaped step, wherein the source arc-shaped step is positioned at a part below the lower edge of the first barrier layer 41 at the same horizontal height, any point on the surface of the source arc-shaped step is at a vertical distance f from the lower edge of the first barrier layer 41 and at a horizontal distance e from the drift layer 2, and approximately satisfies the relationship of f being 9.5-10.5exp (-0.6e), f being at most 1 μm, the surface of the source arc-shaped step and the lower edge of the first barrier layer 41 are positioned at the same horizontal height, and the horizontal distance g from the drift layer 2 is 0.18 μm;
the process conditions of the reactive ion etching are as follows: CF (compact flash)4The flow rate was 45sccm, O2The flow rate is 5sccm, the pressure is 15mTorr, and the power is 250W.
Step 14, making the arc-shaped source field plate 13, as shown in fig. 3 n.
14a) Manufacturing a mask on the upper part of the passivation layer 12 with two source arc steps;
14b) make itBy electron beam evaporation, i.e. at vacuum levels less than 1.8X 10-3Pa, power range of 200-1000W, evaporation rate less than
Figure BDA0001257932340000121
Under the process conditions of (1), depositing metal Ni on the source arc steps on the left side and the right side, manufacturing two arc source field plates 13 which are symmetrical left and right, wherein the height of the upper edge of each arc source field plate 13 is 0.2 mu m higher than that of the lower edge of the first barrier layer 41, and electrically connecting the arc source field plates on the two sides with the source electrode.
Step 15, depositing SiO above the arc-shaped source field plate and the passivation layer2Insulating dielectric material, as in fig. 3 o.
Depositing SiO over the arc-shaped source field plate and over the passivation layer using plasma enhanced chemical vapor deposition techniques2An insulating dielectric material;
the process conditions for depositing the passivation layer are as follows: n is a radical of2O flow rate of 850sccm, SiH4The flow rate was 200sccm, the temperature was 250 ℃, the radio frequency power was 25W, and the pressure was 1100 mTorr.
And step 16, manufacturing a leaky arc-shaped step as shown in figure 3 p.
16a) Manufacturing a mask on the back of the Schottky drain electrode 11 and the back of the passivation layer 12;
16b) etching in the left and right sides of the back of the passivation layer 12 by using a reactive ion etching technology to form a leakage arc-shaped step, wherein the leakage arc-shaped step is positioned at a part above the same horizontal height of the upper boundary of the Schottky drain, any point on the surface of the leakage arc-shaped step is aligned with the vertical distance q of the lower boundary of the substrate 1 and the horizontal distance p of the drift layer 2, and approximately satisfies the relation q-5.5 +2.5ln (p +0.06), the lower boundary of the leakage arc-shaped step is aligned with the lower boundary of the Schottky drain 11, the horizontal distance h between the surface of the leakage arc-shaped step and the part of the upper boundary of the Schottky drain at the same horizontal height is 0.05 μm from the drift layer 2, and the maximum q is 1 μm, wherein:
the process conditions of the reactive ion etching are as follows: CF (compact flash)4The flow rate was 45sccm, O2The flow rate is 5sccm, the pressure is 15mTorr, and the power is 250W.
Step 17, manufacturing the arc-shaped drain field plate 14, as shown in fig. 3 q.
17a) Manufacturing a mask on the back of the Schottky drain electrode 11 and the back of the passivation layer 12;
17b) using electron beam evaporation techniques, i.e. at vacuum levels of less than 1.8X 10-3Pa, power range of 200-1000W, evaporation rate less than
Figure BDA0001257932340000131
Under the process conditions of (3), depositing metal Ni on the left and right arc-shaped leakage steps to manufacture two arc-shaped leakage field plates 14 which are symmetrical left and right, wherein the height of the lower boundary of the arc-shaped leakage field plate 14 is 0.2 mu m lower than that of the upper boundary of the Schottky drain electrode 11, and the leakage field plates at the two sides are electrically connected with the Schottky drain electrode.
Step 18, filling SiO below the arc-shaped drain field plate, the Schottky drain electrode and the passivation layer2Insulating the dielectric material, completing the fabrication of the protective layer 15, as shown in fig. 3 r.
Covering the arc-shaped drain field plate, the Schottky drain electrode and the passivation layer with SiO by using a plasma enhanced chemical vapor deposition technology2The insulating dielectric material of the step and the insulating dielectric material deposited in the step 15 jointly form a protective layer 15, and the manufacture of the whole device is completed;
the process conditions for depositing the passivation layer are as follows: n is a radical of2O flow rate of 850sccm, SiH4The flow rate was 200sccm, the temperature was 250 ℃, the radio frequency power was 25W, and the pressure was 1100 mTorr.
Example two: and adopting SiN materials as a passivation layer and a protective layer to manufacture the arc-shaped source field plate and arc-shaped drain field plate-based vertical power device.
First step, epitaxially n on a substrate 1-Type GaN, forming a drift layer 2, as shown in fig. 3 a.
At a temperature of 1000 deg.C, a pressure of 45Torr, with SiH4Is a doping source, the hydrogen flow is 4400sccm, the ammonia flow is 4400sccm, and the gallium source flow is 110 mu mol/min-GaN type substrate 1 is prepared by epitaxially growing a layer of 20 μm and a layer of 1 × 10 dopant concentration on substrate 1 by use of metal-organic chemical vapor deposition17cm-3N of (A) to (B)-And forming a GaN material to complete the manufacture of the drift layer 2.
And secondly, the n-type GaN is epitaxially grown on the drift layer to form an aperture layer 3, as shown in FIG. 3 b.
At a temperature of 1000 deg.C, a pressure of 45Torr, with SiH4Is a doping source, the hydrogen flow is 4400sccm, the ammonia flow is 4400sccm, the gallium source flow is 110 mu mol/min, the metal organic chemical vapor deposition technology is used, the epitaxial thickness is 1.5 mu m, the doping concentration is 1 multiplied by 10 on the drift layer 217cm-3The aperture layer 3 is completed.
Third, first barrier layer 41 is formed, as shown in fig. 3 c.
3.1) making a mask on the aperture layer 3;
3.2) Using ion implantation technique, the implantation dose is 5X 10 at two side positions within the aperture layer15cm-2The two first barrier layers 41 having a thickness a of 1.5 μm and a width c of 0.4 μm were prepared as the p-type impurity Mg of (1).
Fourth, a second barrier layer 42 is formed, as shown in fig. 3 d.
4.1) making a mask on the aperture layer 3 and the two first barrier layers 41;
4.2) Using ion implantation technique, the implantation dose was 5X 10 on both sides within the aperture layer 3 between the left and right first barrier layers 4115cm-2The two second barrier layers 42 with the thickness b of 0.65 μm and the width d of 1.65 μm are formed, the two first barrier layers and the two second barrier layers form two symmetrical current barrier layers 4 with a two-step structure, and the aperture 5 is formed between the left current barrier layer 4 and the right current barrier layer 4.
And fifthly, epitaxial growth of GaN material is carried out to manufacture the channel layer 6, as shown in figure 3 e.
Under the vacuum degree of 1.0 multiplied by 10-10mbar, radio frequency power of 400W, and N as reactant2And under the process condition of the high-purity Ga source, a molecular beam epitaxy technology is used for epitaxially growing a GaN material with the thickness of 0.1 mu m on the first barrier layer 41, the second barrier layer 42 and the upper part of the aperture 5, so that the channel layer 6 is manufactured.
Sixth step, epitaxial Al0.3Ga0.7N, the barrier layer 7 is produced, as shown in fig. 3 f.
Under the vacuum degree of 1.0 multiplied by 10-10mbar, radio frequency power of 400W, and N as reactant2And high-purity Ga source and high-purity Al source, and epitaxially growing Al with a thickness of 20nm on the channel layer 6 by using molecular beam epitaxy technology0.3Ga0.7And N material, and finishing the manufacture of the barrier layer 7.
The seventh step is to fabricate the left and right two implantation regions 8, as shown in FIG. 3 g.
7.1) manufacturing a mask on the upper part of the barrier layer 7;
7.2) Using ion implantation technique, the implant dose was 6X 10 on both sides within the barrier layer15cm-2Forming two implanted regions 8 with a depth of 0.03 μm;
7.3) carrying out rapid thermal annealing at a temperature of 1200 ℃.
And the eighth step, manufacturing the source 9, as shown in fig. 3 h.
8.1) making a mask on the upper part of the two implantation regions 8 and on the upper part of the barrier layer 7 between the two implantation regions;
8.2) in a vacuum of less than 1.8X 10-3Pa, power range of 200-1000W, evaporation rate less than
Figure BDA0001257932340000151
Using electron beam evaporation techniques, depositing a Ti/Au/Ni composite metal on top of the two implanted regions to form the source electrode 9, wherein: the deposited combined metals are respectively Ti, Au and Ni from bottom to top, and the thicknesses of the combined metals are 0.02 mu m, 0.3 mu m and 0.05 mu m in sequence.
Ninth, the gate 10 is fabricated as shown in fig. 3 i.
9.1) making a mask on the upper part of the source electrode 9 and the upper part of the barrier layer 7 between the two injection regions;
9.2) in vacuum of less than 1.8X 10-3Pa, power range of 200-1000W, evaporation rate less than
Figure BDA0001257932340000152
Using electron beam evaporation techniques, on the barrier layer 7 between the two implanted regionsDepositing Ni/Au/Ni combination metal to form a grid electrode 10, wherein: the thickness of the metal Ni deposited from bottom to top is 0.02 μm, the thickness of Au is 0.2 μm, the thickness of Ni is 0.04 μm, and the overlapping length of the gate electrode 10 and the two second barrier layers 42 in the horizontal direction is 0.35 μm.
Step ten, the schottky drain 11 is fabricated as shown in fig. 3 j.
Under the vacuum degree of less than 1.8 multiplied by 10-3Pa, power range of 200-1000W, evaporation rate less than
Figure BDA0001257932340000153
Under the process conditions of (1), using an electron beam evaporation technology, depositing Ni, Au and Ni in sequence on the back of the whole substrate 1 to form Ni/Au/Ni combined metal, and completing the manufacture of the Schottky drain electrode 11, wherein the thickness of Ni is 0.02 μm, the thickness of Au is 0.7 μm, and the thickness of Ni is 0.05 μm.
A tenth step deposits SiN insulating dielectric material to form a wrapped passivation layer 12, as shown in fig. 3 k.
In the presence of NH as gas3、N2And SiH4And SiN insulating dielectric materials are deposited in all the areas except the bottom of the Schottky drain electrode 11 by using a plasma enhanced chemical vapor deposition technology under the process conditions that the gas flow is 2.5sccm, 950sccm and 250sccm respectively, and the temperature, the radio frequency power and the pressure are 300 ℃, 25W and 950mTorr respectively to form a wrapped passivation layer 12.
The twelfth step etches the upper mesa on both left and right sides within the passivation layer as shown in FIG. 3 l.
12.1) making a mask on the upper part of the passivation layer 12;
12.2) in CF4The flow rate was 45sccm, O2Etching the passivation layer on the upper parts of the left side and the right side of the passivation layer 12 to the same horizontal height with the lower edge of the current blocking layer 4 by using a reactive ion etching technology under the process conditions of 5sccm flow, 15mTorr pressure and 250W power to form a left upper platform and a right upper platform.
And a thirteenth step, manufacturing a source arc-shaped step, as shown in fig. 3 m.
13.1) manufacturing masks on the upper parts of the passivation layers 12 with the upper platforms carved on the left and right sides;
13.2) in CF4The flow rate was 45sccm, O2Etching in upper platforms on the left side and the right side of a passivation layer 12 under the process conditions of 5sccm, 15mTorr of pressure and 250W of power by using a reactive ion etching technology to form a source arc-shaped step, wherein the source arc-shaped step is positioned on the lower edge of a first barrier layer 41 at a part below the same horizontal height, the vertical distance between any point of the surface of the source arc-shaped step and the lower edge of the first barrier layer 41 is f, the horizontal distance between the source arc-shaped step and a drift layer 2 is e, and approximately satisfies the relationship of f being 9.5-10.5exp (-0.6e), f is at most 4 μm, the surface of the source arc-shaped step and the lower edge of the first barrier layer 41 at the same horizontal height, and the horizontal distance g between the source arc-shaped step and the drift layer 2 is 0.18 μm;
and a fourteenth step, manufacturing an arc-shaped source field plate 13, as shown in fig. 3 n.
14.1) manufacturing a mask on the upper part of the passivation layer 12 with two active arc steps;
14.2) in vacuum of less than 1.8X 10-3Pa, power range of 200-1000W, evaporation rate less than
Figure BDA0001257932340000161
Under the process conditions of (1), depositing metal Ti on source arc steps on the left side and the right side of a passivation layer by using an electron beam evaporation technology, manufacturing two arc-shaped source field plates 13 which are symmetrical left and right, wherein the height of the upper edge of each arc-shaped source field plate 13 is 0.3 mu m higher than that of the lower edge of the first barrier layer 41, and electrically connecting the arc-shaped source field plates on the two sides with the source electrode.
Fifteenth step, SiN insulating dielectric material is deposited over the arc-shaped source field plate and over the passivation layer, as shown in fig. 3 o.
In the presence of NH as gas3、N2And SiH4And SiN insulating dielectric materials are deposited above the arc-shaped source field plate and the passivation layer by using a plasma enhanced chemical vapor deposition technology under the process conditions that the gas flow is 2.5sccm, 950sccm and 250sccm respectively, and the temperature, the radio frequency power and the pressure are 300 ℃, 25W and 950mTorr respectively.
Sixthly, manufacturing a leakage arc-shaped step as shown in figure 3 p.
16.1) making a mask on the back of the Schottky drain electrode 11 and the back of the passivation layer 12;
16.2) in CF4The flow rate was 45sccm, O2Etching in the left side and the right side of the back surface of the passivation layer 12 by using a reactive ion etching technology under the process conditions of 5sccm flow, 15mTorr pressure and 250W power to form a leakage arc-shaped step, wherein the leakage arc-shaped step is positioned on the part of the upper boundary of the Schottky drain electrode above the same horizontal height, the vertical distance q between any point of the surface of the leakage arc-shaped step and the lower boundary of the substrate 1 and the horizontal distance p between the leakage arc-shaped step and the drift layer 2 approximately satisfy the relation q is 5.5+2.5ln (p +0.06), the lower boundary of the leakage arc-shaped step is aligned with the lower boundary of the Schottky drain electrode 11, the horizontal distance h between the surface of the leakage arc-shaped step and the upper boundary of the Schottky drain electrode at the same horizontal height and the drift layer 2 is 0.05 mu m, and the q is maximally 3.5.
Seventeenth, an arc-shaped drain field plate 14 is manufactured, as shown in fig. 3 q.
17.1) manufacturing a mask on the back surface of the Schottky drain electrode 11 and the back surface of the passivation layer 12;
17.2) using electron beam evaporation, i.e. in a vacuum of less than 1.8X 10-3Pa, power range of 200-1000W, evaporation rate less than
Figure BDA0001257932340000171
Under the process conditions of (3), depositing metal Ti on the left and right arc-shaped leakage steps to manufacture two arc-shaped leakage field plates 14 which are symmetrical left and right, wherein the height of the lower boundary of the arc-shaped leakage field plate 14 is 0.3 mu m lower than that of the upper boundary of the Schottky drain electrode 11, and the leakage field plates at the two sides are electrically connected with the Schottky drain electrode.
Eighteenth, filling SiN insulating medium material under the arc-shaped drain field plate, the schottky drain electrode and the passivation layer to complete the manufacture of the protection layer 15, as shown in fig. 3 r.
In the presence of NH as gas3、N2And SiH4The gas flow is respectively 2.5sccm, 950sccm and 250sccm, the temperature, the radio frequency power and the pressure are respectively 300 ℃, 25W and 950mTorr, and a plasma enhanced chemical vapor deposition technology is used for forming an arc-shaped leakage field plate and a Schottky leakageAnd filling SiN insulating dielectric materials below the electrode and the passivation layer, wherein the insulating dielectric materials in the step and the insulating dielectric materials deposited in the fifteenth step form a protective layer 15 together, and manufacturing the whole device.
Example three: making the passivation layer of SiO2And the protective layer is a vertical power device which is made of SiN and is based on the arc-shaped source field plate and the arc-shaped drain field plate.
Step A, SiH is adopted at the temperature of 950 ℃ and the pressure of 40Torr4Is a doping source, the hydrogen flow is 4000sccm, the ammonia flow is 4000sccm, the gallium source flow is 100 mu mol/min, and n is adopted-GaN type substrate 1 is prepared by epitaxial growing on substrate with thickness of 50 μm and doping concentration of 1 × 10 by using metal organic chemical vapor deposition18cm-3N of (A) to (B)-Type GaN material, a drift layer 2 is made, as shown in fig. 3 a.
Step B, SiH with the temperature of 950 ℃ and the pressure of 40Torr is adopted4Is a doping source with hydrogen flow of 4000sccm, ammonia flow of 4000sccm and gallium source flow of 100 mu mol/min, and is epitaxially grown on the drift layer 2 to a thickness of 3 mu m and a doping concentration of 1 × 10 by using Metal Organic Chemical Vapor Deposition (MOCVD) technique18cm-3The aperture layer 3 is made of n-type GaN material as shown in fig. 3 b.
Step C, manufacturing a mask on the aperture layer 3; then using ion implantation technique to implant 1 × 10 dosage at two sides in the aperture layer16cm-2Of (2) is formed two first barrier layers 41 having a thickness a of 3 μm and a width c of 1 μm, as shown in FIG. 3 c.
Step d, making a mask on the aperture layer 3 and the two first barrier layers 41; then using ion implantation technology to implant 1 × 10 dosage at two sides in the aperture layer 3 between the left and right first barrier layers 4116cm-2The two second barrier layers 42 with the thickness b of 1 μm and the width d of 3.3 μm are manufactured, the two first barrier layers and the two second barrier layers form two symmetrical current barrier layers 4 with a two-step structure, and an aperture 5 is formed between the left current barrier layer 4 and the right current barrier layer 4, as shown in fig. 3 d.
Step E, adopting a vacuum degree of less than or equal to 1.0 multiplied by 10-10mbar, radio frequency power of 400W, and N as reactant2The process conditions for the high purity Ga source are such that a channel layer 6 of GaN material with a thickness of 0.2 μm is epitaxially grown on the two first barrier layers 41, the two second barrier layers 42 and the aperture 5 using molecular beam epitaxy technique, as shown in fig. 3 e.
Step F, adopting a vacuum degree of less than or equal to 1.0 multiplied by 10-10mbar, radio frequency power of 400W, and N as reactant2High-purity Ga source and high-purity Al source, and epitaxial growth of Al with a thickness of 50nm on the channel layer 6 by using molecular beam epitaxy technique0.1Ga0.9A barrier layer 7 of N material as shown in fig. 3 f.
G, firstly, manufacturing a mask on the upper part of the barrier layer 7; then using ion implantation technique to implant 1 × 10 dosage on both sides in the barrier layer16cm-2Forming an implanted region 8 with a depth of 0.06 μm;
then, rapid thermal annealing was performed at a temperature of 1200 ℃ using as in FIG. 3 g.
Step H, firstly, making a mask on the upper parts of the two injection regions 8 and the upper part of the barrier layer 7 between the two injection regions, and then adopting a vacuum degree smaller than 1.8 multiplied by 10-3Pa, power range of 200-1000W, evaporation rate less than
Figure BDA0001257932340000181
Using electron beam evaporation technique, depositing Ti/Au/Ni composite metal on top of the two implanted regions to form the source electrode 9, wherein: the thickness of the metal deposited from bottom to top was 0.02 μm for Ti, 0.3 μm for Au and 0.05 μm for Ni, as shown in FIG. 3 h.
Step I, firstly, a mask is manufactured on the upper portion of the source electrode 9 and the upper portion of the barrier layer 7 between the two injection regions; then the vacuum degree is less than 1.8 multiplied by 10-3Pa, power range of 200-1000W, evaporation rate less than
Figure BDA0001257932340000182
Using electron beam evaporation techniques, depositing a Ni/Au/Ni combination metal on the barrier layer 7 between the two implanted regions, forming a gate electrode 10, wherein: gold deposited from bottom to topThe thickness of Ni is 0.02 μm, the thickness of Au is 0.2 μm, the thickness of Ni is 0.04 μm, and the overlapping length of the gate electrode 10 and the two second barrier layers 42 in the horizontal direction is 0.6 μm, as shown in FIG. 3 i.
Step J, adopting a vacuum degree of less than 1.8 multiplied by 10-3Pa, power range of 200-1000W, evaporation rate less than
Figure BDA0001257932340000183
Using electron beam evaporation technology, depositing Au and Ni in sequence on the back of the whole substrate 1 to form Au/Ni composite metal, and completing the manufacture of the Schottky drain 11, wherein the thickness of Au is 0.7 μm, and the thickness of Ni is 0.05 μm, as shown in FIG. 3 j.
Step K. adopt N2O flow rate of 850sccm, SiH4The flow rate is 200sccm, the temperature is 250 ℃, the radio frequency power is 25W, and the pressure is 1100mTorr, and the SiO is deposited in all the areas except the bottom of the Schottky drain electrode 11 by using the plasma enhanced chemical vapor deposition technology2Insulating dielectric material forming an encapsulating passivation layer 12, fig. 3 k.
Step L, firstly, a mask is manufactured on the upper part of the passivation layer 12; then adopt CF4The flow rate was 45sccm, O2The reactive ion etching technique is used under the process conditions of 5sccm flow, 15mTorr pressure and 250W power, etching is carried out in the passivation layer at the upper parts of the left side and the right side of the passivation layer 12 to the same horizontal height with the lower edge of the current blocking layer 4, and two left and right upper platforms are formed, as shown in FIG. 3 l.
Step M, firstly, manufacturing masks on the upper parts of the passivation layers 12 with the upper platforms engraved on the left side and the right side; using CF4The flow rate was 45sccm, O2Etching in the upper platforms at the left and right sides of the passivation layer 12 by using a reactive ion etching technique under the process conditions of a flow rate of 5sccm, a pressure of 15mTorr and a power of 250W to form a source arc step, wherein the source arc step is located at a portion of the lower edge of the first barrier layer 41 below the same horizontal level, a vertical distance from any point of the surface to the lower edge of the first barrier layer 41 is f, a horizontal distance from the drift layer 2 is e, and approximately satisfies a relationship of f 9.5-10.5exp (-0.6e), and f is 9 μm at most,the horizontal distance g between the source arc step surface and the lower edge of the first barrier layer 41 at the same level is 0.18 μm, as shown in fig. 3 m.
Step N, firstly, manufacturing a mask on the upper part of the passivation layer 12 with two source arc steps; vacuum degree is less than 1.8X 10-3Pa, power range of 200-1000W, evaporation rate less than
Figure BDA0001257932340000191
Using an electron beam evaporation technology to deposit metal Au on the source arc steps at the left side and the right side, manufacturing two arc-shaped source field plates 13 which are symmetrical at the left side and the right side, wherein the height of the upper edge of each arc-shaped source field plate 13 is 0.5 mu m higher than the height of the lower edge of the first barrier layer 41, and electrically connecting the arc-shaped source field plates at the two sides with the source electrode, as shown in fig. 3 n.
Step O, adopting gas as NH3、N2And SiH4The gas flow rates were 2.5sccm, 950sccm and 250sccm, and the temperature, rf power and pressure were 300 ℃, 25W and 950mTorr, respectively, and SiN insulating dielectric material was deposited over the arc source field plate and over the passivation layer using a plasma enhanced chemical vapor deposition technique, as shown in fig. 3 o.
Step P, firstly, a mask is manufactured on the back of the Schottky drain electrode 11 and the back of the passivation layer 12; then adopt CF4The flow rate was 45sccm, O2The flow is 5sccm, the pressure is 15mTorr, the process conditions of 250W power are that reactive ion etching is used to etch in the left and right sides of the back surface of the passivation layer 12, so as to form a leakage arc-shaped step, the leakage arc-shaped step is located in the part above the same horizontal height of the upper boundary of the schottky drain, the vertical distance q from the lower boundary of the substrate 1 to the horizontal distance p from the drift layer 2 approximately satisfies the relationship q is 5.5+2.5ln (p +0.06), the lower boundary of the leakage arc-shaped step is aligned with the lower boundary of the schottky drain 11, the horizontal distance h from the drift layer 2 to the part of the surface of the leakage arc-shaped step and the upper boundary of the schottky drain at the same horizontal height is 0.05 μm, and q is 11 μm at most, as shown in fig. 3 p.
Step q. first, the schottky drain 11 is formed on the back side and the passivation layer 12 is formed on the back sideMaking a mask; then the vacuum degree is less than 1.8 multiplied by 10-3Pa, power range of 200-1000W, evaporation rate less than
Figure BDA0001257932340000201
Using electron beam evaporation technology to deposit metal Au on the left and right arc-shaped leakage steps to manufacture two arc-shaped leakage field plates 14 which are symmetrical left and right, wherein the height of the lower boundary of the arc-shaped leakage field plate 14 is 0.35 mu m lower than that of the upper boundary of the Schottky drain electrode 11, and the arc-shaped leakage field plates on the two sides are electrically connected with the Schottky drain electrode, as shown in figure 3 q.
Step R, adopting gas as NH3、N2And SiH4The gas flow is respectively 2.5sccm, 950sccm and 250sccm, the temperature, the radio frequency power and the pressure are respectively 300 ℃, 25W and 950mTorr, a plasma enhanced chemical vapor deposition technology is used, SiN insulating dielectric materials are filled below the arc-shaped drain field plate, the schottky drain electrode and the passivation layer, the insulating dielectric materials of the step and the insulating dielectric materials deposited in the step O form a protective layer 15 together, and the whole device is manufactured as shown in fig. 3 r.
The effects of the present invention can be further illustrated by the following simulations:
simulation 1: the longitudinal electric field distribution of the right edge of the drift layer of the device under the condition of forward breakdown of the device is simulated, and the result is shown in FIG. 4, wherein the forward breakdown voltage of the device is 1980V.
As can be seen from fig. 4, after the two-stage stepped current blocking layer is adopted, the device structure of the invention can effectively modulate the electric field distribution near the surfaces on both sides of the drift layer of the device under the condition of forward breakdown, increase the range of the high field region in the device, and promote the electric field distribution near the surfaces on both sides of the drift layer corresponding to the arc-shaped source field plate to be flat, so that the device of the invention can effectively realize the forward blocking function.
Simulation 2: the longitudinal electric field distribution of the right edge of the drift layer of the device under the condition of reverse breakdown of the device is simulated, and the result is shown in figure 5, wherein the reverse breakdown voltage of the device is-1510V.
As can be seen from FIG. 5, the device structure of the invention can effectively modulate the electric field distribution in the drift layer under the condition of reverse breakdown, increase the area of a high electric field region in the drift layer of the device, and promote the electric field distribution near the surfaces of the two sides of the drift layer corresponding to the arc-shaped leakage field plate to be flat, so that the device of the invention can effectively realize the reverse blocking function.
The foregoing description is only exemplary of the invention and is not intended to limit the invention, and it will be apparent to those skilled in the art that various changes and modifications in form and detail can be made therein without departing from the spirit and scope of the invention, but these changes and modifications are within the scope of the appended claims.

Claims (7)

1. A vertical power device based on arc source field plate and arc drain field plate includes: substrate (1), drift layer (2), aperture layer (3), current barrier layer (4) of two symmetries, channel layer (6), barrier layer (7) and passivation layer (12), both sides deposit on barrier layer (7) has two source electrodes (9), two source electrodes (9) below form two injection regions (8) through ion implantation, the deposit has grid (10) above barrier layer (7) between source electrode (9), the deposit has schottky drain electrode (11) below substrate (1), passivation layer (12) wraps up all regions except schottky drain electrode (11) bottom completely, form aperture (5) between two current barrier layer (4), its characterized in that:
the two current blocking layers (4) adopt a two-stage stepped structure formed by a first blocking layer (41) and a second blocking layer (42), and the second blocking layer (42) is positioned on the inner side of the first blocking layer (41);
passivation layer (12), its both sides all adopt double arc step, carve active arc step in the upper portion region on passivation layer both sides promptly, and the lower part region is carved with hourglass arc step, wherein:
metal is deposited on each source arc step to form two symmetrical arc source field plates (13), and the arc source field plates (13) are electrically connected with the source electrode (9);
metal is deposited at each leakage arc-shaped step to form two symmetrical arc-shaped leakage field plates (14), and the arc-shaped leakage field plates (14) are electrically connected with the Schottky drain electrode (11);
the arc-shaped source field plate, the arc-shaped drain field plate, the Schottky drain electrode and the passivation layer are covered with a protective layer (15).
2. The device according to claim 1, wherein the first barrier layer (41) has a thickness a of 1.2 to 3 μm and a width c of 0.2 to 1 μm, the second barrier layer (42) has a thickness b of 0.3 to 1 μm and a width d, and d is 1.1 a.
3. The device according to claim 1, wherein the source arc step surface is located at any point below the same level as the lower edge of the first barrier layer (41), is at a vertical distance f from the lower edge of the first barrier layer (41), is at a horizontal distance e from the drift layer (2), and satisfies the relationship f-9.5-10.5 exp (-0.6e), 0 μm < f ≦ 9 μm; the surface of the source arc step and the lower edge of the first barrier layer (41) are at the same horizontal height, and the horizontal distance g between the surface of the source arc step and the drift layer (2) is 0.18 mu m.
4. The device of claim 1, wherein the lower edge of the drain arc step is aligned with the lower edge of the schottky drain (11), the surface of the drain arc step is located at any point above the same level as the upper edge of the schottky drain, the surface of the drain arc step is located at a vertical distance q from the lower edge of the substrate (1) and a horizontal distance p from the drift layer (2), and the relationship q is 5.5+2.5ln (p +0.06), and 0 μm < q ≦ 11 μm, and the surface of the drain arc step is located at the same level as the upper edge of the schottky drain and is located at a horizontal distance h from the drift layer (2) and h ≦ 0.05 μm.
5. A method for manufacturing a vertical power device based on an arc-shaped source field plate and an arc-shaped drain field plate comprises the following steps:
A. in the presence of n-Epitaxial growth of n on a substrate (1) of GaN type material-A GaN-type semiconductor material forming a drift layer (2);
B. epitaxially growing n-type GaN semiconductor material on the drift layer (2) to a thickness of 1.2 to E3 μm and a doping concentration of 1X 1015～1×1018cm-3The pore diameter layer (3);
C. a mask is formed on the aperture layer (3), and the mask is used to implant a dose of 1X 10 at both sides in the aperture layer15～1×1016cm-2The p-type impurity of (1), two first barrier layers (41) having a thickness a of 1.2 to 3 μm and a width c of 0.2 to 1 μm are formed;
D. a mask is formed on the aperture layer (3) and the first barrier layer (41), and the mask is used to implant a dose of 1X 10 on both sides of the aperture layer between the left and right first barrier layers (41)15～1×1016cm-2The thickness b of the p-type impurity is 0.3-1 mu m, the width d of the p-type impurity is equal to 1.1a, the two first barrier layers (41) and the two second barrier layers (42) form a current barrier layer (4) with a two-stage stepped structure, and an aperture (5) is formed between the two symmetrical current barrier layers (4);
E. extending GaN semiconductor materials on the two first barrier layers (41), the two second barrier layers (42) and the upper part of the aperture (5) in an epitaxial manner to form a channel layer (6) with the thickness of 0.04-0.2 mu m;
F. a GaN-based wide bandgap semiconductor material is extended on the upper part of the channel layer (6) to form a barrier layer (7) with the thickness of 5-50 nm;
G. a mask is formed on the upper part of the barrier layer (7), and the implantation dose is 1 x 10 on both sides in the barrier layer by using the mask15～1×1016cm-2The n-type impurity of (2) to make an implanted region (8), wherein the depth of both implanted regions is greater than the thickness of the barrier layer and less than the total thickness of the channel layer (6) and the barrier layer;
H. manufacturing a mask on the upper parts of the two injection regions (8) and the upper part of the barrier layer (7) between the two injection regions, and depositing metal on the upper parts of the two injection regions (8) by using the mask to manufacture a source electrode (9);
I. manufacturing a mask on the upper part of the barrier layer (7) between the source electrode (9) and the two injection regions, and depositing metal on the upper part of the barrier layer (7) between the two injection regions by using the mask to manufacture a grid electrode (10);
J. depositing metal on the back of the substrate (1) to manufacture a Schottky drain electrode (11);
K. depositing an insulating dielectric material in all areas except the bottom of the Schottky drain electrode (11) to form a wrapped passivation layer (12);
l, manufacturing a mask on the upper part of the passivation layer (12), etching the upper parts of the passivation layer (12) on the left side and the right side by using the mask to the same horizontal height with the lower edge of the current blocking layer, and forming an upper platform;
m, manufacturing masks on the upper parts of the passivation layers (12) with the upper platforms engraved on the left and right sides, and etching the upper platforms on the left and right sides of the passivation layers (12) by using the masks to form source arc-shaped steps; the source arc-shaped step is positioned at a part below the lower edge of the first barrier layer (41) at the same horizontal height, the vertical distance from the surface of any point of the source arc-shaped step to the lower edge of the first barrier layer (41) is f, the horizontal distance from the source arc-shaped step to the drift layer (2) is e, and the relationship f is 9.5-10.5exp (-0.6 e); the surface of the source arc step and the lower edge of the first barrier layer (41) are positioned at a horizontal height, and the horizontal distance between the source arc step and the drift layer (2) is g;
manufacturing a mask on the upper part of a passivation layer (12) with two source arc steps, depositing metal on the source arc steps on the left side and the right side of the passivation layer by using the mask to form two arc source field plates (13) which are symmetrical left and right, and electrically connecting the arc source field plates (13) on the two sides with a source electrode (9), wherein the height of the upper edge of the deposited metal is higher than or equal to that of the lower edge of a first barrier layer (41);
o, covering an insulating medium material on the upper parts of the arc-shaped source field plate (13) and the passivation layer (12) to protect the arc-shaped source field plate;
p, a mask is manufactured on the back surface of the Schottky drain electrode (11) and the back surface of the passivation layer (12), etching is carried out in the left side and the right side of the back surface of the passivation layer (12) by utilizing the mask, a leakage arc-shaped step is formed, the lower boundary of the leakage arc-shaped step is aligned with the lower boundary of the Schottky drain electrode (11), the leakage arc-shaped step is positioned on the part, above the same horizontal height, of the upper boundary of the Schottky drain electrode, any point on the surface of the leakage arc-shaped step is located, the vertical distance between the surface of the leakage arc-shaped step and the lower boundary of the substrate (1) is q, the horizontal distance between the surface of the leakage arc-shaped step and the drift layer (2) is p, the relation q is 5.5+2.5ln (p +0.06), and the horizontal distance h between the surface of the leakage arc-;
q, manufacturing masks on the back of the Schottky drain electrode (11) and the back of the leakage arc-shaped step, depositing metal on the leakage arc-shaped steps on the left side and the right side by using the masks to form two arc-shaped leakage field plates (14) which are symmetrical left and right, and electrically connecting the arc-shaped leakage field plates (14) on the two sides with the Schottky drain electrode (11);
and R, covering an insulating medium material below the arc-shaped drain field plate, the Schottky drain electrode and the passivation layer to protect the arc-shaped drain field plate, wherein the insulating medium material in the step and the insulating medium material covered in the step O jointly form a protective layer (15), and the whole device is manufactured.
6. A method according to claim 5, characterized in that the upper edge of the arc-shaped source field plate (13) is at a level equal to or higher than the level of the lower edge of the first barrier layer (41).
7. A method according to claim 5, characterized in that the lower border of the arc shaped drain field plate (14) is at a level equal to or lower than the level of the upper border of the Schottky drain electrode (11).
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