CN101216529B - Combined test action group test system of micro-electric communication processing structure - Google Patents
Combined test action group test system of micro-electric communication processing structure Download PDFInfo
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- CN101216529B CN101216529B CN2008100563773A CN200810056377A CN101216529B CN 101216529 B CN101216529 B CN 101216529B CN 2008100563773 A CN2008100563773 A CN 2008100563773A CN 200810056377 A CN200810056377 A CN 200810056377A CN 101216529 B CN101216529 B CN 101216529B
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Abstract
The invention discloses a joint test action group (JTAG) test system of a micro-telecommunication computing architecture, which comprises an external test unit, and main carrier hubs (MCH) and an advanced mezzanine card (AMC) of a micro-telecommunication computing architecture, wherein the external test unit is connected with the JTAG interfaces of the MCH and the AMC in a bus manner to serve as a main device master for testing the MCH and the AMC; the MCH serves as a master for testing the AMC or as a slave to be tested by the external test unit; and the AMC services as a slave to be tested by the current master. The invention can achieve connection between the selected master and the set slave and achieve slave test step by step without achieving JTAG switch module (JSM).
Description
Technical field
The present invention relates to (the JTAG of combined testing action group, JOINT TEST ACTION GROUP) measuring technology, relate in particular to the jtag test system of a kind of little communication processing structure (MicroTCA, Micro TelecommunicationComputing Architecture).
Background technology
The JTAG agreement is a kind of international standard test protocol, is mainly used in the chip internal test.PCI industrial computer manufacturing tissue (PICMG, PCI Industrial Computer Manufacturers Group) formulated a cover MicroTCA standard, purpose is to allow advanced subcard (AMC, Advanced Mezzanine Card) directly be inserted on the backboard.MicroTCA is little because of its size, extendability and dirigibility is good and characteristics such as cost factor are fit to the use of wireless base station side apparatus etc.
Test is the part of the outbalance of MicroTCA, and the test of MicroTCA can realize with jtag interface.Fig. 1 is the composition structural drawing of the jtag test system of existing MicroTCA.As shown in Figure 1, the jtag test system of existing MicroTCA comprises external testing unit 111; The master control borad of two MicroTCA (MCH, MicroTCA Carrier Hub) is labeled as a MCH211, the 2nd MCH212 respectively; JTAG Switching Module (JSM, JTAG Switch Module) 311; 12 AMC are labeled as an AMC411～the 12 AMC422 respectively.
And among Fig. 1, the interface signal that external testing unit 111 relates to comprises: data input signal, represent with TDIe; Data output signal is represented with TDOe; Test clock signals is represented with TCKe; Test mode select signal is represented with TMSe; Test reset signal is represented with TRST#e; The master uses request signal, represents with TMREQ#e; The JSM configuration mode is selected signal, represents with JSMCONFIG#e.
The interface signal that the one MCH211 relates to comprises: input signal of test data, represent with TDI1; Test data output signal is represented with TDO1; Test clock signals is represented with TCK1; Test mode select signal is represented with TMS1; Test reset signal is represented with TRST1; The master uses request signal, represents with TMREQ# 1; The one MCH interface direction control signal is represented with MCDIR#1.The interface signal that the 2nd MCH212 relates to comprises: input signal of test data, represent with TDI2; Test data output signal is represented with TDO2; Test clock signals is represented with TCK2; Test mode select signal is represented with TMS2; Test reset signal is represented with TRST2; The master uses request signal, represents with TMREQ# 2; The one MCH interface direction control signal is represented with MCDIR# 2.
12 AMC relate to the expression mode type of interface signal, are example with an AMC411, and the interface signal that an AMC411 relates to comprises: test data output signal, represent with STDO1; Input signal of test data is represented with STDI1; Test mode select signal is represented with STMS1; Test clock signals STCK1 represents; Test reset signal is represented with STRST#1.
In sum, it is pointed out that the above-mentioned uniformity signal that relates to represents that the difference of mode only is the sign difference of last position, the sign of this last position is used to distinguish the different ingredients of corresponding diagram 1 system.Such as, represent with TCKe that with the test clock signals that outside test cell 111 relates to the test clock signals that a MCH211 relates to is represented with TCK1.Wherein TCK represents test clock signals.
At present, the general employing of the jtag test system of existing MicroTCA realized JSM on the backboard of MicroTCA cabinet, or extra veneer of independent increase is realized JSM in the MicroTCA cabinet.And each veneer of MicroTCA system all is connected on the JSM by jtag interface such as MCH and AMC and external testing unit.So, in the jtag test system of MicroTCA, the external testing unit can be by the MCH and the AMC of jtag interface test macro as the main device master that initiates test.MCH can come the AMC of test macro and other MCH in the system as master, again can be as being tested by other master from device slave.AMC can only be tested by master as slave.Here, the effect of JSM mainly contains 2 points: the one, for outside test cell, among the MCH of system, with the selection of which MCH as master; The 2nd, the selected master and the slave of setting are linked to each other, progressively slave is tested.
In sum, prior art need realize JSM, and the effect by JSM, behind the selected master, the selected master and the slave of setting is linked to each other, and progressively slave is tested.So, on backboard, realize JSM, then will increase the complexity of backboard, can increase the paster operation in the time of processing one if adopt.Increase an extra veneer realization JSM if adopt, then will certainly increase the manufacturing cost of the jtag test system of MicroTCA.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide the jtag test system of a kind of MicroTCA, need not to realize JSM, and can realize the selected master and the slave of setting are linked to each other, and progressively finishes the test to slave.
For achieving the above object, technical scheme of the present invention is achieved in that
The jtag test system of a kind of MicroTCA, this system comprises external testing unit, MCH and AMC; Wherein,
The external testing unit adopts bus mode to connect together with the jtag interface of described MCH and described AMC, is used for as master, and described MCH and described AMC are tested;
MCH is used for as master, tests described AMC; Perhaps as slave by described external testing unit testing;
AMC is used for being tested by current master as slave.
Wherein, the signal connected mode of described external testing unit and described MCH and described AMC is: TDI is connected to the TDO of described MCH and described AMC, and the TDO of described external testing unit is connected to the TDI of described MCH and described AMC.
Wherein, described MCH also comprises judging module, and then MCH further judges according to the default judgement mode of described judging module and current master in the described system the current slave in the described system tested.
Wherein, when described MCH was a MCH, judgement mode default in the described judging module was:
Judge whether the TMREQ#e signal is effective, as effectively, judge that then described external testing unit is master, a described MCH is as slave; When the TMREQ#e invalidating signal, judge whether the TMREQ# 1 signal is effective, effectively then a MCH is defaulted as slave as master under other condition.
Wherein, when described MCH is a MCH and the 2nd MCH, and current MCH is when being the 2nd MCH, and judgement mode default in the described judging module is:
Judge whether the TMREQ#e signal is effective, as effectively, then described external testing unit is master, and described the 2nd MCH is as slave; When the TMREQ#e invalidating signal, must judge whether the TMREQ# 1 signal is effective, an effectively then described MCH is master, described the 2nd MCH is as slave; When TMREQ#e and TMREQ# 1 signal are all invalid, judge the TMREQ# 2 signal, effectively then the 2nd MCH is defaulted as slave as master under other condition.
Wherein, the signal connected mode of described external testing unit and described MCH further is:
The TMREQ#e signal is connected on a described MCH and described the 2nd MCH; And, the TMREQ# 1 of a MCH is connected on the 2nd MCH; The TMREQ# 2 of the 2nd MCH is linked on the MCH.
System of the present invention comprises external testing unit, MCH and AMC.To comprise two MCH in the system for instance, realize part at backboard, the present invention need not to realize JSM, only needs to adopt the jtag interface of each MCH and each AMC and external testing unit bus mode to connect together.And, it is pointed out that the TDI of external testing unit links the TDO of each MCH and each AMC; The TDI of the TDO of external testing unit and each MCH and each AMC connects together.Realize part at MCH, need link two MCH to the TMREQ#e signal of external testing unit such as on MCH1 and the MCH2.Wherein, the TMREQ# 1 of MCH1 is connected on the MCH2, the TMREQ# 2 of MCH2 links MCH1, and jtag interface and core bus connect together.Realize part at AMC, only needing jtag interface and core bus connected together gets final product.
In sum, the present invention need not additionally to increase JSM, can finish the test operation to MicroTCA equally, can realize the selected master and the slave of setting are linked to each other, and progressively finishes the test to slave.Thereby reduced the manufacturing cost of the jtag test system of MicroTCA.
Description of drawings
Fig. 1 is the composition structural drawing of the jtag test system of existing MicroTCA;
Fig. 2 is the composition structural drawing of one embodiment of jtag test system of MicroTCA of the present invention;
Fig. 3 is the composition structural drawing of MCH one embodiment in the system of the present invention;
Fig. 4 is the composition structural drawing of AMC one embodiment in the system of the present invention.
Embodiment
Core concept of the present invention is: the present invention need not additionally to increase JSM, specifically realize that by backboard part, MCH realize that part realizes being connected of part interface signal with AMC, can finish test operation equally to MicroTCA, can realize the selected master and the slave of setting are linked to each other, progressively finish test slave.
Be described in further detail below in conjunction with the enforcement of accompanying drawing technical scheme.
The jtag test system of a kind of MicroTCA, this system comprises external testing unit, MCH and AMC.And MCH/AMC can be one, also can be polylith.This system specifically realizes that by backboard part, MCH realize that part realizes being connected of part interface signal with AMC, finishes the test operation to MicroTCA.
Wherein, when comprising polylith MCH/AMC in the system, the jtag interface of each MCH and each AMC adopts bus mode to connect together in external testing unit and the system.The external testing unit is used for as master, and each MCH and each AMC are tested.MCH can be as master, the AMC of test macro and other MCH in the system; Can be tested by other master as slave again.Each AMC can only be tested by master as slave.
Here, when external test tools, when each MCH applies for master simultaneously, their priority as master need be set.
Here, described MCH also comprises judging module, and then MCH further judges according to the default judgement mode of described judging module and current master in the described system the current slave in the described system tested.
In the system embodiment one shown in Figure 2, comprise external testing unit 111; Two MCH are respectively a MCH211 and the 2nd MCH212; 12 AMC are respectively an AMC411～the 12 AMC422.
Below system is specifically realized that by backboard part, MCH realize that part and AMC realize being connected of part interface signal, finish the test operation of MicroTCA is set forth.
As shown in Figure 2, realize part, adopt bus mode to connect together the jtag interface of a MCH211, the 2nd MCH212, an AMC411～the 12 AMC422 and external testing unit 111 at backboard.And, the TDI of external testing unit 111 is connected to the TDO of a MCH211 and the 2nd MCH212; The TDI of external testing unit 111 is connected to the TDO of an AMC411～the 12 AMC422.The TDO of external testing unit 111 is connected to the TDI of a MCH211 and the 2nd MCH212; The TDO of external testing unit 111 is connected to the TDI of an AMC411～the 12 AMC422.Here, the following backboard position of representing of dot-and-dash line among Fig. 2.
Realize part at MCH, need link two MCH to the TMREQ#e signal of external testing unit 111 is on a MCH211 and the 2nd MCH212, shown in the heavy line among Fig. 2.Wherein, the TMREQ# 1 of a MCH211 is connected on the 2nd MCH212, the TMREQ# 2 of the 2nd MCH212 is linked on the MCH211, shown in the middle solid line among Fig. 2.And MCH realizes that the jtag interface of part and backboard realization part adopt bus mode to link together.Realize part at AMC, AMC is realized that the jtag interface of part and backboard realization partial bus adopt bus mode to link together.
Be illustrated in figure 3 as the implementation method of MCH in the system.This MCH comprises CPU511, a JTAG device 61～the n JTAG device 6n, and logical device 711, the first logical devices 811 and second logical device 812 are connected to the connector 911 of backboard.Here, a JTAG device～n JTAG device can also be n JTAG chain, is respectively a JTAG chain～n JTAG chain, and first logical device and second logical device can also be two JTAG bridge sheets, are respectively a JTAG bridge sheet and the 2nd JTAG bridge sheet.Here it is pointed out that heavy line among Fig. 3 represents controller read-write bus.The interface signal that relates among Fig. 3 is referring to above-mentioned description to related MCH among Fig. 1.
For total system, can as the differentiation of insertion groove position, determine that this MCH is that a MCH still is the 2nd MCH according to setting in advance.And, as external testing unit, a MCH, when the 2nd MCH applies for master simultaneously, their priority as master need be set.The priority that the external testing unit can be set is the highest, and a MCH takes second place, and the 2nd MCH is minimum.
Here, the judgement mode that MCH further presets according to judging module is judged the current master in the system shown in Figure 2, and the current slave in this system is tested.
So, default judgement mode is in the judging module:
Include only a MCH in system, and when being a MCH, judge at first whether the TMREQ#e signal is effective, as effectively, judge that then the external testing unit is master, a MCH is as slave; When the TMREQ#e invalidating signal, judge whether the TMREQ# 1 signal is effective, effectively then a MCH is defaulted as slave as master under other condition.
Comprise two MCH in system, and current MCH must judge at first whether the TMREQ#e signal is effective when being the 2nd MCH, as effectively, then the external testing unit is master, and the 2nd MCH is as slave; When the TMREQ#e invalidating signal, must judge whether the TMREQ# 1 signal is effective, effectively then a MCH is master, the 2nd MCH is as slave; When TMREQ#e and TMREQ# 1 signal are all invalid, judge the TMREQ# 2 signal, effectively then the 2nd MCH is defaulted as slave as master under other condition.
Here, as shown in Figure 3, as MCH when promptly a MCH/ the 2nd MCH is as master, test instruction under the CPU511 changes the control interface of CPU511 into jtag interface by first logical device 811, is connected to backboard, thereby total system is tested.As MCH when promptly a MCH/ the 2nd MCH is as slave, the jtag interface that first logical device 811 among Fig. 3 is set is for ternary, the jtag interface signal that comes from backboard is distributed to each device on this MCH by second logical device 812 Fig. 3, thereby is tested by other master.And first logical device 811 and second logical device 812 can select for use special device realization or employing oneself to realize with programming device among Fig. 3.
Be illustrated in figure 4 as the implementation method of AMC in the system.This AMC comprises a JTAG device 61～the n JTAG device 6n, the 3rd logical device 813 and the connector 911 that is connected to backboard.Can know intuitively that from Fig. 4 only each chip that need be distributed to the JTAG signal that backboard comes on this AMC gets final product.Here, a JTAG device～n JTAG device can also be n JTAG chain, is respectively a JTAG chain～n JTAG chain, and the 3rd logical device can also be JTAG bridge sheet.Here it is pointed out that the interface signal that relates among Fig. 4 is referring to above-mentioned description to related AMC among Fig. 1.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.
Claims (4)
1. the combined testing action group test macro of a little communication processing structure is characterized in that, this system comprises the master control borad MCH and the advanced subcard AMC of external testing unit, little communication processing structure; Wherein,
The external testing unit adopts bus mode to connect together with the combined testing action group jtag interface of described MCH and described AMC, is used for as main device master described MCH and described AMC being tested;
MCH is used for as master, tests described AMC; Perhaps conduct is from installing slave by described external testing unit testing;
AMC is used for being tested by current master as slave;
Wherein, the signal connected mode of described external testing unit and described MCH and described AMC is: the data input signal TDI of external testing unit is connected to the data output signal TDO of described MCH and described AMC, and the TDO of described external testing unit is connected to the TDI of described MCH and described AMC; The main of external testing unit is connected on a described MCH and described the 2nd MCH with request signal TMREQ#e, and the main of a MCH is connected on the 2nd MCH with request signal TMREQ#1, and the main of the 2nd MCH linked on the MCH with request signal TMREQ#2.
2. system according to claim 1, it is characterized in that, described MCH also comprises judging module, and then MCH further judges according to the default judgement mode of described judging module and current master in the described system the current slave in the described system tested.
3. system according to claim 2 is characterized in that, when described MCH was a MCH, judgement mode default in the described judging module was:
Judge whether the TMREQ#e signal is effective, as effectively, judge that then described external testing unit is master, a described MCH is as slave; When the TMREQ#e invalidating signal, judge whether the TMREQ#1 signal is effective, effectively then a MCH is defaulted as slave as master under other condition of the one MCH.
4. system according to claim 2 is characterized in that, when described MCH is a MCH and the 2nd MCH, and current MCH is when being the 2nd MCH, and judgement mode default in the described judging module is:
Judge whether the TMREQ#e signal is effective, as effectively, then described external testing unit is master, and described the 2nd MCH is as slave; When the TMREQ#e invalidating signal, must judge whether the TMREQ#1 signal is effective, an effectively then described MCH is master, described the 2nd MCH is as slave; When TMREQ#e and TMREQ#1 signal are all invalid, judge the TMREQ#2 signal, effectively then the 2nd MCH is defaulted as slave as master under other condition of the 2nd MCH.
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| CN2008100563773A CN101216529B (en) | 2008-01-17 | 2008-01-17 | Combined test action group test system of micro-electric communication processing structure |
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| CN2008100563773A CN101216529B (en) | 2008-01-17 | 2008-01-17 | Combined test action group test system of micro-electric communication processing structure |
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| CN102385034B (en) * | 2011-10-12 | 2013-08-07 | 京信通信***（中国）有限公司 | Circuit test device of micro telecommunications computing architecture (TCA) and test method thereof |
| CN103163451B (en) * | 2013-03-06 | 2014-04-16 | 中国人民解放军国防科学技术大学 | Super computing system oriented self-gating boundary scan test method and device |
| CN105548863B (en) * | 2015-12-29 | 2018-04-17 | 广州慧睿思通信息科技有限公司 | A kind of structure and method of the interconnection of plate level multi-chip JTAG chains |
| WO2021189322A1 (en) * | 2020-03-25 | 2021-09-30 | 华为技术有限公司 | Chip testing apparatus and chip testing method |
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