CN101197333A - Pixel structure manufacturing method - Google Patents
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- CN101197333A CN101197333A CNA2007103053157A CN200710305315A CN101197333A CN 101197333 A CN101197333 A CN 101197333A CN A2007103053157 A CNA2007103053157 A CN A2007103053157A CN 200710305315 A CN200710305315 A CN 200710305315A CN 101197333 A CN101197333 A CN 101197333A
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Abstract
A manufacturing method of a pixel structure includes the following steps that: firstly, a substrate is provided; secondly, a first conductive layer is formed on the substrate, and a first shade which exposes part of the first conductive layer is arranged above the first conductive layer; thirdly, laser passes through the first shade to irradiate the first conductive layer, thereby removing part of the first conductive layer to form a grid electrode; fourthly, a grid electrode insulating layer is formed on the substrate to cover the grid electrode; fifthly, a channel layer is formed on the grid electrode insulating layer positioned above the grid electrode; sixthly, a source electrode and a drain electrode are formed on the channel layer positioned at both sides of the grid electrode; seventhly, a patterning protective layer is formed to cover the channel layer and expose the drain electrode; finally, an electrode material layer is formed to cover the patterning protective layer and the exposed drain electrode, and patterning of the electrode material is completed through the patterning protective layer to form a pixel electrode. Compared with the well known manufacturing method of a pixel structure, the invention can simplify processing steps and reduces the manufacturing cost of photomask.
Description
Technical field
The present invention relates to a kind of production method of pixel structure, and be particularly related to the production method of pixel structure that a kind of use laser lift-off (laser ablation process) is made semiconductor layer.
Background technology
The communication interface of display behaviour and information is the trend of main development at present with the flat-panel screens.Flat-panel screens mainly contains following several: (thin film transistor liquid crystal display) such as organic electro-luminescent display (organicelectroluminescence display), plasma scope (plasma display panel) and Thin Film Transistor-LCDs.Wherein, being most widely used with Thin Film Transistor-LCD again.Generally speaking, Thin Film Transistor-LCD mainly is made of thin-film transistor array base-plate (thin film transistor array substrate), colorful filter array substrate (color filter substrate) and liquid crystal layer (liquid crystal layer).Wherein, thin-film transistor array base-plate comprises the dot structure (pixel unit) of multi-strip scanning line (scan lines), many data wires (data lines) and a plurality of arrayed, and each dot structure electrically connects with corresponding scanning line and data wire respectively.
Figure 1A～Fig. 1 G is the manufacture method schematic diagram of known pixel structure.At first, please refer to Figure 1A, substrate 10 is provided, and on substrate 10, form grid 20 by the first road photo-marsk process.Then, please refer to Figure 1B, on substrate 10, form gate insulator 30 with cover grid 20.Then, please refer to Fig. 1 C, on gate insulator 30, form the channel layer 40 that is positioned at grid 20 tops by the second road photo-marsk process.Afterwards, please refer to Fig. 1 D, on the subregion of the subregion of channel layer 40 and gate insulator 30, form source electrode 50 and drain 60 by the 3rd road photo-marsk process.Generally speaking, the material of channel layer 40 is amorphous silicon (amorphous silicon), what deserves to be mentioned is, in order to reduce between channel layer 40 and the source electrode 50 and channel layer 40 and the contact impedance of drain electrode between 60, can utilize the mode of ion doping (ion doping) to form N type doped region on the practice in the surface of amorphous silicon.
Please continue the D with reference to Fig. 1, source electrode 50 is extended on the gate insulator 30 by the both sides of channel layer 40 respectively with drain electrode 60, and the subregion of channel layer 40 is exposed.Then, please refer to Fig. 1 E, on substrate 10, form protective layer 70 with cover gate insulating barrier 30, channel layer 40, source electrode 50 and drain 60.Then, please refer to Fig. 1 F, by the 4th road photo-marsk process with protective layer 70 patternings, in protective layer 70, to form contact hole H.By Fig. 1 F as can be known, the contact hole H in the protective layer 70 can expose the part district of drain electrode 60.Afterwards, please refer to Fig. 1 G, form pixel electrode 80 by the 5th road photo-marsk process on protective layer 70, by Fig. 1 G as can be known, pixel electrode 80 can see through contact hole H and electrically connect with drain electrode 60.After pixel electrode 80 completes, just finished the making of dot structure 90.
Hold above-mentionedly, known dot structure 90 mainly is to make by five road photo-marsk processes, and in other words, dot structure 90 needs to adopt five photomasks (mask) with different pattern to make.Because the cost of photomask is very expensive, and the per pass photo-marsk process must use the photomask with different pattern, and therefore, if can't reduce the number of photo-marsk process, the manufacturing cost of dot structure 90 can't reduce.
In addition, along with the size of liquid crystal display panel of thin film transistor increases day by day, the photomask size that is used for making thin-film transistor array base-plate also can increase thereupon, and large-sized photomask will be more expensive on cost, make the manufacturing cost of dot structure 90 to reduce effectively.
Summary of the invention
The present invention relates to a kind of production method of pixel structure, it is suitable for reducing cost of manufacture.
For specifically describing content of the present invention, at this a kind of production method of pixel structure is proposed, it provides substrate earlier, and forms first conductive layer on substrate.Then, provide first shade in first conductive layer top, and first shade expose first conductive layer of part.Afterwards, use laser to shine first conductive layer, removing first shade institute exposed portions first conductive layer, and form grid through first shade.Continue it, form gate insulator on substrate, with cover gate.Then, form channel layer on the gate insulator of grid top.Afterwards, form source electrode and drain on the channel layer of grid both sides, and grid, channel layer, source electrode and drain electrode constitute thin-film transistor.Then, form the patterning protective layer on thin-film transistor, to cover channel layer and to expose drain electrode.Afterwards, form electrode material layer, with overlay pattern protective layer and exposed drain, and make the electrode material layer patterning, to form pixel electrode by the patterning protective layer.
In pixel structure preparation method of the present invention, also be included in after the formation patterning protective layer, baking patterning protective layer is so that the top surface of patterning protective layer protrudes from the sidewall of patterning protective layer.In one embodiment, the top surface of patterning protective layer is gill fungus shape (mushroom) top surface.
In pixel structure preparation method of the present invention, also be included in after the formation pixel electrode, remove the patterning protective layer.
In pixel structure preparation method of the present invention, the method that forms channel layer comprises for example being to form semiconductor layer earlier on substrate, and then, patterned semiconductor layer is to form channel layer.In another embodiment, the method that forms channel layer for example is to form semiconductor layer earlier on substrate, then, provide second shade in the semiconductor layer top, and second shade exposes the semiconductor layer of part.Afterwards, use laser through the second shade irradiating semiconductor layer, to remove second shade institute exposed portions semiconductor layer.
In pixel structure preparation method of the present invention, the method that forms source electrode and drain electrode for example is to form second conductive layer earlier on channel layer and gate insulator, and then, patterning second conductive layer is to form source electrode and drain electrode.
In pixel structure preparation method of the present invention, comprise forming this channel layer, this source electrode and this drain electrode simultaneously.In one embodiment, the method that forms this channel layer, this source electrode and this drain electrode simultaneously then, forms the 3rd conductive layer on semiconductor layer for example for forming semiconductor layer earlier on gate insulator.Continue it, form the photoresist layer on the 3rd conductive layer of grid top, wherein the photoresist layer can be divided into the first photoresist block and the second photoresist block that is positioned at the first block both sides, and the thickness of the first photoresist block is less than the thickness of the second photoresist block.Then, be that mask carries out first etch process to the 3rd conductive layer and semiconductor layer with the photoresist layer.Then, reduce the thickness of photoresist layer, removed fully up to the first photoresist block.At last, be that mask carries out second etch process to the 3rd conductive layer with the remaining second photoresist block, so that remaining the 3rd conductive layer constitutes source electrode and drain electrode, and semiconductor layer constitutes channel layer.In another embodiment, the method that forms channel layer, source electrode and drain electrode simultaneously then, forms second conductive layer on semiconductor layer for example for forming semiconductor layer earlier on gate insulator.Afterwards, form the photoresist layer on second conductive layer of grid top, wherein the photoresist layer can be divided into the first photoresist block and the second photoresist block that is positioned at the first block both sides, and the thickness of the first photoresist block is less than the thickness of the second photoresist block.Continuing it, is that mask carries out first etch process and semiconductor layer is carried out second etch process second conductive layer with the photoresist layer.Afterwards, reduce the thickness of photoresist layer, removed fully up to the first photoresist block.Then, be that mask carries out the 3rd etch process and semiconductor layer is carried out the 4th etch process second conductive layer with the remaining second photoresist block, so that remaining second conductive layer constitutes source electrode and drain electrode, and semiconductor layer constitutes channel layer.
The first photoresist block of above-mentioned formation photoresist layer and the method for the second photoresist block for example are through semi-modulation type photomask technology or grey mode photo-marsk process.In another embodiment, the method for the first photoresist block of formation photoresist layer and the second photoresist block also can be to use laser to shine photic resist layer through shade and form.In addition, in other embodiments, the manufacture method of channel layer, source electrode and drain electrode also is included in and forms after the semiconductor layer, forms ohmic contact layer earlier in semiconductor layer surface.Then, through first etch process and second etch process, remove corresponding to the ohmic contact layer outside the second photoresist block.The method of above-mentioned minimizing photoresist layer thickness comprises carries out ashing (ashing) technology.
In pixel structure preparation method of the present invention, form the method for patterning protective layer, for example be in one embodiment after forming thin-film transistor, form protective layer on thin-film transistor.Then, patterning protective layer again.In another embodiment, the method that forms the patterning protective layer for example is after forming thin-film transistor, forms protective layer on thin-film transistor.Then, provide the 3rd shade in the protective layer top, and the 3rd shade expose the protective layer of part.Then, use laser through the 3rd shade irradiation protective layer, to remove the 3rd shade institute exposed portions protective layer.
In pixel structure preparation method of the present invention, the patterning protective layer comprises and being formed on the part of grid pole insulating barrier.
In pixel structure preparation method of the present invention, the composition of patterning protective layer comprises organic photo anti-corrosion agent material.
In pixel structure preparation method of the present invention, the method that forms conductive layer comprises by sputter formation indium tin oxide layer or indium-zinc oxide layer.
In pixel structure preparation method of the present invention, shining in the laser energy of semiconductor layer for example is between 10mJ/cm
2To 500mJ/cm
2Between.In addition, Wavelength of Laser for example is between between the 100nm to 400nm.
In pixel structure preparation method of the present invention, also be included in and form lower floor's capacitance electrode when forming grid, and when forming source electrode and drain electrode, form the upper strata capacitance electrode, wherein lower floor's capacitance electrode and upper strata capacitance electrode constitute reservior capacitor.
The present invention passes through the suitable pattern of patterning protective layer when forming conductive layer; promptly finish the patterning of conductive layer; to form pixel electrode,, can simplify processing step and reduce the cost of manufacture of photomask therefore than known pixel structure preparation method.In addition, when making semiconductor layer, the more known photomask of the employed shade of laser lift-off is simple and easy, so the cost of employed shade is comparatively cheap in the laser lift-off step.
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended accompanying drawing, be described in detail below.
Description of drawings
Figure 1A～Fig. 1 G is the manufacture method schematic diagram of known pixel structure.
Fig. 2 A～Fig. 2 H is a kind of production method of pixel structure schematic diagram of the present invention.
Fig. 3 A～Fig. 3 C is a kind of laser lift-off manufacture method schematic diagram that forms channel layer.
Fig. 4 A～Fig. 4 C is a kind of manufacture method schematic diagram that forms source electrode and drain electrode.
Fig. 5 A～Fig. 5 D is a kind of manufacture method schematic diagram that forms channel layer, source electrode and drain electrode simultaneously.
Fig. 6 A～Fig. 6 F is the another kind of manufacture method schematic diagram that forms channel layer, source electrode and drain electrode simultaneously.
Fig. 7 A～Fig. 7 E is the another kind of manufacture method schematic diagram that forms channel layer, source electrode and drain electrode simultaneously.
Fig. 8 A～Fig. 8 C is a kind of laser lift-off manufacture method schematic diagram that forms the patterning protective layer.
Fig. 9 A～Fig. 9 I is an another kind of production method of pixel structure schematic diagram of the present invention.
And each description of reference numerals in the above-mentioned accompanying drawing is as follows:
10,200 substrates
20,212 grids
30 gate insulators
40,232 channel layers
50,242 source electrodes
60,244 drain electrodes
70 protective layers
80,282 pixel electrodes
90 dot structures
210 first conductive layers
216 lower floor's capacitance electrodes
220 gate insulators
230 semiconductor layers
240 second conductive layers
246 upper strata capacitance electrodes
250 photoresist layers
The 250a first photoresist block
The 250b second photoresist block
252 patterning photoresist layers
260 thin-film transistors
270 protective layers
272 patterning protective layers
280 conductive material layers
280A, 280B partially conductive material layer
The C reservior capacitor
L laser
The H contact hole
The top surface of M gill fungus shape
S1 first shade
S2 second shade
S3 the 3rd shade
Embodiment
First embodiment
Fig. 2 A～Fig. 2 H is the schematic diagram of a kind of production method of pixel structure of the present invention.Please refer to Fig. 2 A, substrate 200 at first is provided, the material of substrate 200 for example is hard or soft materials such as glass, plastic cement.Then, form first conductive layer 210 on substrate 200, wherein first conductive layer 210 for example is by sputter (sputtering), evaporation (evaporation) or other film deposition techniques form, and the material of first conductive layer 210 for example is aluminium (Al), molybdenum (Mo), titanium (Ti), neodymium (Nd), above-mentioned nitride such as molybdenum nitride (MoN), titanium nitride (TiN), its lamination, above-mentioned alloy or other electric conducting materials.
Then, shown in Fig. 2 B, provide the first shade S1, and the first shade S1 exposes first conductive layer 210 of part, and use laser L to shine first conductive layer 210 through the first shade S1 in first conductive layer, 210 tops.In detail, through postradiation first conductive layer 210 of laser L can absorb laser L energy and from substrate 200 sur-face peelings (ablation).Particularly, the energy that is used for peeling off the laser L of first conductive layer 210 for example is between 10mJ/cm
2To 500mJ/cm
2Between.In addition, the wavelength of laser L for example is between between the 100nm to 400nm.Specifically, the laser L of present embodiment also can utilize digit explosure mode (digital exposure) to carry out the program of peeling off of gate material layers 210, wherein the digit explosure mode has the effect of automatic location and adjustment energy, makes that the stripping technology of laser beam is more accurate.
Afterwards, shown in Fig. 2 C, remove after first shade S1 institute exposed portions first conductive layer 210, remaining first conductive layer 210 constitutes grid 212.It should be noted that being different from the photomask that known use involves great expense carries out the making of grid 212, the present invention uses cheap shade S1 to finish the making of grid 212, therefore can save cost.In the present embodiment, production method of pixel structure also is included in when forming grid 212, forms lower floor's capacitance electrode 216.
Then, please refer to Fig. 2 D, on substrate 200, form the gate insulator 220 of cover gate 212 and lower floor's capacitance electrode 216, wherein gate insulator 220 for example is by chemical vapour deposition technique (chemical vapor deposition, CVD) or other suitable film deposition techniques form, and the material of gate insulator 220 for example is dielectric materials such as silica, silicon nitride or silicon oxynitride.Then, form channel layer 232 on the gate insulator 200 of grid 212 tops, and the material of channel layer 232 for example is amorphous silicon (amorphous silicon) or other semi-conducting materials.In the present embodiment, the method that forms channel layer 232 for example is to form semiconductor layer 230 (being shown in Fig. 3 A) by chemical vapour deposition technique, then, in patterned semiconductor layer 230 to form channel layer 232.
Please follow E with reference to Fig. 2, form source electrode 242 and drain 244 on the channel layer 232 of grid 212 both sides, wherein form source electrode 242 and 244 the method for draining comprises and forms second conductive layer 240 (being shown in Fig. 4 A) earlier on channel layer 232 and gate insulator 220, then patterning second conductive layer 240 again, and the material of second conductive layer 240 for example is aluminium (Al), molybdenum (Mo), titanium (Ti), neodymium (Nd), above-mentioned nitride such as molybdenum nitride (MoN), titanium nitride (TiN), its lamination, above-mentioned alloy or other electric conducting materials.Above-mentioned grid 212, channel layer 232, source electrode 242 and the 244 formation thin-film transistors 260 that drain.In addition, shown in Fig. 2 E, in the present embodiment, forming source electrode 242 and draining in 244, also comprise forming upper strata capacitance electrode 246, make lower floor's capacitance electrode 216 and upper strata capacitance electrode 246 constitute reservior capacitor C, to keep good display quality.
In addition, in other embodiments, can form ohmic contact layer (not indicating) earlier on the surface of semiconductor layer 230 (being shown in Fig. 3 A), then, remove the ohmic contact layer (not indicating) of part again by etch process.For example, the mode that can utilize ion doping (ion doping) forms N type doped region in the surface of semiconductor layer 230 (being shown in Fig. 3 A), to reduce between channel layer 232 and the source electrode 242 and channel layer 232 and the contact impedance between 244 of draining.
Then, please refer to Fig. 2 F, form patterning protective layer 272 on thin-film transistor 260, to cover channel layer 232 and to expose part drain electrode 244.Shown in Fig. 2 F; in the present embodiment; patterning protective layer 272 formed scopes comprise and being formed on the part of grid pole insulating barrier 220; the material of patterning protective layer 272 can for example be that organic dielectric materials such as acrylic resin, photoresist are formed; also can for example be that Inorganic Dielectric Materials such as silica, silicon nitride or silicon oxynitride are formed; and the method that forms patterning protective layer 272 for example is by photoresist coating or other suitable film deposition techniques, forms as chemical vapour deposition technique.Then; please continue F with reference to Fig. 2; with the patterning protective layer 272 and second conductive layer 240 is mask; carry out etch process; be not patterned another part gate insulator 220 that protective layer 272 and second conductive layer 240 are covered to remove, and expose first conductive layer 210 (indicating) on the gate pad (indicating) simultaneously.
Then; please refer to Fig. 2 G; form electrode material layer 280; with overlay pattern protective layer 272 and exposed drain 244; wherein the material of electrode material layer 280 is indium tin oxide or indium-zinc oxide, and the method for formation electrode material layer 280 for example is to form indium tin oxide layer or indium-zinc oxide layer by sputter.Because the patterning protective layer 272 as electrode material layer 280 bottoms has suitable thickness, make when forming electrode material layer 280, can form two partial electrode material layer 280A and the 280B that are electrically insulated.In detail; the designer can suitably control the thickness of bottom patterning protective layer 272; and utilize the anisotropic characteristic of the thin film deposition processes of electrode material layer 280; make electrode material layer 280 according to the thickness drop of bottom patterning protective layer 272, form discontinuous two partial electrode material layer 280A and 280B.Part electrode material layer 280A is formed on the patterning protective layer 272, and another part electrode material layer 280B then is formed in substrate 200 and the drain electrode 244.Wherein, part then constitutes pixel electrode 282 with the drain electrode 244 electrode material layer 280B that are connected.It should be noted that to be different from known technology, present embodiment utilizes the design of patterning protective layer 272; synchronization patternization when forming electrode material layer 280; make and finish pixel electrode 282, so the present invention can reduce photo-marsk process one, and reduce the complexity of technology.Generally speaking, after forming pixel electrode 282, more patterning protective layer 272 can be removed, shown in Fig. 2 H.The method that removes patterning protective layer 272 for example uses stripper in the surface of patterning protective layer 272 with electrode material layer 280, make patterning protective layer 272 basal surface because of the intrusion of stripper from thin-film transistor 260 surfaces or gate insulator 220 sur-face peelings.
In addition, the method for above-mentioned formation channel layer 232 for example can use laser lift-off to make.Fig. 3 A～Fig. 3 C is a kind of laser lift-off manufacture method schematic diagram that forms channel layer.Please, form semiconductor layer 230 earlier on substrate 200 earlier with reference to Fig. 3 A.Then, provide the second shade S2, and the second shade S2 expose the semiconductor layer 230 of part in semiconductor layer 230 tops with reference to Fig. 3 B.Then, use laser L through the second shade S2 irradiating semiconductor layer 230, to remove the second shade S2 institute exposed portions semiconductor layer 230.Shown in Fig. 3 C, remaining semiconductor layer 230 constitutes channel layer 232 at last.Specifically, the laser L of present embodiment also can utilize the digit explosure mode to carry out the program of peeling off of semiconductor layer 230, and wherein the digit explosure mode has the effect of automatic location and adjustment energy, makes that the stripping technology of laser beam is more accurate.
In addition, Fig. 4 A～Fig. 4 C is a kind of above-mentioned formation source electrode 242 and 244 the manufacture method schematic diagram of draining.Please, form second conductive layer 240 earlier on channel layer 232 and gate insulator 220 earlier with reference to Fig. 4 A.Then please refer to Fig. 4 B, patterning second conductive layer 240.In detail, for example on the channel layer 232 of grid 212 both sides, form photoresist layer 250, and be that mask carries out etch process, to remove second conductive layer 240 that is not covered by photoresist layer 250 with this photoresist layer 250.Remove after the photoresist layer 250, shown in Fig. 4 C, on the channel layer 232 of grid 212 both sides, form source electrode 242 respectively and drain 244.In the present embodiment, photoresist layer 250 also is formed on the gate insulator 220 of lower floor's capacitance electrode 216 tops, with after carrying out etch process, form upper strata capacitance electrode 246, and make upper strata capacitance electrode 246 and lower floor's capacitance electrode 216 constitute reservior capacitor C.The material of second conductive layer 240 for example is aluminium (Al), molybdenum (Mo), titanium (Ti), neodymium (Nd), above-mentioned nitride such as molybdenum nitride (MoN), titanium nitride (TiN), its lamination, above-mentioned alloy or other electric conducting materials.In the present embodiment, etch process is for example for carrying out Wet-type etching, and in other embodiments, etch process also can be a dry-etching.In addition, the technology of removal photoresist layer 250 for example is wet etch process.
Certainly, in another embodiment, above-mentioned channel layer 232, source electrode 242 and draining 244 also can form simultaneously.For example, Fig. 5 A～Fig. 5 D is a kind of manufacture method schematic diagram that forms channel layer, source electrode and drain electrode simultaneously.Shown in Fig. 5 A, after forming gate insulator 220, on gate insulator 220, form the semiconductor layer 230 and second conductive layer 240 in regular turn.Then please refer to Fig. 5 B, on second conductive layer 240 of grid 212 tops, form photoresist layer 250.Shown in Fig. 5 B, photoresist layer 250 above grid 212 can be divided into the first photoresist block 250a and the second photoresist block 250b that is positioned at the first photoresist block 250a both sides, and the thickness of the first photoresist block 250a is less than the thickness of the second photoresist block 250b, in the present embodiment, forming first photoresist block 250a of photoresist layer 250 and the method for the second photoresist block 250b for example is through semi-modulation type photomask technology or grey mode photo-marsk process, in other embodiments, forming first photoresist block 250a of photoresist layer 250 and the method for the second photoresist block 250b also can for example be to use laser to form through shade (not indicating) the photic resist layer 250 of irradiation.Then, please continue the B with reference to Fig. 5, be that mask carries out first etch process to second conductive layer 240 with photoresist layer 250.Afterwards, reduce the thickness of photoresist layer 250, removed fully up to the first photoresist block 250a, shown in Fig. 5 C, the method that wherein reduces photoresist layer 250 thickness for example is to adopt the mode of ashing.Please continue the C with reference to Fig. 5, after the first photoresist block 250a is removed fully, be that mask carries out second etch process to the semiconductor layer 230 and second conductive layer 240 with the remaining second photoresist block 250b again.In the present embodiment, first etch process is for example for carrying out Wet-type etching, and in other embodiments, etch process also can be a dry-etching.Then, please refer to Fig. 5 D, after the technology of removing remaining photoresist layer 250, remaining second conductive layer 240 constitutes source electrode 242 and drain electrode 244, and semiconductor layer 230 constitutes channel layer 232.In the present embodiment, the technology of removal photoresist layer 250 for example is wet etch process.Certainly, in the present embodiment, photoresist layer 250 comprises the top that is formed at lower floor's capacitance electrode 216.
Fig. 6 A～Fig. 6 F is the another kind of manufacture method schematic diagram that forms channel layer, source electrode and drain electrode simultaneously.Channel layer 232, source electrode 242 and draining 244 also can form simultaneously.As shown in Figure 6A, after forming gate insulator 220, on gate insulator 220, form the semiconductor layer 230 and second conductive layer 240 in regular turn.Then please refer to Fig. 6 B, photoresist layer 250 above grid 212 can be divided into the first photoresist block 250a and the second photoresist block 250b that is positioned at the first photoresist block 250a both sides, and the thickness of the first photoresist block 250a is less than the thickness of the second photoresist block 250b, in the present embodiment, forming first photoresist block 250a of photoresist layer 250 and the method for the second photoresist block 250b for example is through semi-modulation type photomask technology or grey mode photo-marsk process, in other embodiments, forming first photoresist block 250a of photoresist layer 250 and the method for the second photoresist block 250b also can for example be to use laser to form through shade (not indicating) the photic resist layer 250 of irradiation.Continuing it, please refer to Fig. 6 C, is that mask carries out first etch process to second conductive layer 240 with photoresist layer 250, and continuation is that mask carries out second etch process to semiconductor layer 230 with photoresist layer 250.Afterwards, shown in Fig. 6 D, reduce the thickness of photoresist layer 250, removed fully up to the first photoresist block 250a, the method that wherein reduces photoresist layer 250 thickness for example is to adopt the mode of ashing.Then, please refer to Fig. 6 E, being mask with the remaining second photoresist block 250b carries out the 3rd etch process to second conductive layer 240 of grid 212 tops, and to continue with the remaining second photoresist block 250b be that mask carries out the 4th etch process to semiconductor layer 230.Afterwards, please refer to Fig. 6 F, after the technology of removing remaining photoresist layer 250, remaining second conductive layer 240 constitutes source electrode 242 and drains 244, and semiconductor layer 230 constitutes channel layer 232.What deserves to be mentioned is, the above-mentioned manufacture method that forms channel layer, source electrode and drain electrode simultaneously can be utilized second etch technology or four etch processs, certainly, in other embodiments, the manufacture method that forms channel layer, source electrode and drain electrode simultaneously also can only be utilized one time etch process, and the present invention does not limit the etching number of times of the manufacture method that forms channel layer, source electrode and drain electrode simultaneously.
Fig. 7 A～Fig. 7 E forms channel layer 232, source electrode 242 and 244 the manufacture method schematic diagram of draining simultaneously for another kind of.At first please refer to Fig. 7 A, after forming gate insulator 220, on gate insulator 220, form the semiconductor layer 230 and second conductive layer 240 in regular turn, and on second conductive layer 240 of grid 212 tops, form patterning photoresist layer 252.Then, shown in Fig. 7 B, with patterning photoresist layer 252 is mask, remove 252 exposed second conductive layer 240 of patterning photoresist layer, the method that wherein removes second conductive layer 240 is for example for carrying out Wet-type etching, and the material of semiconductor layer 230 can be the combination of amorphous silicon, polysilicon, microcrystal silicon, monocrystalline silicon or above-mentioned material.In addition, in other embodiments, also can form ohmic contact layer (not indicating) earlier on the surface of semiconductor layer 230, wherein the making material of ohmic contact layer and purpose such as above-mentioned are not repeated in this.
Please continue 7C, use laser L to divest partially patterned photoresist layer 252, so that patterning photoresist layer 252 exposes second conductive layer 240 of part with reference to figure.Specifically, the laser L of present embodiment also can utilize the digit explosure mode to carry out divesting of patterning photoresist layer 252, and wherein the digit explosure mode has the effect of automatic location and adjustment energy, makes that the stripping technology of laser beam is more accurate.Then, be mask with the patterning photoresist layer 252 and second conductive layer 240 again, remove part semiconductor layer 230, the method that wherein removes semiconductor layer 230 can be utilized etc. and to reach to etch process to etch process or non-etc..It should be noted that; shown in Fig. 7 C; in the step that removes semiconductor layer 230; second conductive layer 240 can be used as protective layer; the semiconductor layer of avoiding being positioned at grid 212 tops 230 is removed; therefore, this step also can be carried out before use laser L divests partially patterned photoresist layer 252.Then, please refer to Fig. 7 D, with patterning photoresist layer 252 is mask, remove second conductive layer 240 that patterning photoresist layer 252 is exposed, constitute source electrode 242 and drain 244 so that be positioned at second conductive layer 240 of grid 212 tops, and be positioned at the semiconductor layer 230 formation channel layers 232 of grid 212 tops.At last, shown in Fig. 7 E, behind the removal patterning photoresist layer 252, grid 212, channel layer 232, source electrode 242 and the 244 formation thin-film transistors 260 that drain.Certainly, in the present embodiment, patterning photoresist layer 252 comprises the top that is formed at lower floor's capacitance electrode 216, with when forming source electrode 242 and drain electrode 244, forms upper strata capacitance electrode 246.It should be noted that, present embodiment is different from known technology, utilize laser L to come the pattern of define pattern photoresist layer 252, and then form channel layer 232, source electrode 242 simultaneously and 244 the making of draining, therefore can reduce the technology of one photomask and the cost of photomask.In addition, the method for above-mentioned formation patterning protective layer 272 for example is after forming thin-film transistor 260, forms protective layer 270 on gate insulator 220 and thin-film transistor 260.Then, patterning protective layer 270 again.In another embodiment, the method that forms patterning protective layer 272 also can for example use laser lift-off to make.Fig. 8 A～Fig. 8 C is a kind of laser lift-off manufacture method schematic diagram that forms the patterning protective layer.Please earlier with reference to Fig. 8 A; after forming thin-film transistor 260,, on gate insulator 220 and thin-film transistor 260, form protective layer 270 then as Fig. 8 B; and provide the 3rd shade S3 in protective layer 270 tops, and the 3rd shade S3 exposes the protective layer 270 of part.Then, use laser L through the 3rd shade S3 irradiation protective layer 270, to remove the 3rd shade S3 institute exposed portions protective layer 270.At last, shown in Fig. 8 C, form patterning protective layer 272.It should be noted that Fig. 8 C is not for carrying out the schematic diagram of the etch process of gate insulator 220 as yet.Specifically, the laser L of present embodiment also can utilize the digit explosure mode to carry out the making of patterning protective layer 272, and wherein the digit explosure mode has the effect of automatic location and adjustment energy, makes that the stripping technology of laser beam is more accurate.
Second embodiment
Fig. 9 A～Fig. 9 I is the schematic diagram of production method of pixel structure in the second embodiment of the present invention, and the method that wherein forms channel layer 232 for example is to utilize above-mentioned Fig. 3 A～Fig. 3 C to make.In addition, form source electrode 242 and 244 the manufacture method of draining can utilize above-mentioned Fig. 4 A～Fig. 4 C or Fig. 5 A～5D to make, or make with above-mentioned Fig. 7 A～Fig. 7 E.Because the step of Fig. 9 A～Fig. 9 F is similar to Fig. 2 A～Fig. 2 F of first embodiment, so locate that the descriptions thereof are omitted.
Please refer to Fig. 9 G, after forming patterning protective layer 272, baking patterning protective layer 272 is so that the top surface of patterning protective layer 272 protrudes from the sidewall of this patterning protective layer.In the present embodiment, the top surface of patterning protective layer 272 presents gill fungus shape top surface M in fact.What deserves to be mentioned is; fabrication errors such as the temperature of necessary consideration baking process, firing rate, heating time on practice; therefore the shape of patterning protective layer 272 may produce a little variation because of fabrication error; the rough sidewall that protrudes from of its top surface makes its shape present gill fungus shape pattern haply, but the top surface shape of patterning protective layer 272 of the present invention is not as limit.
Then, please refer to Fig. 9 H, form electrode material layer 280, with overlay pattern protective layer 272 and exposed drain 244, and the method for formation electrode material layer 280 for example is to form indium tin oxide layer or indium-zinc oxide layer by sputter.Because it is the top surface M of gill fungus shape that the top surface of patterning protective layer 272 protrudes from the sidewall of patterning protective layer 272, therefore when forming electrode material layer 280, can form two parts electrode material layer 280A and the 280B that is electrically insulated.Part electrode material layer 280A is formed on the patterning protective layer 272, and another part electrode material layer 280B then is formed at substrate 200 and drains on 244.Wherein, part then constitutes pixel electrode 282 with the drain electrode 244 electrode material layer 280B that are connected.It should be noted that; be different from known technology; utilize the top surface of patterning protective layer 272 to protrude from the design of patterns of the sidewall of this patterning protective layer in the present embodiment; synchronization patternization when forming electrode material layer 280; make and finish pixel electrode 282; therefore can reduce one photo-marsk process, and reduce the complexity of technology.
Generally speaking, after forming pixel electrode 282, more patterning protective layer 272 can be removed, shown in Fig. 9 I.The method that removes patterning protective layer 272 for example uses stripper in the surface of patterning protective layer 272 with electrode material layer 280, make patterning protective layer 272 basal surface because of the intrusion of stripper from thin-film transistor 260 surfaces or gate insulator 220 sur-face peelings.
Based on above-mentioned; the present invention is in the making of pixel electrode; be different from known technology use one photomask carry out pixel electrode making; but when forming electrode material layer; by the direct patterned electrodes material layer of the patterning protective layer of suitable pattern; to form pixel electrode, therefore has the advantage that reduces processing step than known technology.And the present invention adopts the mode of laser radiation to form semiconductor layer, but not adopts known photoengraving carving technology, and therefore production method of pixel structure proposed by the invention has following advantage at least:
1. the production method of pixel structure that proposes of the present invention, its pixel electrode technology need not used photoetching process, so than the employed high accuracy photo-marsk process of photoetching process, can reduce the cost of manufacture of photomask.
2. because to make the technology of dot structure less, can reduce the defective that tediously long photo-marsk process (divest as photoresist coating, soft roasting, hard roasting, exposure, development, etching, photoresist etc.) is produced when making dot structure.
3. the method for laser lift-off part semiconductor layer proposed by the invention can be applied to the repairing of the pixel electrode in the pixel repairing, with in dot structure technology, remove the residual pixel electrode (ITOresidue) of possibility, solve the short circuit problem between the pixel electrode, and then increase the production qualification rate.
4. utilize the digit explosure mode and can adjust energy, therefore can improve the production qualification rate so that laser beam is located automatically according to the material of rete and thickness.
Though the present invention with preferred embodiment openly as above; but it is not in order to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the scope that claim defined of enclosing.
Claims (21)
1. production method of pixel structure comprises:
Substrate is provided;
Form first conductive layer on this substrate;
Provide first shade in this first conductive layer top, and this first shade expose this first conductive layer of part;
Use laser to shine this first conductive layer, removing this first shade institute this first conductive layer of exposed portions, and form grid through this first shade;
Form gate insulator on this substrate, to cover this grid;
Form channel layer on this gate insulator of this grid top;
Form source electrode and drain on this channel layer of these grid both sides, and this grid, this channel layer, this source electrode and should drain electrode constitute thin-film transistor;
Form the patterning protective layer on this thin-film transistor, to cover this channel layer and to expose this drain electrode; And
Form electrode material layer, covering this drain electrode of this patterning protective layer and exposure, and make this electrode material patterning, with the formation pixel electrode by this patterning protective layer.
2. production method of pixel structure as claimed in claim 1 also is included in after the formation patterning protective layer, toasts this patterning protective layer, so that the top surface of this patterning protective layer protrudes from the sidewall of this patterning protective layer.
3. production method of pixel structure as claimed in claim 2, wherein the top surface of patterning protective layer is a gill fungus shape top surface.
4. production method of pixel structure as claimed in claim 1 also is included in after this pixel electrode of formation, removes this patterning protective layer.
5. production method of pixel structure as claimed in claim 1, the method that wherein forms this channel layer comprises:
Form semiconductor layer on this substrate; And
This semiconductor layer of patterning is to form this channel layer.
6. production method of pixel structure as claimed in claim 1, the method that wherein forms this channel layer comprises:
Form semiconductor layer on this substrate;
Provide second shade in this semiconductor layer top, and this second shade expose this semiconductor layer of part; And
Use laser to shine this semiconductor layer, to remove this second shade institute this semiconductor layer of exposed portions through this second shade.
7. production method of pixel structure as claimed in claim 1, the method that wherein forms this source electrode and this drain electrode comprises:
Form second conductive layer on this channel layer and this gate insulator; And
This second conductive layer of patterning is to form this source electrode and this drain electrode.
8. production method of pixel structure as claimed in claim 1, the method that wherein forms this patterning protective layer comprises:
Form protective layer on this thin-film transistor; And
This protective layer of patterning.
9. production method of pixel structure as claimed in claim 1, the method that wherein forms this patterning protective layer comprises:
Form protective layer on this thin-film transistor;
Provide the 3rd shade in this protective layer top, and the 3rd shade expose this protective layer of part; And
Use laser to shine this protective layer, to remove the 3rd shade institute this protective layer of exposed portions through the 3rd shade.
10. production method of pixel structure as claimed in claim 1, the method that wherein forms this first conductive layer comprises that selecting one by sputter, evaporation and other film deposition techniques forms.
11. production method of pixel structure as claimed in claim 1, wherein the energy of this laser is between 10mJ/cm
2To 500mJ/cm
2Between.
12. production method of pixel structure as claimed in claim 1, wherein this Wavelength of Laser is between between the 100nm to 400nm.
13. production method of pixel structure as claimed in claim 1, wherein this patterning protective layer comprise be formed at the part this gate insulator on.
14. production method of pixel structure as claimed in claim 1, wherein the composition of this patterning protective layer comprises organic photo anti-corrosion agent material.
15. production method of pixel structure as claimed in claim 1, also be included in and form lower floor's capacitance electrode when forming this grid, and when forming this source electrode and drain electrode, form the upper strata capacitance electrode, wherein this lower floor's capacitance electrode and this upper strata capacitance electrode constitute reservior capacitor.
16. production method of pixel structure as claimed in claim 1, wherein this substrate is glass or plastic cement.
17. production method of pixel structure as claimed in claim 1, wherein this channel layer is amorphous silicon or n type doped amorphous silicon.
18. production method of pixel structure as claimed in claim 1, wherein the material of this first conductive layer is aluminium, molybdenum, titanium, neodymium, molybdenum nitride, titanium nitride, or the combination of aforementioned material.
19. production method of pixel structure as claimed in claim 1, wherein the material of this source electrode and drain electrode is aluminium, molybdenum, titanium, neodymium, molybdenum nitride, titanium nitride, or the combination of aforementioned material.
20. production method of pixel structure as claimed in claim 1, wherein the material of this electrode material layer is indium tin oxide or indium-zinc oxide.
21. production method of pixel structure as claimed in claim 1 wherein uses the step of laser also to comprise: utilize the digit explosure mode to carry out laser beam location and adjustment energy automatically.
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| CN200710305315A CN100587944C (en) | 2007-12-26 | 2007-12-26 | Pixel structure manufacturing method |
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| CN200710305315A CN100587944C (en) | 2007-12-26 | 2007-12-26 | Pixel structure manufacturing method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102496625A (en) * | 2011-08-15 | 2012-06-13 | 友达光电股份有限公司 | Thin film transistor, pixel structure and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102496625A (en) * | 2011-08-15 | 2012-06-13 | 友达光电股份有限公司 | Thin film transistor, pixel structure and manufacturing method thereof |
| US9117915B2 (en) | 2011-08-15 | 2015-08-25 | Au Optronics Corporation | Thin film transistor, pixel structure and method for fabricating the same |
| CN102496625B (en) * | 2011-08-15 | 2016-06-22 | 友达光电股份有限公司 | Thin film transistor, pixel structure and manufacturing method thereof |
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