CN101192830B - Circuit for transferring data, device with the circuit and data transmission method - Google Patents
Circuit for transferring data, device with the circuit and data transmission method Download PDFInfo
- Publication number
- CN101192830B CN101192830B CN200710186989XA CN200710186989A CN101192830B CN 101192830 B CN101192830 B CN 101192830B CN 200710186989X A CN200710186989X A CN 200710186989XA CN 200710186989 A CN200710186989 A CN 200710186989A CN 101192830 B CN101192830 B CN 101192830B
- Authority
- CN
- China
- Prior art keywords
- circuit
- signal
- mentioned
- power supply
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
- Manipulation Of Pulses (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention provides circuitry and method for transferring data, and circuitry and method utilizing clock pulses. A variable power supply voltage generator generates a variable power supply voltage Vvar and supplies it to other circuits. A transmitting circuit, operative at the variable power supply voltage Vvar, generates multi-value analog signals Smulti and transmits them to other circuits. A receiving circuit, operative at the variable power supply voltage Vvar, receives the multi-value analog signals Smulti and subjects them to A/D conversion to generate multi-value digital signals. The threshold voltage generator generates threshold voltages used for A/D conversion from the variable power supply voltage Vvar or from a signal having a voltage value proportional to that of the variable power supply voltage Vvar and supplies them to the receiving circuit. An analog clock generator generates an analog clock signal having a cyclical analog waveform. In response to the analog clock signal, a clock pulse generator generates a clock pulse signal having a cycle period of 1/N of the cycle period of the analog clock signal. The clock-synchronous circuits operate synchronously with the clock pulse signals generated by the clock pulse generator.
Description
The application advocates Japanese publication 2006-319718 number that proposed on November 28th, 2006 and Japanese publication 2006-319722 number and the priority of the Japanese publication that proposed on September 20th, 2007 2007-243339 number, as reference, the application comprises whole disclosures of above-mentioned application.
Technical field
The present invention relates to the circuit and the method for carrying out the circuit and the method thereof of transfer of data and utilizing clock pulse.
Background technology
Usually use digital signal to carry out transfer of data.But, in recent years also the someone attempt using many-valued analog signal to carry out transfer of data (for example Japanese kokai publication hei 7-193605 communique, TOHKEMY 2000-47768 communique, TOHKEMY 2001-285388 communique, TOHKEMY 2002-152029 communique).In addition, in order to cut down the power consumption in the computer system, having adopted the supply voltage that makes each circuit in the system of offering is variable technology (Japanese kokai publication hei 8-44465 communique).
Yet, in the device that uses variable power supply voltage,, be difficult to convert many-valued analog signal to multivalue digital signal such problem uniquely so exist because supply voltage is variable.
In addition, well-known, in the device that uses electronic signal or light signal, be that each circuit and clock pulse are synchronously moved (for example TOHKEMY 2006-259753 communique) mostly.
Yet, when a plurality of circuit in device transmit high-frequency clock pulse, have high-frequency noise and the such problem of the easy deterioration of impulse waveform of being easy to generate.
Summary of the invention
First purpose of the present invention is, a kind of technology that can many-valued analog signal suitably be converted to multivalue digital signal in the device that uses variable power supply voltage is provided.
In addition, second purpose of the present invention is, a kind of technology that can reduce the transmitting range of clock pulse is provided.
The circuit of one aspect of the present invention is the circuit that carries out transfer of data, and it has: the variable power supply voltage generation circuit, and it generates variable power supply voltage; Many-valued analog signal generative circuit, it moves under above-mentioned variable power supply voltage, generates many-valued analog signal and sends to other circuit; The multivalue digital signal generative circuit, it moves under above-mentioned variable power supply voltage, receives above-mentioned many-valued analog signal, carries out the AD conversion and the generation multivalue digital signal; And local clock's generative circuit, it has particular phases signal generating unit, PLL circuit and threshold voltage generative circuit with crest voltage filter and bleeder circuit, this particular phases signal generating unit generates the periodic particular phases signal of the particular phases of the sinusoidal wave clock signal of expression, this PLL circuit becomes Na by the frequency that makes above-mentioned particular phases signal and doubly generates local clock's pulse signal, wherein Na is an integer, this threshold voltage generative circuit generates the threshold voltage that is used for above-mentioned AD conversion and offers above-mentioned multivalue digital signal generative circuit according to the voltage value signal that has above-mentioned variable power supply voltage or be directly proportional with above-mentioned variable power supply voltage.
According to this circuit, according to the voltage value signal that has variable power supply voltage or be directly proportional, generate the threshold voltage that is used for the AD conversion, therefore with variable power supply voltage, in the multivalue digital signal generative circuit, can suitably convert many-valued analog signal to multivalue digital signal.
In addition, can be that foregoing circuit also has sinusoidal wave clock forming circuit, this sine wave clock forming circuit generates sinusoidal wave clock signal, and send to above-mentioned many-valued analog signal generative circuit and above-mentioned multivalue digital signal generative circuit, wherein, above-mentioned variable power supply voltage is low more, the cycle of this sine wave clock signal is long more, above-mentioned many-valued analog signal generative circuit and above-mentioned multivalue digital signal generative circuit receive above-mentioned sinusoidal wave clock signal, generate the clock pulse signal in the 1/N cycle in cycle respectively with above-mentioned sinusoidal wave clock signal, and carry out action according to above-mentioned clock pulse signal, this N is the value more than 2.
According to this structure, the cycle of sinusoidal wave clock signal and clock pulse signal also changes according to variable power supply voltage, and therefore, these both sides of clock signal that can be by variable power supply voltage and they are used for reducing power consumption.
In addition, also can be that above-mentioned sinusoidal wave clock signal has the crest voltage that is directly proportional with above-mentioned variable power supply voltage, above-mentioned threshold voltage generative circuit generates above-mentioned threshold voltage according to the crest voltage of above-mentioned sinusoidal wave clock signal.
According to this structure, can generate the suitable threshold voltage that is used for the AD conversion according to sinusoidal wave clock signal.
The circuit of another aspect of the present invention is the circuit that utilizes clock pulse, and it has: simulated clock simulation clock generative circuit, its generation have the simulated clock simulation clock signal of periodic analog waveform shape; Clock pulse generating circuit, it generates the clock pulse signal in 1/N (N is the value more than the 2) cycle in the cycle with above-mentioned simulated clock simulation clock signal according to above-mentioned simulated clock simulation clock signal; And clock synchronization circuit, itself and above-mentioned clock pulse signal synchronously move.
According to this circuit, clock signal is transmitted as the simulated clock simulation clock signal, generate clock pulse signal and in clock synchronization circuit, utilize according to this simulated clock simulation clock signal, therefore, can reduce the transmitting range of clock pulse.
Also can be the cycle of the variable above-mentioned simulated clock simulation clock signal of above-mentioned simulated clock simulation clock generative circuit, the cycle of above-mentioned clock pulse signal changes according to the change in the cycle of above-mentioned simulated clock simulation clock signal.
According to this structure, can satisfy purposes such as reducing power consumption, the cycle of changing the clock pulse signal that in clock synchronization circuit, utilizes by the cycle of change simulated clock simulation clock signal.
In addition, also can be that foregoing circuit has a plurality of above-mentioned clock synchronization circuit that comprises first clock synchronization circuit and second clock synchronous circuit,
Above-mentioned clock pulse generating circuit is provided with according to each clock synchronization circuit.
According to this structure, clock pulse generating circuit is provided with according to each clock synchronization circuit, therefore, can further shorten the transmitting range of clock pulse signal.
In addition, also can be that the value of above-mentioned N can be set independently according to each clock pulse generating circuit.
In this structure, can generate clock pulse signal with the cycle that is suitable for each clock synchronization circuit.
Also can be that above-mentioned first clock synchronization circuit has many-valued analog signal generative circuit, this many-valued analog signal generative circuit synchronously moves with first clock pulse signal that is generated by first clock pulse generating circuit, generate the many-valued analog signal that expression should be transferred to the digital value of above-mentioned second clock synchronous circuit, wherein, above-mentioned first clock pulse generating circuit is provided with for above-mentioned first clock synchronization circuit, above-mentioned second clock synchronous circuit has the multivalue digital signal generative circuit, this multivalue digital signal generative circuit synchronously moves with the second clock pulse signal that is generated by the second clock pulse generation circuit, above-mentioned many-valued analog signal conversion is become multivalue digital signal, wherein, above-mentioned second clock pulse generation circuit is provided with for above-mentioned second clock synchronous circuit.
According to this structure, can use many-valued analog signal to carry out transfer of data between first clock synchronization circuit and the second clock synchronous circuit, therefore, can cut down the quantity of the holding wire that is used for transfer of data, in addition, can also further reduce high-frequency noise.
Also can be that above-mentioned simulated clock simulation clock signal has sine waveform.
In this structure, can realize most effectively that the reduction of high-frequency noise and the deterioration of impulse waveform suppress the two.
In addition, the present invention can realize in every way, for example can realize as follows; Method, circuit, circuit aggregate, device and being used to realize the function of these methods, circuit, circuit aggregate or device computer program, record the recording medium of this computer program etc.
Above-mentioned and other purpose, feature, form and advantage of the present invention will obtain further clear and definite according to the explanation of the following preferred embodiment of representing with accompanying drawing.
Description of drawings
Fig. 1 is the block diagram of expression as the structure of the computer system of one embodiment of the present of invention.
Fig. 2 is the block diagram of the internal structure of expression variable voltage/V-CLK generative circuit.
Fig. 3 is the block diagram of the internal structure of the sinusoidal wave clock forming circuit of expression.
Fig. 4 is the block diagram of the internal structure of expression local clock generative circuit.
Fig. 5 A, 5B are the block diagrams of the internal structure of expression threshold voltage generating unit.
Fig. 6 a～6f is the sequential chart of the action example of expression particular phases signal generating unit.
Fig. 7 a～7c is the sequential chart of another action example of expression particular phases signal generating unit.
Fig. 8 is the block diagram of the internal structure of expression multi-valued signal treatment circuit.
Fig. 9 is the sequential chart of the action example of expression multivalue digital signal generative circuit.
Figure 10 is the key diagram of the internal structure of expression particular phases signal generating unit.
Figure 11 is the sequential chart of the action of expression upward peak test section.
Figure 12 is the expression sequential chart of the action of peak value test section down.
Figure 13 is the key diagram that is illustrated in the summary that particular phases that preceding half period in each cycle of sinusoidal wave clock signal carries out detects.
Figure 14 is the key diagram that schematically shows the establishing method of the generation action of top peak signal and phase-detection point.
Figure 15 is the key diagram of the portable phone of the expression circuit that adopts embodiments of the invention.
Figure 16 is a key diagram example, electric bicycle (electric assisted bicycle) of expression as the moving body of the circuit that adopts embodiments of the invention.
Embodiment
Then, embodiments of the present invention are described in the following order.
A. Zhuan Zhi structure and action
B. the internal structure of particular phases signal generating unit and action
C. variation
A. Zhuan Zhi structure and action
Fig. 1 is the block diagram of expression as the structure of the computer system of one embodiment of the present of invention.This computer system has variable voltage/V-CLK generative circuit 110, sinusoidal wave clock forming circuit 120, CPU130 and memory circuit 140.
Variable voltage/V-CLK generative circuit 110 is created on the variable power supply voltage Vvar that uses in a plurality of circuit in the computer system, and generates the variable clock signal VCLK that has with the level associated frequency of variable power supply voltage Vvar.Variable power supply voltage Vvar is provided for the power supply voltage terminal Vddin of another circuit.Sinusoidal wave clock forming circuit 120 generates the sinusoidal wave clock signal Swave with the cycle that is associated with the cycle of variable clock signal VCLK according to variable clock signal VCLK.
In CPU130 and memory circuit 140, be respectively equipped with local clock's generative circuit 150 and multi-valued signal treatment circuit 160.Local clock's generative circuit 150 is according to sinusoidal wave clock signal Swave, generates local clock's pulse in cycle of the 1/N (N is the value more than 2) in the cycle with sinusoidal wave clock signal Swave.CPU130 and memory circuit 140 are circuit units of local clock's impulsive synchronization ground action of being generated with separately local clock's generative circuit 150.Multi-valued signal treatment circuits 160 in CPU130 or the memory circuit 140 generate the many-valued analog signal Smulti of the digital value that expression should transmit, and will this many-valued analog signal Smulti be transferred to the multi-valued signal treatment circuit 160 of the other side's side.In addition, after receiving many-valued analog signal Smulti, multi-valued signal treatment circuit 160 converts thereof into many-valued digital value.Many-valued analog signal Smulti is the signal with the above multi-valued signal level of 3 values.
In addition, preferably, CPU130 and memory circuit 140 constitute the semiconductor circuit of single-chip respectively.Under these circumstances, preferably, local clock's generative circuit 150 also is installed in the identical chips.
Fig. 2 is the block diagram of the internal structure of expression variable voltage/V-CLK generative circuit 110 (Fig. 1).Variable voltage/V-CLK generative circuit 110 has reference oscillator 112, PLL circuit 114 and variable voltage generative circuit 116.PLL circuit 114 has phase place comparing section 210, loop filter (LPF) 212, voltage-controlled oscillator (VCO) 214 and frequency divider 216.
Frequency divider 216 is connected with CPU130 via bus, stores the frequency division value Ma that is set by CPU130.The reference clock signal CLK0 that comprises the reference oscillator 112 generation fixed frequencies of oscillators such as quartz vibrator.
Reference clock signal CLK0 is imported into phase place comparing section 210 as reference signal.On the other hand, the fractional frequency signal DVCLK that generates by frequency divider 216 as a comparison signal be input to phase place comparing section 210.Phase place comparing section 210 generates the error signal CPS of the phase difference of expression these two signal CLK0, DVCLK.This error signal CPS is sent to the loop filter 212 that is built-in with charge pump circuit.Loop filter 212 generates and output has the voltage control signal LPS of the voltage level corresponding with the impulse level of error signal CPS and umber of pulse.
Voltage control signal LPS is provided for voltage-controlled oscillator (VCO) 214 and variable voltage generative circuit 116.The variable clock signal VCLK that voltage-controlled oscillator 214 outputs have the frequency corresponding with the voltage level of voltage control signal LPS.This variable clock signal VCLK is become 1/Ma and generates fractional frequency signal DVCLK by frequency divider 216 frequency divisions.As mentioned above, this fractional frequency signal DVCLK is sent to phase comparator 210 and carries out bit comparison mutually with reference clock signal CLK0.Its result, the frequency convergence of variable clock signal VCLK makes that the phase difference of 2 signal CLK0, DVCLK is 0.The frequency of variable clock signal VCLK after the convergence is that the frequency of reference clock signal CLK0 multiply by the value that frequency division value Ma obtains.During the value of the frequency division value Ma in rewriting frequency divider 216, CPU130 can be desired value with the frequency setting of variable clock signal VCLK.For example, when transferring to the lower pattern of power consumption, frequency division value Ma is set at littler value.
Variable voltage generative circuit 116 is according to the level of the voltage level control output voltage Vvar of the voltage control signal LPS that provides from loop filter 212.This variable voltage generative circuit 116 for example can be realized by the DC-DC transducer.The variable power supply voltage Vvar of Sheng Chenging is provided for the several circuit 120,130,140 in the computer system like this.That is, these circuit move offering under the variable power supply voltage Vvar of power supply voltage terminal Vddin.As everyone knows, the power consumption of each circuit depends on the level of supply voltage.Therefore, by reducing the level of variable power supply voltage Vvar, just can reduce the power consumption of these circuit.
In addition, in the present embodiment, the frequency of variable clock signal VCLK is also controlled according to the voltage level of voltage control signal LPS.In other words, the variable power supply voltage Vvar of the frequency of variable clock signal VCLK and system is interrelated, and the frequency of the low more then variable clock signal of variable power supply voltage Vvar VCLK is also low more.This variable clock signal VCLK is converted to sinusoidal wave clock signal Swave by sinusoidal wave clock forming circuit 120 (Fig. 1) and offers each local clock's generative circuit 150, converts local clock's pulse to by this circuit 150.Therefore, local clock's pulse is the clock with the frequency that is directly proportional with the frequency of variable clock signal VCLK.Be appreciated that according to the above description, several circuit (for example CPU130 and memory circuit 140) in the computer system move under variable power supply voltage Vvar, and, with local clock's impulsive synchronization ground action with the frequency that is directly proportional with the frequency of variable clock signal VCLK.Because these circuit move according to the speed that the frequency with variable clock signal VCLK is directly proportional, therefore, its power consumption also reduces corresponding to the frequency of variable clock signal VCLK and descends.In addition, owing to reduce with the frequency of variable clock signal VCLK, variable power supply voltage Vvar also reduces, and therefore, can further reduce the power consumption of each circuit 130,140.
Fig. 3 is the block diagram of the internal structure of the sinusoidal wave clock forming circuit 120 of expression (Fig. 1).Sinusoidal wave clock forming circuit 120 has RAM122, latch 124, DA transducer 126, voltage amplifier 128 and frequency divider 129.In RAM122, store n waveform values K1～Kn of expression sine waveform.These waveform values K1～Kn can be rewritten by CPU130 as required.
In addition, also can substitute RAM122 and use nonvolatile memories such as EEPROM.Under the situation of using nonvolatile memory,, can realize the waveform that is consistent with the waveform characteristic of the circuit substrate that in system, uses by when dispatching from the factory, writing waveform shape.In addition,, can only store the value of 1/4 (for example during phase place 0～pi/2) in the one-period (during 2 π), determine the waveform of (pi/2～π, π～3 pi/2s, 3 pi/2s～2 π) during other by computing etc. as waveform values K1～Kn.Under these circumstances, can suppress memory capacity.
The impulsive synchronization of RAM122 and this timer clock TCLK ground, (j=1～n) upgrade reads address j output waveform value Kj according to this to reading address j seriatim.In addition, when reading address j and reach maximum n, read address j and turn back to 1 in next pulse.Therefore, periodically read n waveform values K1～Kn from RAM122 successively.
The waveform values Kj that reads from RAM122 is kept by latch 124, converts analog signal to by DA transducer 126.The output analog signal of DA transducer 126 is amplified by voltage amplifier 128 and is exported as sinusoidal wave clock signal Swave.
Because sinusoidal wave clock signal Swave and variable clock signal VCLK synchronously generate, and therefore, can be regarded as sinusoidal wave clock signal Swave and have the cycle that is directly proportional with the cycle of variable clock signal VCLK.In addition, the integral body of sinusoidal wave clock forming circuit 120 is moved being provided under the variable power supply voltage Vvar of its power supply voltage terminal Vddin, and therefore, the crest voltage Ep of sinusoidal wave clock signal Swave is the value for being directly proportional with variable power supply voltage Vvar also.More particularly, the crest voltage Ep of sinusoidal wave clock signal Swave is the maximum Kmax of waveform values Kj and variable power supply voltage Vvar are multiplied each other value (KmaxVvar) that obtains or the value that is directly proportional with it.
Fig. 4 is the block diagram of the internal structure of expression local clock's generative circuit 150 (Fig. 1).Local clock's generative circuit 150 has particular phases signal generating unit 152, PLL circuit 154 and threshold voltage generating unit 156.Particular phases signal generating unit 152 generates the periodic particular phases signal PCLK of the particular phases of the sinusoidal wave clock signal Swave of expression." particular phases " for example can use the phase place of the peak of sinusoidal wave clock signal Swave, middle site (zero crossing, zero-cross-point) phase place of position etc.
PLL circuit 154 becomes Na by the frequency that makes particular phases signal PCLK and doubly generates the pulse signal LCLK of local clock.Preferably the value of Integer N a is the fixed value of regulation, but also can at random be set the value of Integer N a by CPU 130.As described later, in the present embodiment, the cycle of particular phases signal PCLK be sinusoidal wave clock signal Swave cycle 1/2, therefore, the cycle of the pulse signal LCLK of local clock is 1/ (2Na) in the cycle of sinusoidal wave clock signal Swave.But, can be set at the 1/N (N is the value more than 2) in the cycle of sinusoidal wave clock signal Swave usually the cycle of the pulse signal LCLK of local clock.Wanting value to be set under the situation of non integer value, also can append frequency divider in the prime of PLL circuit 154 with N.In such structure, the frequency dividing ratio by regulating the frequency divider appended and the frequency Na of PLL circuit 154 can be set at the value of N the arbitrary value that comprises decimal.In addition, also the value of this N can be set at public value in a plurality of local clocks generative circuit 150, can also set the value of this N independently according to each local clock's generative circuit 150.Under the situation that is the latter, can obtain the pulse signal LCLK of local clock of appropriate frequency according to each circuit unit that comprises each local clock's generative circuit 150.
The pulse signal LCLK of local clock is provided near other circuit key elements that are located at local clock's generative circuit 150.For example, the pulse signal LCLK of local clock that is generated by the local clock's generative circuit 150 in the CPU130 is provided for each circuit key element in the CPU130.Therefore, circuit key element and the pulse signal LCLK of this local clock in the CPU130 synchronously moves.In addition, the pulse signal LCLK of local clock that is generated by the local clock's generative circuits 150 in the memory circuit 140 is provided for each circuit key element in the memory circuit 140, its result, circuit key element and the pulse signal LCLK of this local clock in the memory circuit 140 synchronously move.In this manual, will be called " local clock's synchronous circuit ", perhaps be called for short and make " clock synchronization circuit " with the circuit that the pulse signal LCLK of local clock synchronously moves.
Threshold voltage generating unit 156 is resolved by the level variation of offset of sinusoidal ripple clock signal Swave and is generated a plurality of threshold voltage vt h1～Vth3.These threshold voltage vts h1～Vth3 is provided for multi-valued signal treatment circuit 160 (Fig. 1) and is used.In addition, 1 threshold voltage vt h2 wherein also is provided for particular phases signal generating unit 152.
Fig. 5 (A) is the block diagram of the internal structure of expression threshold voltage generating unit 156 (Fig. 4).Threshold voltage generating unit 156 has crest voltage filter 158 and bleeder circuit 159.Crest voltage filter 158 is the circuit that detect the crest voltage Ep of sinusoidal wave clock signal Swave.This crest voltage Ep is generated a plurality of threshold voltage vt h1～Vth3 by bleeder circuit 159 dividing potential drops.An example of Fig. 5 (B) expression bleeder circuit 159.At this, utilize 4 resistance R 1 to generate a plurality of threshold voltage vt h1～Vth3 according to crest voltage Ep.In addition, the number of threshold voltage is not limited to 3 and can be set at number arbitrarily.In addition, can also be constructed as follows circuit: set in advance a plurality of bleeder circuits, these a plurality of bleeder circuits are used to generate the different threshold voltage of number, select 1 in above-mentioned a plurality of bleeder circuit, and utilize from the threshold voltage of selected bleeder circuit output.
Fig. 6 is the sequential chart of the action example of expression particular phases signal generating unit 152 (Fig. 4).Fig. 6 (a) represents sinusoidal wave clock signal Swave.The result of sinusoidal wave as a comparison clock signal Swave of Fig. 6 (b) expression and threshold voltage Ep/2 and the comparison signal S110 that obtains.This comparison signal S110 is the pulse signal that the middle site (with the suitable point of zero crossing of common AC sine wave signal) at sinusoidal wave clock signal Swave produces rising edge or trailing edge.The upward peak signal S111U that Fig. 6 (c) expression obtains according to this comparison signal S110.Upward peak signal S111U is the pulse signal of the upward peak position of the sinusoidal wave clock signal Swave of expression.Inversion signal/S110 of Fig. 6 (d) expression comparison signal S110, the following peak signal S111D that Fig. 6 (e) expression obtains according to this inversion signal/S110.Following peak signal S111D is the pulse signal of the following peak of the sinusoidal wave clock signal Swave of expression.Fig. 6 (f) is by logic of getting upward peak signal S111U and following peak signal S111D and the particular phases signal PCLK that obtains.This particular phases signal PCLK is the upward peak of the sinusoidal wave clock signal Swave of expression and the pulse signal of these two positions of following peak value.In other words, this particular phases signal PCLK is the signal of the phase place of the sinusoidal wave clock signal Swave of expression for the timing (is arbitrary integer at this m) of (m+1/2) π.
Fig. 7 is the sequential chart of another action example of expression particular phases signal generating unit 152.In this example, the pulse that produces particular phases signal PCLK according to the rising edge of comparison signal S110 and trailing edge.It is to represent that the phase place of sinusoidal wave clock signal Swave is the signal of the timing (is arbitrary integer at this m) of m π that this particular phases signal PCLK can be regarded as.2 kinds of particular phases signal PCLK shown in Fig. 6 (f) and Fig. 7 (c) are the signals according to each given reference phase difference (being π at this) generation pulse among the sinusoidal wave clock signal Swave.Therefore, by utilize frequency that PLL circuit 154 shown in Figure 4 makes any one particular phases signal PCLK wherein for Na doubly, can obtain the identical pulse signal LCLK of local clock.The pulse signal LCLK of this local clock is provided for multi-valued signal treatment circuit 160 (Fig. 1) with a plurality of threshold voltage vt h1～Vth3.
Fig. 8 is the block diagram of the internal structure of expression multi-valued signal treatment circuit 160 (Fig. 1).Multi-valued signal treatment circuit 160 has many-valued analog signal generative circuit 162 and multivalue digital signal generative circuit 164.After circuit received multivalue digital signal Dmulti internally, many-valued analog signal generative circuit 162 converted this multivalue digital signal Dmulti many-valued analog signal Smulti to and outputs to external circuit.At this, " internal circuit " is meant other circuit in the circuit unit (for example identical chips) that is present under the multi-valued signal treatment circuit 160.Particularly, " internal circuit " for the multi-valued signal treatment circuit 160 in being located at CPU130 is meant other circuit in the CPU130.In addition, " external circuit " is meant the circuit unit circuit external that is present under the multi-valued signal treatment circuit 160.Particularly, " external circuit " for the multi-valued signal treatment circuit 160 in being located at CPU130 is meant CPU130 other circuit (for example memory circuit 140) in addition.After receiving many-valued analog signal Smulti from external circuit, multivalue digital signal generative circuit 164 should convert multivalue digital signal Dmulti to and send to internal circuit by many-valued analog signal Smulti.In addition, many-valued analog signal Smulti is the signal with the above multi-valued signal level of 3 values.
Fig. 9 is the sequential chart of the action example of expression multivalue digital signal generative circuit 164 (Fig. 8).Trailing edge at the pulse signal LCLK of local clock carries out the AD conversion to many-valued analog signal Smulti.In this AD conversion, utilize a plurality of threshold voltage vt h1～Vth3 that provide from local clock's generative circuit 150 (Fig. 4).That is, the level of many-valued analog signal Smulti and a plurality of threshold voltage vt h1～Vth3 are compared and carry out the AD conversion, generate multivalue digital signal Dmulti.In addition, can utilize various types of AD converter as multivalue digital signal generative circuit 164.Many-valued analog signal generative circuit 162 generates many-valued analog signal Smulti by the action roughly opposite with Fig. 9.
In addition, in AD in multi-valued signal treatment circuit 160 conversion and the DA conversion, shown in the reasons are as follows of threshold voltage vt h1～Vth3 that utilization is obtained by local clock's generative circuit 150 (Fig. 4).The circuit unit (CPU130 and memory circuit 140) that comprises multi-valued signal treatment circuit 160 moves under variable power supply voltage Vvar, and multi-valued signal treatment circuit 160 also moves under this variable power supply voltage Vvar.Therefore, the many-valued level of the many-valued analog signal Smulti that is generated by many-valued analog signal generative circuit 162 is directly proportional with variable power supply voltage Vvar.Equally, the crest voltage Ep of the sinusoidal wave clock signal Swave that generates by sinusoidal wave clock forming circuit 120 also be directly proportional (with reference to Fig. 3) with variable power supply voltage Vvar.Therefore, in local clock's generative circuit 150 (Fig. 4), if detect the crest voltage Ep of sinusoidal wave clock signal Swave, and utilize this crest voltage Ep is carried out dividing potential drop and threshold voltage vt h1～Vth3 of obtaining, then can correctly carry out AD conversion and the DA relevant and change with many-valued analog signal Smulti.
In addition, the threshold voltage that uses in multi-valued signal treatment circuit 160 also can generate according to variable power supply voltage Vvar.In other words, voltage (for example crest voltage Ep of the sinusoidal wave clock signal Swave) generation that the threshold voltage of use can utilize variable power supply voltage Vvar itself or change with variable power supply voltage Vvar with being directly proportional in multi-valued signal treatment circuit 160.
In addition, always be to use not using variable power supply voltage Vvar in the system of fixing supply voltage and also can use multi-valued signal treatment circuit 160.Under these circumstances, can use fixing voltage level as one or more threshold voltages that in multi-valued signal treatment circuit 160, use.
As mentioned above, in the present embodiment, a plurality of circuit units (CPU130 and memory circuit 140) in device transmit sinusoidal wave clock signal Swave as clock signal, do not need these circuit units are transmitted high-frequency clock pulse.Therefore, can reduce and transmit the high-frequency noise that high-frequency clock pulse causes, in addition, can also avoid following the such problem of waveform deterioration that transmits the clock pulse that produces.In addition,, preferably variable voltage/V-CLK generative circuit 110 and sinusoidal wave clock forming circuit 120 are installed in the same chip, shorten the transmitting range of variable clock signal VCLK from reducing the viewpoint of high-frequency noise.
In addition, preferably, send sinusoidal wave clock signal Swave in the device circuit as much as possible, but do not need to send sinusoidal wave clock signal Swave to all circuit, also sinusoidal wave clock signal Swave can be sent to 1 or a plurality of circuit of selecting in advance.
In addition, as mentioned above, in the present embodiment, the frequency of variable clock signal VCLK and local clock signal LCLK changes with the voltage level of variable power supply voltage Vvar with being directly proportional.Therefore, the two the effect of voltage level by variable power supply voltage Vvar and clock frequency can reduce the power consumption of each circuit effectively.
And in the present embodiment, CPU130 and memory circuit 140 have multi-valued signal treatment circuit 160 respectively, use many-valued analog signal Smulti to carry out transfer of data.Therefore, compare, can on each holding wire, transmit more information at high speed with the situation of transmission of digital signals.In addition, being used to transmit the number of the holding wire of many-valued analog signal Smulti can be according to answering an information transmitted amount (being the transmitted bit width) at random to set.
B. the internal structure of particular phases signal generating unit and action
Figure 10 is the key diagram of an example of the internal structure of expression particular phases signal generating unit 152 (Fig. 4).This particular phases signal generating unit 152 has top peak value test section 300, bottom peak value test section 400, comparator 500, PLL circuit 510, control part 520 and OR circuit 530.Comparator 500 offset of sinusoidal ripple clock signal Swave and threshold voltage Ep/2 compare and generate comparison signal S110 (with reference to Fig. 6 (b)).
Top peak value test section 300 has count section 320, count value storage part 330, operation values storage part 340, mlultiplying circuit 350, operation result storage part 360 and comparing section 370.Bottom peak value test section has inverter (NOT circuit) 410, count section 420, count value storage part 430, operation values storage part 440, mlultiplying circuit 450, operation result storage part 460 and comparing section 470.Bottom peak value test section 400 can be regarded as to have top peak value test section 300 is appended structure behind the inverter 410.This inverter 410 is used for comparison signal S110 anti-phase and offer count section 420.The corresponding key element of top peak value test section 300 and bottom peak value test section 400 has identical functions respectively.PLL circuit 510 plays a role as the clock signal generating unit that is used to be created on the clock signal clks that use in the particular phases signal generating unit 152.Control part 520 offers count section 320,420 with this clock signal clk, and, provide suitable maintenance regularly (to latch regularly) to count value storage part 330,430 and operation values storage part 360,460.Top peak value test section 300 generates the 1st detection signal S111U (being also referred to as " top peak signal ") of the top peak of representing sinusoidal wave clock signal Swave in fact.Bottom peak value test section 400 generates the 2nd detection signal S111D (being also referred to as " bottom peak signal ") of the bottom peak of representing sinusoidal wave clock signal Swave in fact.The OR circuit by getting these two detection signal S111U, S111D logic and, generate final particular phases signal (being also referred to as " peak signal ") PCLK.The action of top peak value test section 300 and bottom peak value test section 400 is roughly the same, therefore, below the action of main explanation top peak value test section 300.
Figure 11 is the sequential chart of the action of expression top peak value test section 300.Top peak value test section 300 moves as described below.At first, count section 320 is transfused to comparison signal S110, and, according to the clock signal clk that provides from control part 520, successively to the comparison signal S110 that is imported be high level during in the clock pulse number count, and, successively resulting count value is outputed to comparing section 370.Then, become the low level stage at comparison signal S110 from high level, count section 320 stores count value Ui (i is the sequence number in cycle) at this moment into count value storage part 330.
In addition, in the example of Figure 11, the frequency of sinusoidal wave clock signal Swave changes terrifically, but as long as the frequency division value Ma (Fig. 2) in variable voltage/V-CLK generative circuit 110 does not change, then sinusoidal wave clock signal Swave is just for having the neat sine wave of fixed cycle.Its in Figure 12～Figure 14 too.
The operation values Ku that 340 storages of operation values storage part are set by CPU130.Mlultiplying circuit 350 multiplies each other count value Ui that is stored in the count value storage part 330 and the operation values Ku that is stored in the operation values storage part 340, and resulting operation result is stored in the operation result storage part 360.Ku=0.4 in the example of Figure 10, Figure 11.Comparing section 370 generates and output top peak signal S111U, and, to successively from the count value of count section 320 input be stored in operation result (=Ui * Ku) compare the operation result storage part 360, under the situation of their unanimities, make top peak signal S111U in specified time limit, be high level.
Figure 12 is the sequential chart of the action of expression bottom peak value test section 400.The action of bottom peak value test section 400 is except using with comparison signal S110 the signal this point after anti-phase, and is identical with the action of top peak value test section 300, therefore, omits detailed explanation.
Figure 13 is the key diagram of the summary that detects of expression particular phases in the present embodiment, that carry out in the preceding half period in each cycle of sinusoidal wave clock signal Swave.In Figure 13, the waveform of sinusoidal wave clock signal Swave is represented on top, and comparison signal S110 is represented in the bottom.In addition, hollow triangle arrow is represented peak, black triangle arrow represent to replace peak and detected, as the position (below be called " phase-detection point ") that is used for the benchmark of comparison phase place.
In the 1st the cycle N (0～2 π) of Figure 13, during a1 represent preceding 1/2 cycle (0～π), during b1 represent comparison signal S110 be high level during.In addition, among the cycle N+1 during among a2, b2 and the cycle N+2 during a3, b3 with above-mentioned during a1, b1 identical, therefore omit explanation.
Because sinusoidal wave clock signal Swave is sinusoidal wave, therefore, as during a1 center (pi/2) peak with during the center of b1 consistent.Therefore, will during from center stagger the position 0.1 after of b1 when being made as " 1 ", be equivalent to during among the a1 will during from peak the stagger regulation ratio of a1 when being made as " 1 " during position behind the d1.At this, during among the b1, from the center stagger position after 0.1 be equivalent to during b1 from the starting position to the center during be made as 100% o'clock, before the center 20% position, be relatively near the position of center.And, this position during among the a1 also for relatively near the position of peak, thereby d1 is a value near 0.1 during above-mentioned.
Similarly, for ensuing cycle N+1, during among the b2 will during from center stagger the position 0.1 after of b2 when being made as " 1 ", also be equivalent to during among the a2 will during the position behind the d2 during a2 staggering when being made as " 1 " from peak, d2 also is the value near 0.1 during this period.In addition, for cycle N+2 too, shown in Figure 13 during d3 be value near 0.1.
Like this, for comparison signal S110 be high level during, when the position after 0.1 of will staggering from the center, promptly apart from the center preceding 20% during position when being made as phase-detection point, in each cycle, the position of phase-detection point for staggering from top peak (phase place pi/2) after 0.1, with respect to the relative position of top peak for fixing.Therefore, for example can be with comparison signal S110 high level during the position after 0.1 of staggering from the center as the phase-detection point.But, also can make comparison signal S110 be high level during the center be the phase-detection point.
Figure 14 is the key diagram that schematically shows definite method of the generation action of top peak signal S111U and phase-detection point.In Figure 14, the waveform of sinusoidal wave clock signal Swave is represented on top, the bottom represent comparison signal S110, PLL circuit shown in Figure 10 510 outputs clock signal, be stored in count value Ui, top peak signal S111U, phase-detection point and peak in the count value storage part 330.
Consider the moment that cycle N+1 begins at this.At this moment, in last cycle N, count section 320 (Figure 10) is counted the clock pulse number among the b1 during shown in Figure 14, resulting count value U1 is stored in the count value storage part 330, and mlultiplying circuit 350 will make this count value " U1 " and be stored in operation values " 0.4 " in the operation values storage part 340 and multiply each other and obtain " U1*0.4 " and store in the operation result storage part 360.
Begin and sinusoidal wave clock signal Swave when reaching threshold value Ep/2 at cycle N+1, comparison signal S110 becomes high level, the counting of count section 320 beginning clock pulse numbers.Then, count value that comparing section 370 is counted count section 320 successively and " U1*0.4 " that is stored in the operation result storage part 360 compare, in count value is the stage of " U1*0.4 ", makes top peak signal S111U be high level in specified time limit.Then, comparison signal S110 become from high level low level, during stage of having finished of b2, count section 320 is rewritten as the count value " U2 " of this moment with count value " U1 " and stores in the count value storage part 330.Then, " U1*0.4 " that mlultiplying circuit 350 will have been stored is rewritten as to make this count value " U2 " and be stored in operation values " 0.4 " in the operation values storage part 340 and multiplies each other and obtain " U2*0.4 ", and stores in the operation result storage part 360.
As shown in figure 14, in the adjacent cycle, comparison signal S110 be high level during variation less, particularly under the state that the frequency of sinusoidal wave clock signal Swave is maintained fixed, because the amplitude of sinusoidal wave clock signal Swave is also for fixing, thus high level during also identical.Therefore, for d1～d3 during shown in Figure 14, in that (0～π) is made as under the situation of " 1 " and all is roughly " 0.1 ", the relative position almost fixed with respect to the top peak of each phase-detection point with 1/2 cycle.In addition, the pulse that also can produce top peak signal S111U in the timing of expression top peak value itself.Under these circumstances, be made as " 0.5 " and get final product being stored in operation values in the operation values storage part 340.For the bottom peak too.
OR circuit 530 shown in Figure 10 by getting the top peak signal S111U that obtains thus and bottom peak signal S111D logic and, generate particular phases signal PCLK.Like this, particular phases signal generating unit 152 can generate the particular phases signal PCLK fixing with respect to the relative position of peak.
C. variation
In addition, the invention is not restricted to the foregoing description or execution mode, can in the scope that does not break away from its main idea, implement in every way, for example also can carry out following such distortion.
C1. variation 1
In the above-described embodiments, suppose that following a plurality of feature is interrelated, but can at random constitute the device of a part that only has these features.
(1) adopts variable power supply voltage Vvar.
(2) adopt variable clock signal VCLK.
(3) transmit sinusoidal wave clock signal Swave and generate the pulse signal LCLK of local clock according to sinusoidal wave clock signal Swave.
(4) utilize multi-valued signal treatment circuit 160.
Particularly, be directly proportional, also can set them individually though for example suppose the level of variable power supply voltage Vvar and the cycle of sinusoidal wave clock signal Swave.Particularly, also can not exist with ... the level of variable power supply voltage Vvar and be maintained cycle of sinusoidal wave clock signal Swave fixing.Under these circumstances, preferably the crest voltage Ep of sinusoidal wave clock signal Swave is directly proportional with the level of variable power supply voltage Vvar.In addition, always be to use in the device of fixing supply voltage, also can utilize sinusoidal wave clock signal Swave at alternative variable power supply voltage Vvar.
In addition, in the above-described embodiments, suppose multi-valued signal treatment circuit 160 and synchronously carry out processing, but also can in the device that does not utilize sinusoidal wave clock signal Swave, utilize multi-valued signal treatment circuit 160 according to the clock signal of sinusoidal wave clock signal Swave generation.
C2. variation 2
In the above-described embodiments, the cycle (frequency) of supposing sinusoidal wave clock signal is variable, but can suppose that also the cycle (frequency) of sinusoidal wave clock signal is fixing.In addition, also alternative sinusoidal wave clock and utilizing has the simulated clock simulation clock signal of the periodic analog waveform shape beyond sinusoidal wave, and at this, " analog waveform shape " is meant the curvilinear waveform shape of non-rectangle ripple.In addition, from preventing the viewpoint of high-frequency noise, preferably use sinusoidal wave clock signal.
C3. variation 3
In the example of Fig. 1 and Fig. 8, suppose that the multi-valued signal treatment circuit of being located in 2 circuit units (CPU130 and memory circuit 140) 160 has many-valued analog signal generative circuit 162 and 164,2 circuit of multivalue digital signal generative circuit 130,140 respectively respectively not only as transtation mission circuit but also as receiving circuit performance function.But, many-valued analog signal generative circuit 162 usually is set in the transtation mission circuit that many-valued analog signal is sent to other circuit, generates receiving many-valued analog signal and in the receiving circuit of multivalue digital signal multivalue digital signal generative circuit 164 is set and gets final product.
C4. variation 4
The structure of Fig. 1～Fig. 5 and each circuit shown in Figure 8 is example only, the internal structure of each circuit and annexation, position etc. is set can at random changes.For example also variable voltage/V-CLK generative circuit 110 can be split up into these two of variable voltage generative circuit and V-CLK generative circuits installs.In addition, also variable voltage/V-CLK generative circuit 110 and sinusoidal wave clock forming circuit 120 can be focused in 1 circuit (chip) and install.And, also can be provided with by 1 shared local clock's generative circuit 150 of a plurality of multi-valued signal treatment circuit 160, according to each multi-valued signal treatment circuit 160 local clock's generative circuit 150 is set and substitute.
C5. variation 5
In the above-described embodiments, being assumed to various signals is signals of telecommunication, but also can use the present invention in the device of other kind signals such as use light signal.
C6. variation 6
Circuit of the present invention and device also can be applicable to portable equipments such as portable phone, portable personal computer, PDA.Applying the present invention under the situation of portable equipment, above-mentioned various effects (low-power consumption, minimizing high-frequency noise) are obvious especially.Similarly, circuit of the present invention and device also can be applicable to moving body such as vehicle, have effect same when being applied to portable equipment.
Figure 15 A, 15B are the key diagrams of portable phone that expression utilizes the circuit of embodiments of the invention.Figure 15 A represents the outward appearance of portable phone 700, and Figure 15 B represents the example of internal structure.Portable phone 700 has the control circuit 710 and the fuel cell 730 of the action of control portable phone 700.Fuel cell 730 provides power supply to control circuit 710.Control circuit 710 has MPU712 and peripheral circuit 714.MPU712 is equivalent to the CPU130 of Fig. 1, and peripheral circuit 714 comprises the circuit 110,120,130,140 of Fig. 1.In this control circuit 710, can realize the various processing that illustrated in the above-described embodiments.
Figure 16 is a key diagram example, electric bicycle (electric assisted bicycle) of expression as the moving body of the circuit that utilizes embodiments of the invention.This bicycle 800 is provided with motor 810 at front-wheel, is provided with control circuit 820 and rechargeable battery 830 on the framework of below-seat.The driven by power front-wheel that motor 810 is used to self-charging battery 830 to carry out travelling power-assisted.In addition, the power charge that will be regenerated by motor 810 in when braking is in rechargeable battery 830.Control circuit 820 is the driving of control motor and the circuit of regeneration, comprises the circuit 110,120,130,140 of Fig. 1.In this control circuit 820, also can realize the various processing that illustrated in the above-described embodiments.
Claims (7)
1. circuit that carries out transfer of data, it has:
The variable power supply voltage generation circuit, it generates variable power supply voltage;
Many-valued analog signal generative circuit, it moves under above-mentioned variable power supply voltage, generates many-valued analog signal and sends to other circuit;
The multivalue digital signal generative circuit, it moves under above-mentioned variable power supply voltage, receives above-mentioned many-valued analog signal, carries out the AD conversion and the generation multivalue digital signal; And
Local clock's generative circuit, it has particular phases signal generating unit, PLL circuit and threshold voltage generative circuit with crest voltage filter and bleeder circuit, this particular phases signal generating unit generates the periodic particular phases signal of the particular phases of the sinusoidal wave clock signal of expression, this PLL circuit becomes Na by the frequency that makes above-mentioned particular phases signal and doubly generates local clock's pulse signal, wherein Na is an integer, this threshold voltage generative circuit generates the threshold voltage that is used for above-mentioned AD conversion and offers above-mentioned multivalue digital signal generative circuit according to the voltage value signal that has above-mentioned variable power supply voltage or be directly proportional with above-mentioned variable power supply voltage.
2. circuit according to claim 1,
Foregoing circuit also has sinusoidal wave clock forming circuit, this sine wave clock forming circuit generates sinusoidal wave clock signal, and send to above-mentioned many-valued analog signal generative circuit and above-mentioned multivalue digital signal generative circuit, wherein, above-mentioned variable power supply voltage is low more, the cycle of this sine wave clock signal is long more
Above-mentioned many-valued analog signal generative circuit and above-mentioned multivalue digital signal generative circuit receive above-mentioned sinusoidal wave clock signal, generate the clock pulse signal in the 1/N cycle in cycle respectively with above-mentioned sinusoidal wave clock signal, and carry out action according to above-mentioned clock pulse signal, above-mentioned N is the value more than 2.
3. circuit according to claim 2,
Above-mentioned sinusoidal wave clock signal has the crest voltage that is directly proportional with above-mentioned variable power supply voltage,
Above-mentioned threshold voltage generative circuit generates above-mentioned threshold voltage according to the crest voltage of above-mentioned sinusoidal wave clock signal.
4. device that carries out transfer of data, it has the described circuit of claim 1.
5. device according to claim 4, said apparatus is a portable equipment.
6. device according to claim 4, said apparatus is a moving body.
7. data transmission method, it has following steps:
Generate the step of variable power supply voltage;
The many-valued analog signal generative circuit that use is moved under above-mentioned variable power supply voltage generates many-valued analog signal and sends to the step of other circuit;
The multivalue digital signal generative circuit that use is moved under above-mentioned variable power supply voltage receives above-mentioned many-valued analog signal and carries out the AD conversion, generates the step of multivalue digital signal thus; And
According to the voltage value signal that has above-mentioned variable power supply voltage or be directly proportional with above-mentioned variable power supply voltage, be created on threshold voltage that uses in the above-mentioned AD conversion and the step that offers above-mentioned multivalue digital signal generative circuit,
Wherein, utilize a plurality of threshold voltages that provide from local clock's generative circuit, level and above-mentioned a plurality of threshold voltage of many-valued analog signal compared and carry out AD conversion, generation multivalue digital signal.
Applications Claiming Priority (9)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006319722 | 2006-11-28 | ||
| JP2006-319722 | 2006-11-28 | ||
| JP2006319718 | 2006-11-28 | ||
| JP2006319718 | 2006-11-28 | ||
| JP2006319722 | 2006-11-28 | ||
| JP2006-319718 | 2006-11-28 | ||
| JP2007243339A JP5309511B2 (en) | 2006-11-28 | 2007-09-20 | Circuit and method for performing data transfer, and apparatus including the circuit |
| JP2007243339 | 2007-09-20 | ||
| JP2007-243339 | 2007-09-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101192830A CN101192830A (en) | 2008-06-04 |
| CN101192830B true CN101192830B (en) | 2011-02-16 |
Family
ID=39661132
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200710186989XA Expired - Fee Related CN101192830B (en) | 2006-11-28 | 2007-11-16 | Circuit for transferring data, device with the circuit and data transmission method |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP5309511B2 (en) |
| CN (1) | CN101192830B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106815173B (en) * | 2017-02-10 | 2021-03-19 | 联想(北京)有限公司 | Data sending and receiving method, device and system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5396240A (en) * | 1993-09-01 | 1995-03-07 | Maxtor Corporation | Missing pulse generator for gray code decoding |
| CN1322062A (en) * | 2000-04-13 | 2001-11-14 | 松下电器产业株式会社 | Sigma delta type analog-to-digital converter |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2728394B2 (en) * | 1986-08-25 | 1998-03-18 | 株式会社日立製作所 | Semiconductor integrated circuit device |
| JPH04277931A (en) * | 1991-03-05 | 1992-10-02 | Japan Radio Co Ltd | Adaptive identification level discriminating circuit |
| JPH07142929A (en) * | 1993-11-17 | 1995-06-02 | Kokusai Electric Co Ltd | Direct digital synthesizer |
| JP3866781B2 (en) * | 1994-05-26 | 2007-01-10 | セイコーエプソン株式会社 | Information processing device with improved power consumption |
| JPH09116391A (en) * | 1995-10-13 | 1997-05-02 | Pioneer Electron Corp | Receiver |
| JP4001591B2 (en) * | 1996-10-09 | 2007-10-31 | 富士通株式会社 | Signal transmission system |
| JP4099994B2 (en) * | 2002-01-07 | 2008-06-11 | 富士通株式会社 | Phase-locked loop circuit |
| JP2003229920A (en) * | 2002-02-01 | 2003-08-15 | General Res Of Electronics Inc | Center level detecting and correcting circuit for fsk demodulated signal |
| JP2006050396A (en) * | 2004-08-06 | 2006-02-16 | Sony Corp | System, device and method for radio communication and computer program |
-
2007
- 2007-09-20 JP JP2007243339A patent/JP5309511B2/en not_active Expired - Fee Related
- 2007-11-16 CN CN200710186989XA patent/CN101192830B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5396240A (en) * | 1993-09-01 | 1995-03-07 | Maxtor Corporation | Missing pulse generator for gray code decoding |
| CN1322062A (en) * | 2000-04-13 | 2001-11-14 | 松下电器产业株式会社 | Sigma delta type analog-to-digital converter |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2008160797A (en) | 2008-07-10 |
| JP5309511B2 (en) | 2013-10-09 |
| CN101192830A (en) | 2008-06-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103947116B (en) | For recovering the apparatus and method of paroxysm mode PWM (PWM) and non-return-to-zero (NRZ) data | |
| CN101039108B (en) | Delay locked loop circuit and semiconductor integrated circuit device | |
| US20190199357A1 (en) | Non-linear spread spectrum profile generator using linear combination | |
| CN1111955C (en) | Phase-locked loop circuit | |
| CN101599301B (en) | Memory and memory-writing method | |
| CN102035705B (en) | Method and system for transmitting bus data | |
| CN103947093A (en) | Device for controlling a switching mode power supply | |
| CN1156975C (en) | Clock generation circuit, serial/parallel converter and parallel/serial converter and semiconductor device | |
| CN102801403A (en) | Synchronous phase locking method for power supply and power supply | |
| CN104155630A (en) | High-speed data record storage and playback system | |
| CN100576140C (en) | Produce the circuit and the method for the clock signal of digital signal processor and storer | |
| CN101359909B (en) | Flexible waveform generator with extended range capability | |
| CN104601148A (en) | Digital voltage ramp generator | |
| CN101053197B (en) | Method and apparatus for a digital-to-phase converter | |
| CN101192830B (en) | Circuit for transferring data, device with the circuit and data transmission method | |
| JP2621414B2 (en) | Information processing device having cordless keyboard | |
| CN103179065B (en) | Offset quadrature phase-shift-keying modulator approach, device and digital signal generator | |
| CN102959862B (en) | Dispensing device, receiving system and receive-transmit system | |
| US8396112B2 (en) | Circuitry and method for transferring data, and circuitry and method utilizing clock pulses | |
| DE10343565B3 (en) | Master latch circuit with signal level shift for dynamic flip-flop has signal node charged to operating voltage during charging phase and discharged dependent on data signal during evalaution phase | |
| CN1941172A (en) | Dll driver control circuit | |
| CN101630951B (en) | Spread spectrum clock signal generator | |
| CN102136793B (en) | Frequency generator and phase interleaving frequency synchronization device and method | |
| CN100550630C (en) | Be used to generate the method and apparatus of distortionless pulse width modulatedwaveform | |
| CN101674082B (en) | Clock generating device and clock generating method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20161020 Address after: Tokyo, Japan, Japan Patentee after: GODO KAISHA IP BRIDGE 1 Address before: Tokyo, Japan Patentee before: Seiko Epson Corp. |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110216 Termination date: 20181116 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |