CN101159307A - Emitting surface semiconductor LED with nanostructure and its preparing process - Google Patents
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Abstract
The invention relates to the technical field of semiconductor photoelectronic device manufacturing, in particular to a semiconductor light emitting diode (LED) with a nanometer light emitting surface. The inventive method comprises growing a dielectric layer (12) and a metal layer (13) on a GaP layer (2) of the conventional LED, and sequentially using the metal layer (13) as a mask to etch the dielectric layer (12) and the parts outside a P type electrode (11) on the upper surface of the GaP layer (2) to obtain the LED with the nanometer light emitting surface. The method also comprises coating a layer of indium tin oxide (ITO) conducting film (10) on the nanometer light emitting surface and the upper surface of the P-type electrode (11), and preparing a P-type electrode (11) with the same structure on the P-type electrode (11) coated with the ITO conducting film (10). The invention reduces light reflex, improves device performance, and can be used in various semiconductor LEDs. Meanwhile, the invention has the advantages of simple process, low cost, and applicability to batch production.
Description
Technical field
The present invention relates to semiconductor photoelectronic device manufacturing technology field, relate in particular to a kind of semiconductor light-emitting-diode LED of nanostructure exiting surface, be suitable for multi-wavelength's LED, as ruddiness, blue light, green light LED etc.
Background technology
Semiconductor light-emitting-diode is the illumination revolution of a new generation because advantages such as its energy-saving and environmental protection and longevity are widely used in colored demonstration, lighting field.The luminous tube internal quantum efficiency is enough high at present, but external quantum efficiency is not high, and how making the photon that produces in semiconductor active region fully overflow is one of important channel of current raising LED brightness.
Because the semi-conducting material of preparation light-emitting diode and the refractive index difference of air are big, cause the little and boundary reflection rate height of shooting angle of light.If the refractive index of semi-conducting material of getting light-emitting diode is about 3.6, the critical angle that then this semiconductor and air have a common boundary is θ
1=sin
-1(1/n
1) 16.2 ° of ≈, incidence angle forms total reflection during greater than critical angle.With regard in that each is with regard to the recombination luminescence of even emission in the 4 π solid angles, the light in the critical angle only accounts for (1-cos θ
1)/2 ≈ 0.02.Light in the critical angle also has 1/3rd by return reflection surface inside.If the light that is reflected back can not will be absorbed in LED inside from other surperficial outgoing.A large amount of light losses causes the external quantum efficiency of LED low in LED inside.
At above-mentioned reason, the micro-structural that people adopt surperficial semi-conducting material is the method for structure again, utilizes scattering and diffraction principle to change light and goes out direction of light at the interface, makes the light effusion LED that will be reflected back toward LED originally.What adopt mostly at present is photoetching film version method and wet etching.Photoetching film version method is subjected to the restriction of reticle size, and nano level size is not accomplished in common photoetching, and electron beam lithography can reach nanoscale, but its cost increases greatly.The method of wet etching is subjected to the restriction of semiconductor surface material lattice structure, can be subjected to the influence of its doping content and growth quality in addition, and repeatability is not high.
Summary of the invention
The objective of the invention is to reduce because light in the light loss that the reflection of light output surface causes, provides a kind of emitting surface semiconductor LED with nanostructure and preparation method thereof, overcome the internal reflection of exiting surface.Utilize indium tin oxide ITO or metal electrode structure simultaneously, increase the expansion of injection current, light emission rate is improved, obtain high excellent product with low cost.
A kind of emitting surface semiconductor LED with nanostructure provided by the present invention, include Bragg reflecting layer DBR6, N type lower limit layer 5, the sub-active area 4 of volume, P type upper limiting layer 3 and the gallium phosphide GaP layer 2 of on substrate 7, upwards growing successively, the P type electrode of GaP layer 2 upper surface preparation, the lower surface preparation of substrate 7 has N type electrode 8, the invention is characterized in do not have the top layer of P type electrode to etch nano level concaveconvex structure aspect at the upper surface of described GaP layer 2; Also can on the upper surface of GaP layer, cover one deck indium tin oxide ITO conducting film 10, be coated with preparation isostructure P type electrode 11 on the P type electrode of indium tin oxide ITO conducting film 10 at the upper surface of GaP layer again.
The jog of described concavo-convex aspect is pressed periodic law and is distributed, and period T is 150～500nm, and the described cycle is meant till first cutting point of first cutting point to the second recessed face of first recessed aspect.
The cross section of the projection of described concavo-convex aspect is set to upright tapered, column type and grid type; Height H from the minimum point of projection to the projection peak is 300～1000nm, and wherein the diameter D of column type and grid type is 50～300nm.
Described P type electrode is the matts structure of metal framework, and the center of matts is provided with a metal round dot that communicates with the matts framework.
Described nano level scope is 50～1000nm.
A kind of method for preparing emitting surface semiconductor LED with nanostructure provided by the present invention is characterized in that, may further comprise the steps:
1) Bragg reflecting layer DBR6, N type lower limit layer 5, the sub-active area 4 of volume, P type upper limiting layer 3 and the GaP layer 2 of on substrate 7, upwards growing successively,
2) prepare P type electrode 11 at GaP layer 2 upper surface, superficial growth thickness is 200～500 dielectric layers 12 thereon earlier, and dielectric layer 12 adopts silicon dioxide SiO
2, or indium tin oxide ITO or silicon nitride SiN
X,
4) splash-proofing sputtering metal thin layer 13 on dielectric layer 12, sputtering time is 19～72s,
5) at N
2High annealing under the compression ring border, temperature are 300～400 ℃, and the time is 2～10min, and thin metal layer 13 is assembled into metal nanoparticle 13-1,
6) utilize nano-metal particle 13-1 to make mask, with inductively coupled plasma ICP lithographic technique etching dielectric layer 12, the time of etching is 5～9min, at 12 quarters of dielectric layer saturating after, make mask with the dielectric layer 12-1 after the etching, continue the upper epidermis face of etching GaP layer 2, do not have the top layer of P type electrode to etch nano level concaveconvex structure aspect at the upper surface of GaP layer 2
7) float dielectric layer 12-1 and nano-metal particle 13-1 after the etching with HF or HCl solution,
Utilizing the ICP lithographic technique, is mask with metal nanoparticle 13-1, the upper epidermis face of etching dielectric layer 12 and GaP layer 2.The ICP etch rate of metal is littler than dielectric layer 12, can be replicated in the structure of metallic particles on the dielectric layer 12, and dielectric layer 12 etchings are become discrete particles shape structure; The ICP etch rate of dielectric layer 12 is littler than GaP layer 2, can be under the shielding of the dielectric layer 12-1 after the etching, continue etching GaP layer 2 surface, etch into certain degree of depth, after removing the dielectric layer 12-1 and metal nanoparticle 13-1 after the etching, nano level upright tapered, grid type and cylindrical structure have occurred, the cycle can cover visible wavelength, the degree of depth can be controlled by etch period
8) at the lower surface sputter N of substrate 7 type electrode 8;
9) after the 7th of this process the) step is finished, also can on the upper surface of concaveconvex structure aspect and P type electrode, cover one deck indium tin oxide ITO conducting film 10 again, being coated with preparation same structure P type electrode 11 on the P type electrode of indium tin oxide ITO conducting film 10, carry out 8 more afterwards again) step.
Described silicon nitride SiN
XMiddle x is 1～5 integer; Described on dielectric layer 12 thickness of splash-proofing sputtering metal thin layer 13 be 25～100 .
A kind of emitting surface semiconductor LED with nanostructure provided by the present invention and preparation method thereof has the following advantages:
Nanostructure exiting surface of the present invention destroys out the conditioned reflex of optical interface, reduces the light reflection, makes light to overflow than conventional exiting surface and be multiplied, and improves device performance greatly.Behind deposition ITO conducting film on the concaveconvex structure aspect of GaP layer upper surface, can make the electric current evenly in the expansion of concaveconvex structure aspect, remedied the concaveconvex structure transverse current be obstructed every problem.The transparent characteristic of ITO makes light to overflow from the inside of light-emitting diode more in addition.The P type electrode of matts structure has enlarged the scope of P type ohmic contact, can make the charge carrier of injection even as quick expansion metal, makes the light-emitting area of active area increase, and the current density of average unit are increases, and promptly produces more photon.
Buckle layer structure exiting surface preparation method technological operation among the present invention is simple, controlled; The technology that has saved the nanoscale reticle mask that is difficult to make; Save cost, help producing in batches.
Description of drawings
Fig. 1, existing red light semiconductor light-emitting diode structure schematic diagram
Fig. 2, emitting surface semiconductor LED with nanostructure structural representation of the present invention: a, semiconductor LED structure schematic diagram with nano level concaveconvex structure aspect
B, be coated with the semiconductor LED structure schematic diagram of indium tin oxide ITO conducting film at the upper surface of concaveconvex structure aspect and P type electrode
Fig. 3, the semiconductor LED structure schematic diagram with nano level concaveconvex structure aspect of the present invention: the cross section of the projection of a concaveconvex structure aspect is set to upright tapered semiconductor LED structure schematic diagram; The cross section of the projection of b concaveconvex structure aspect is set to the semiconductor LED structure schematic diagram of grid type; The cross section of the projection of c concaveconvex structure aspect is set to the semiconductor LED structure schematic diagram of column type
Fig. 4, on the GaP layer, etch the technical process schematic diagram of nano level concaveconvex structure aspect: a, the top layer growth has the GaP layer of dielectric layer 12 and metal level 13, b, the top layer growth has the GaP layer of dielectric layer 12 and metal nanoparticle 13-1, c has dielectric layer 12-1 after the etching and the GaP layer of metal nanoparticle 13-1, d, the cross section of projection that has the concavo-convex aspect that is etched out of dielectric layer 12-1 after the etching and metal nanoparticle 13-1 is set to upright tapered GaP layer, e, the cross section of projection that has the concavo-convex aspect that is etched out of dielectric layer 12-1 after the etching and metal nanoparticle 13-1 is set to the GaP layer of grid type, f, the cross section of projection that has the concavo-convex aspect that is etched out of dielectric layer 12-1 after the etching and metal nanoparticle 13-1 is set to the GaP layer of column type, g, the cross section of the projection of concavo-convex aspect is set to upright tapered GaP layer, h, the cross section of the projection of concavo-convex aspect is set to the GaP layer of grid type, i, the cross section of the projection of concavo-convex aspect is set to the GaP layer of column type
Fig. 5, P electrode pattern: a have P type electrode pattern now; The P type electrode pattern of b metal framework matts of the present invention structure
1, P type electrode, 2, the GaP layer, 3, upper limiting layer, 4, active area, 5, lower limit layer, 6, the Bragg reflecting layer DBR in 40 cycles, 7, substrate, 8, N type electrode, 9, upper surface etches the GaP layer of nano level concaveconvex structure aspect, 9-1, the cross section of the projection of concavo-convex aspect is set to upright tapered GaP layer, 9-2, the cross section of the projection of concavo-convex aspect is set to the GaP layer of grid type, 9-3, the cross section of the projection of concavo-convex aspect is set to the GaP layer of column type, 10, indium tin oxide ITO conductive film layer, 11, the matts structure P type electrode of metal framework, 12, dielectric layer, dielectric layer after the 12-1 etching, 13, thin metal layer, 13-1, metal nanoparticle, T, cycle, the H height, the D diameter
Embodiment
Comparative Examples
The existing LED of preparation, as shown in Figure 1:
1) adopt metal-organic chemical vapor deposition equipment MOCVD equipment grow the successively compound Bragg reflecting layer DBR 6 of AlGaAs/AlAs, N type lower limit layer 5, the sub-active area 4 of volume, P type upper limiting layer 3 and the GaP layer 2 in 40 cycles on substrate 7, the thickness of GaP layer 2 is 8 μ m;
2) upper surface at GaP layer 2 prepares P type electrode 1, and electrode size is 100 μ m * 100 μ m, and the electrode pattern is shown in Fig. 5 a;
3) with substrate 7 attenuates, after splash-proofing sputtering metal AuGeNiAu on the substrate 7 forms N type electrode 8, carry out annealing in process, temperature is 400 ℃, the time is 40s;
4) cleavage, sintering, pressure welding.
Use light intensity test equipment that red-light LED is tested: under the 20mA constant current, average voltage is 1.95V, and light intensity is 103mcd, and luminous power is 2.345mW.
1) adopt metal-organic chemical vapor deposition equipment MOCVD equipment grow the successively compound Bragg reflecting layer DBR 6 of AlGaAs/AlAs, N type lower limit layer 5, the sub-active area 4 of volume, P type upper limiting layer 3 and the GaP layer 2 in 40 cycles on substrate 7, the thickness of GaP layer 2 is 8 μ m;
2) prepare the P type electrode of the matts structure of metal framework at GaP layer 2 upper surface, planar graph is shown in Fig. 5 b, and electrode size is 300 μ m * 300 μ m;
3) use the upper surface growth SiO of plasma enhanced chemical vapor deposition method PECVD at GaP layer 2
2 Dielectric layer 12, as shown in Fig. 4 a, SiO
2The thickness of dielectric layer 12 is 200 ;
4) at SiO
2Sputter Au thin layer 13 on the dielectric layer 12, as shown in Fig. 4 a, power is 57.7W, and the time is 22s, and the thickness of Au thin layer 13 is 30 , puts into to have N
2In the annealing furnace in compression ring border, temperature is 300 ℃, and the time is 2min, and Au thin layer 13 is assembled into Au nano particle 13-1, as shown in Fig. 4 b;
5) ICP dry etching SiO
2 Dielectric layer 12 and GaP layer 2, etch period are 4min, do not have the top layer of P type electrode to etch the upright tapered structure of nanoscale at the upper surface of GaP layer 2, and as shown in Fig. 4 d, the period T of upright tapered structure is 150nm, and height H is 300nm;
6) float SiO after the etching with HF
2Dielectric layer 12-1 and Au nano particle 13-1;
7) with substrate 7 attenuates, after splash-proofing sputtering metal AuGeNiAu on the substrate 7 forms N type electrode 8, carry out annealing in process, temperature is 400 ℃, the time is 40s;
8) cleavage, sintering, pressure welding.
Use light intensity test equipment that the projection of concaveconvex structure aspect is tested for upright tapered semiconductor red light-emitting diode.Under the 20mA constant current, average voltage is 1.96V, and light intensity is 132.5mcd, and luminous power is 2.679mW.
1) adopt metal-organic chemical vapor deposition equipment MOCVD equipment grow the successively compound Bragg reflecting layer DBR 6 of AlGaAs/AlAs, N type lower limit layer 5, the sub-active area 4 of volume, P type upper limiting layer 3 and the GaP layer 2 in 40 cycles on substrate 7, the thickness of GaP layer 2 is 8 μ m;
2) prepare the P type electrode of the matts structure of metal framework at GaP layer 2 upper surface, planar graph is shown in Fig. 5 b, and electrode size is 300 μ m * 300 μ m;
3) use the upper surface growth SiO of plasma enhanced chemical vapor deposition method PECVD at GaP layer 2
2 Dielectric layer 12, as shown in Fig. 4 a, SiO
2The thickness of dielectric layer 12 is 200 ;
4) at SiO
2Sputter Au thin layer 13 on the dielectric layer 12, as shown in Fig. 4 a, power is 57.7W, and the time is 19s, and the thickness of Au thin layer 13 is 25 , puts into to have N
2In the annealing furnace in compression ring border, temperature is 300 ℃, and the time is 5min, and Au thin layer 13 is assembled into Au nano particle 13-1, as shown in Fig. 4 b;
5) ICP dry etching SiO
2 Dielectric layer 12 and GaP layer 2, etch period are 4min, do not have the top layer of P type electrode to etch the nanoscale grating structure at the upper surface of GaP layer 2, and as shown in Fig. 4 e, the period T of bar structure is 150nm, and height H is 300nm, and diameter D is 50nm;
6) float SiO after the etching with HF
2Dielectric layer 12-1 and Au nano particle 13-1;
7) with substrate 7 attenuates, after splash-proofing sputtering metal AuGeNiAu on the substrate 7 forms N type electrode 8, carry out annealing in process, temperature is 400 ℃, the time is 40s;
8) cleavage, sintering, pressure welding.
Use light intensity test equipment that the projection of concaveconvex structure aspect is tested as the semiconductor red light-emitting diode of grid type.Under the 20mA constant current, average voltage is 1.96V, and light intensity is 135.1mcd, and luminous power is 2.65mW.
1) adopt metal-organic chemical vapor deposition equipment MOCVD equipment grow the successively compound Bragg reflecting layer DBR 6 of AlGaAs/AlAs, N type lower limit layer 5, the sub-active area 4 of volume, P type upper limiting layer 3 and the GaP layer 2 in 40 cycles on substrate 7, the thickness of GaP layer 2 is 8 μ m;
2) prepare the P type electrode of the matts structure of metal framework at GaP layer 2 upper surface, planar graph is shown in Fig. 5 b, and electrode size is 300 μ m * 300 μ m;
3) use ITO electron beam evaporation platform at the upper surface growth ITO of GaP layer 2 dielectric layer 12, as shown in Fig. 4 a, the thickness of ITO dielectric layer 12 is 300 ;
4) sputter Au thin layer 13 on ITO dielectric layer 12, as shown in Fig. 4 a, power is 57.7W, and the time is 36s, and the thickness of Au thin layer 13 is 50 , puts into to have N
2In the annealing furnace in compression ring border, temperature is 350 ℃, and the time is 5min, and Au thin layer 13 is assembled into Au nano particle 13-1, as shown in Fig. 4 b;
5) ICP dry etching ITO dielectric layer 12 and GaP layer 2, etch period is 6min, does not have the top layer of P type electrode to etch nano level grating structure at the upper surface of GaP layer 2, as shown in Fig. 4 e, the period T of grating structure is 350nm, and height H is 600nm, and diameter D is 200nm;
6) float ITO dielectric layer 12-1 and Au nano particle 13-1 after the etching with HF;
7) with substrate 7 attenuates, after splash-proofing sputtering metal AuGeNiAu on the substrate 7 forms N type electrode 8, carry out annealing in process, temperature is 400 ℃, the time is 40s;
8) cleavage, sintering, pressure welding.
Use light intensity test equipment that the projection of concaveconvex structure aspect is tested as the semiconductor red light-emitting diode of grid type.Under the 20mA constant current, average voltage is 1.97V, and light intensity is 1 34mcd, and luminous power is 2.668mW.
1) adopt metal-organic chemical vapor deposition equipment MOCVD equipment grow the successively compound Bragg reflecting layer DBR 6 of AlGaAs/AlAs, N type lower limit layer 5, the sub-active area 4 of volume, P type upper limiting layer 3 and the GaP layer 2 in 40 cycles on substrate 7, the thickness of GaP layer 2 is 8 μ m;
2) prepare the P type electrode of the matts structure of metal framework at GaP layer 2 upper surface, planar graph is shown in Fig. 5 b, and electrode size is 300 μ m * 300 μ m;
3) use the upper surface growth SiN of plasma enhanced chemical vapor deposition method PECVD at GaP layer 2
X Dielectric layer 12, as shown in Fig. 4 a, SiN
XThe thickness of dielectric layer 12 is 500 ;
4) at SiN
XSputter Au thin layer 13 on the dielectric layer 12, as shown in Fig. 4 a, power is 57.7W, and the time is 72s, and the thickness of Au thin layer 13 is 100 , puts into to have N
2In the annealing furnace in compression ring border, temperature is 400 ℃, and the time is 10min, and Au thin layer 13 is assembled into Au nano particle 13-1;
5) ICP dry etching SiN
XDielectric layer 12 and GaP layer 2, etch period are 8min, do not have the top layer of P type electrode to etch nano level cylindrical structure at the upper surface of GaP layer 2, and as shown in Fig. 4 f, the period T of cylindrical structure is 500nm, and height H is 1000nm, and diameter D is 300nm;
6) float SiN after the etching with HF
XDielectric layer 12-1 and Au nano particle 13-1;
7) growth ITO conductive film layer 10 on GaP layer 9-3 and P type electrode 11, as shown in Fig. 2 b, growth temperature is 190 ℃, and oxygen flow is 3sccm, and evaporation rate is 0.2nm/s;
8) being coated with preparation isostructure P type electrode 11 on the P type electrode 11 of indium tin oxide ITO conducting film 10, as shown in Fig. 2 b;
9) with substrate 7 attenuates, after splash-proofing sputtering metal AuGeNiAu on the substrate 7 forms N electrode 8, carry out annealing in process, temperature is 400 ℃, the time is 40s;
10) cleavage, sintering, pressure welding.
Use light intensity test equipment that the projection of concaveconvex structure aspect is tested as the semiconductor red light-emitting diode of column type.Under the 20mA constant current, average voltage is 1.98V, and light intensity is 141.5mcd, and luminous power is 2.68mW.
Adopt emitting surface semiconductor LED with nanostructure of the present invention, make the extraction efficiency of LED improve, the LED of beam intensity ratio routine improves 30%, and luminous power improves 20%.Voltage does not have significant change, and this illustrates this kind design and processes process when improving the output of LED light, and the electrical characteristics of device do not degenerate.
The nano level concaveconvex structure aspect of the exiting surface among the present invention is not only applicable to red light-emitting diode, is applicable to other various semiconductor light-emitting-diodes yet.To the LED of different wave length,, make the period T of concaveconvex structure and etching height H reach optimal value by changing thickness, annealing process and the etching condition of metal level 13.
It should be noted that at last: above embodiment only in order to the explanation the present invention and and unrestricted technical scheme described in the invention; Therefore, although this specification has been described in detail the present invention with reference to each above-mentioned embodiment,, those of ordinary skill in the art should be appreciated that still and can make amendment or be equal to replacement the present invention; And all do not break away from the technical scheme and the improvement thereof of the spirit and scope of invention, and it all should be encompassed in the middle of the claim scope of the present invention.
Claims (7)
1. emitting surface semiconductor LED with nanostructure, include Bragg reflecting layer DBR (6), N type lower limit layer (5), the sub-active area of volume (4), P type upper limiting layer (3) and the gallium phosphide GaP layer (2) of on substrate (7), upwards growing successively, the P type electrode of GaP layer (2) upper surface preparation, the lower surface preparation of substrate (7) has N type electrode (8), the invention is characterized in do not have the top layer of P type electrode to etch nano level concaveconvex structure aspect at the upper surface of described GaP layer; Also can on the upper surface of concaveconvex structure aspect and P type electrode, cover one deck indium tin oxide ITO conducting film (10) again, be coated with preparation same structure P type electrode (11) on the P type electrode of indium tin oxide ITO conducting film (10) again.
2. a kind of emitting surface semiconductor LED with nanostructure according to claim 1, it is characterized in that, the jog of described concavo-convex aspect is pressed periodic law and is distributed, the described cycle is meant that till first cutting point of first cutting point to the second recessed face of first recessed aspect, period T is 150～500nm.
3. a kind of emitting surface semiconductor LED with nanostructure according to claim 1 is characterized in that, the cross section of the projection of described concavo-convex aspect is set to upright tapered, column type and grid type; Height H from the minimum point of projection to the projection peak is 300～1000nm, and wherein the diameter D of column type and grid type is 50～300nm.
4. a kind of emitting surface semiconductor LED with nanostructure according to claim 1 is characterized in that, described P type electrode is the matts structure of metal framework, and the center of matts is provided with a metal round dot that is connected with the matts framework.
5. a kind of emitting surface semiconductor LED with nanostructure according to claim 1 is characterized in that, described nano level scope is 50～1000nm.
6. a method for preparing the described emitting surface semiconductor LED with nanostructure of claim 1 is characterized in that, may further comprise the steps:
1) Bragg reflecting layer DBR (6), N type lower limit layer (5), the sub-active area of volume (4), P type upper limiting layer (3) and the GaP layer (2) of on substrate (7), upwards growing successively,
2) prepare P type electrode (11) at GaP layer (2) upper surface, superficial growth thickness is 200～500 dielectric layers (12) thereon earlier, and dielectric layer (12) adopts silicon dioxide SiO
2, or indium tin oxide ITO or silicon nitride SiN
X,
4) go up splash-proofing sputtering metal thin layer (13) at dielectric layer (12), sputtering time is 19～72s,
5) at N
2High annealing under the compression ring border, temperature are 300～400 ℃, and the time is 2～10min, and thin metal layer (13) is assembled into metal nanoparticle (13-1),
6) utilize nano-metal particle (13-1) to make mask, with inductively coupled plasma ICP lithographic technique etching dielectric layer (12), the time of etching is 5～9min, after carving dielectric layer (12) thoroughly, make mask with the matter layer (12-1) after the etching, continue the upper epidermis face of etching GaP layer (2), do not have the top layer of P type electrode to etch nano level concaveconvex structure aspect at the upper surface of GaP layer (2)
7) float dielectric layer (12-1) and nano-metal particle (13-1) after the etching with HF or HCl solution,
8) at the lower surface sputter N type electrode (8) of substrate (7);
9) after the 7th of this process the) step is finished, also can on the upper surface of concaveconvex structure aspect and P type electrode, cover one deck indium tin oxide ITO conducting film (10) again, being coated with preparation isostructure P type electrode (11) on the P type electrode of indium tin oxide ITO conducting film (10), carry out 8 more afterwards again) step.
7. the method for emitting surface semiconductor LED with nanostructure according to claim 6 is characterized in that, described silicon nitride SiN
XMiddle x is 1～5 integer; Described thickness at the last splash-proofing sputtering metal thin layer (13) of dielectric layer (12) is 25～100 .
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2007
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