CN101150378B - Interleaving scheme of 32APSK system for low-density checksum coding - Google Patents

Abstract

This invention provides a method for interleaving bits through low density odd-even check coding (LDPC), which can get wanted compromise between error performance and error flat-bottom provided by the LDPC effectively.

Description

The interleaving scheme of the 32APSK system of low-density checksum coding

Technical field

The bit of low-density checksum (" LDPC ") coding the present invention relates to interweave in the 32APSK modulating system.Specifically, by distribute determining the bit of modulated symbol based on different bit degree (bitdegrees), can be effectively between error performance that employed LDPC sign indicating number provides and mistake flat (error floor), find the compromise that needs.

Show at Yan Li and William Ryan, be published in IEEE CommunicationsLetters, vol.9, no.1, January 2005 " Bit-Reliability Mapping inLDPC-Codes Modulation systems; " in (the bit reliability mapping in the LDPC sign indicating number modulating system), the author has studied the performance of the modulating system of the LDPC coding that adopts 8PSK.Utilize the bit reliability mapping policy of suggestion, realized surpassing the improvement in performance of the about 0.15dB of non-interleaving scheme.The author also uses the analysis tool that is called as the EXIT chart to explain this improved reason.In this interleaving scheme, considered a kind of deinterleaving method, the result shows that this method provides than non-interlacing system more performance, just, in the bit reliability mapping scheme, the LDPC sign indicating number bit of low reliability is mapped to the modulation bit of low order, and will be mapped to the bit of high-order than reliable bit.

Background technology

Forward error control (FEC) coding guarantees that for communication system data are extremely important through the reliable transmission of noisy communication channel.Based on the theory of Shannon, these channels have the capacity of representing with the every code element of bit of determining under the signal to noise ratio (snr) of determining, this is defined as shannon limit (Shannonlimit).One of most important research field is design provides the performance of approaching shannon limit with rational complexity a encoding scheme in communication and the coding theory.Shown and used the LDPC sign indicating number of belief propagation (BP) decoding to have controlled Code And Decode complexity, and the performance near shannon limit can be provided.

The LDPC sign indicating number is described by Gallager in nineteen sixty at first.The performance of LDPC sign indicating number is approached shannon limit very much.(N, the parity check matrix H definition that K) binary LDPC sign indicating number is capable by (N-K) and N is listed as with code length N and dimension K.Most of elements of matrix H are 0, and only the fraction element is 1, so matrix H is sparse.Every line display verification of matrix H and, and every tabulation shows variable, for example, bit or code element.The LDPC sign indicating number of being described by Gallager is regular, and just, parity check matrix H has the heavy and column weight of constant row.

The LDPC sign indicating number of rule can be extended to the LDPC sign indicating number of non-rule, and wherein heavily capable and column weight changes.The LDPC sign indicating number of non-rule is specified by degree distribution multinomial (the degree distribution polynomial) v (x) and the c (x) of defined variable node and check-node degree distribution respectively.More particularly, order

$v\left(x\right)=\underset{j=1}{\overset{d_{v\max }}{\mathrm{\Σ}}}{v}_j{x}^{j-1}$

With

$c\left(x\right)=\underset{j=1}{\overset{d_{c\max }}{\mathrm{\Σ}}}{c}_j{x}^{j-1}$

Variable d wherein _VmaxAnd d _CmaxBe respectively maximum variable node degree and check-node degree, and v _j(c _j) expression is the mark (fraction) on variable (verification) node of the j limit (edge) of sending from the number of degrees.

Though irregular LDPC codes expression and/or realize complicated more, in theory with experience on demonstrated degree distribution with suitable selection irregular LDPC codes be better than regular LDPC sign indicating number.Fig. 1 has illustrated the parity matrix figure of the exemplary irregular LDPC codes of code word size six.

The LDPC sign indicating number also can be represented by bipartite graph or Tanner figure.In Tanner figure, be called as the bit of a group node of variable node (or bit node), and be called as the one group parity check constraint of another group node of restraint joint (or check-node) corresponding to definition LDPC sign indicating number corresponding to code word.There are fillet in bit node and check-node.If bit node and check-node have fillet, think that then they are contiguous or adjacent.Usually, suppose that a pair of node is connected by no more than one limit.

Fig. 2 has illustrated that the bipartite graph of irregular LDPC codes as shown in Figure 1 represents.The code word size of the LDPC sign indicating number of being represented by Fig. 1 is 6 and has 4 parity checks.As shown in Figure 1, in representing, the parity matrix of LDPC sign indicating number has 91 altogether.Therefore in the Tanner figure expression as Fig. 2,6 bit nodes 201 are connected to 4 check-nodes 202 by 9 limits 203.

The LDPC sign indicating number can be decoded in many ways, such as majority logic decoding and iterative decoding.Because the structure of its parity matrix, but the LDPC sign indicating number is the majority logic decoding.Though the majority logic decoding needs minimum complexity, and (for example for the LDPC sign indicating number of some types that in parity matrix, have higher relatively row weight, Euclidean geometry LDPC and perspective geometry LDPC sign indicating number) show pretty good decoding performance, but the iterative decoding method has obtained more attention because they can obtain better compromise between complexity and performance.Different with the majority logic decoding, iterative decoding is based on the constraints of definitions type, by recalling of institute's receiving symbol handled the reliability that improves each code element.In first time iteration, iterative decoder only uses channel output as input, and each code element is produced reliability output.When subsequently, the iterative process of at every turn decoding being finished the degree of reiability of decoded symbol output is used as the input of next iteration.This decoding processing finishes when satisfying certain stop condition.After this make terminal decision based on the degree of reiability that the decoded symbol of last iteration is exported.According to the different characteristic of the degree of reiability of using when the each iteration, iterative decoding algorithm can further be divided into hard decision, soft-decision and mixing decision algorithm.Corresponding algorithms most in use is respectively iterative bit upset (BF), belief propagation (BP) and weighting bit reversal (WBF) decoding algorithm.Verified when corresponding Tanner figure be non-circulation time, the BP algorithm can be realized maximum likelihood decoding, thereby this algorithm becomes most popular coding/decoding method.The BP decoding of LDPC sign indicating number will only be discussed among the present invention who describes below.

The BP of LDPC sign indicating number is a kind of information transmission decoding.The information that sends along the limit of figure is the log-likelihood ratio that is associated with variable node corresponding to code word bits

In this expression formula, p ₀And p ₁The probability of representing related bits value 0 and 1 respectively.The BP decoding comprises two steps: horizontal step and vertical step.In horizontal step, each check-node c _mWill be based on removing from bit b _nIn addition all enter verification c _m" verification-to-bit " information of drawing of " bit-to-verification " information calculations send to adjacent node b _nIn vertical step, each bit node b _nWill be based on removing from check-node c _mIn addition all enter bit b _n" bit-to-verification " information of drawing of " verification-to-bit " information calculations send to adjacent check-node c _mRepeat these two steps up to finding available code word or reaching maximum iterations.

Because the remarkable performance of BP decoding, irregular LDPC codes all is one of best choice to a lot of application.Many communications and storage standards are as DVB-S2/DAB, Wireline ADSL, IEEE802.11n and IEEE802.16[4] [5] etc. all adopted or considering to adopt irregular LDPC codes.When considering to use irregular LDPC codes in video broadcast system, people often run into because the flat problem that causes of mistake.

The flat performance zones of the mistake of LDPC decoder can be described by the error performance curve of system.The LDPC decoder system generally shows error probability and descends fast when the quality of input signal improves.The error performance curve that produces is commonly called the waterfall curve, and corresponding zone is called as the waterfall zone.Yet, reach certain a bit after, input signal quality improves pairing error probability decrease speed and eases up, it is flat that the smooth error performance curve of generation is called as mistake.Fig. 3 has exemplarily illustrated the FER performance curve of the LDPC sign indicating number that comprises waterfall zone 301 and flat regional 302 the non-rule of mistake.

Summary of the invention

The invention discloses a kind of deinterleaving method,, be mapped as a part of low-order-modulated bit and a part of high order modulation bit wherein for LDPC sign indicating number bit with any reliability class.To specific LDPC code structure and modulator approach, can determine the optimal dividing of low order and high order modulation bit by the theoretical algorithm that is called as density evolution.

In one embodiment of the invention, provide a kind of in the 32APSK modulating system that uses the FEC sign indicating number digital communication system of interleaving bits, it comprises: can produce through the reflector of communication channel to the signal waveform of receiver, this reflector has the information source that a generation has one group of discrete bits of corresponding signal waveform; With a LDPC encoder, this encoder produces signal according to character list and is sent to signal mapper, and interweaving in mapper is a kind of discontinuous mapping, can produce the minimum threshold of the corresponding LDPC sign indicating number that is obtained by the density evolution prediction.

Distribute and the Tannner graph structure by careful selection check and bit node degree, LDPC sign indicating number of the present invention has good threshold property, can reduce the through-put power under the specific FER performance requirement.

The threshold value of LDPC sign indicating number is defined as minimum SNR value, under this value during when the code word size approach infinity, and can be so that bit error rate be arbitrarily small.

Different application has different requirements for the threshold value of LDPC sign indicating number and mistake are flat.Therefore, need a kind of decision method of design, the mapping scheme of determining by this method in the 32APSK system can provide required threshold value, keeps simultaneously that mistake is flat to be lower than specific criteria.

Description of drawings

The present invention passes through example, rather than is illustrated by the mode that limits, and in the accompanying drawings, identical reference number is represented components identical, in the accompanying drawings:

Fig. 1 is that the parity matrix of the exemplary irregular LDPC codes of code word size six is represented;

Fig. 2 has illustrated that the bipartite graph of irregular LDPC codes as shown in Figure 1 represents;

Fig. 3 has illustrated the waterfall that comprises irregular LDPC codes and the exemplary FER performance curve in the flat zone of mistake;

Fig. 4 is according to the embodiment of the invention, adopts the example communication system of LDPC sign indicating number and interlacing device and de-interlacing device;

Fig. 5 has illustrated the example of reflector among Fig. 4;

Fig. 6 has illustrated the example of receiver among Fig. 4;

Fig. 7 has illustrated the bit mapping function module in the 32APSK modulation;

Fig. 8 has illustrated the bit mapping of 32APSK code element.

Embodiment

With reference to the accompanying drawings, provide detailed description according to the program of the coded-bit mapping method of the use LDPC sign indicating number of the embodiment of the invention and this method of execution.

Though the present invention describes by the LDPC sign indicating number, should be realized that and in other sign indicating number, to use bit labeling method (bit labeling approach) equally.In addition, can in non-coded system, realize this method.

Fig. 4 is according to the embodiment of the invention, adopts the figure of the communication system with interleaver of LDPC sign indicating number.This communication system comprises reflector 401, and this reflector produces the signal waveform that sends to receiver 403 through communication channel 402.Reflector 401 comprises the information source that produces one group of discrete possible information.These information are all corresponding to a certain signal waveform.This waveform enters channel 402 and by noise degradation.Adopt the LDPC sign indicating number to reduce the interference of introducing by channel 402.For specific LDPC sign indicating number and the required flat level of mistake, can produce the interlacing rule of good threshold based on certain, in reflector 401 and receiver 403, use interleaver and deinterleaver respectively.

Fig. 5 has described the exemplary transducer in the communication system of Fig. 4, wherein adopts LDPC sign indicating number and interleaver.LDPC encoder 502 will be encoded to the LDPC code word from the information bit in source 501.Mapping from each block of information to each LDPC code word is by parity matrix (or generator matrix of the equivalence) regulation of LDPC sign indicating number.Being interweaved and modulated the LDPC code word by interleaver/modulator 503 is signal waveform.These signal waveforms are sent to transmitting antenna 504 and propagate into as shown in Figure 6 receiver.

Fig. 6 has described the exemplary receiver of Fig. 4, wherein adopts LDPC sign indicating number and deinterleaver.By reception antenna 601 received signal waveforms, and be distributed to demodulator/deinterleaver 602.By the demodulator demodulation and by the deinterleaver deinterleaves signal waveform, be distributed to the LDPC decoder 603 of the message that decoding iteratively receives afterwards, and the estimation of the code word that sends of output.Should mate with the interlacing rule that adopts by interleaver/modulator 503 by the deinterleaving rule that demodulator/deinterleaver 602 adopts.In other words, this deinterleaving scheme should satisfy the anti-rule (anti-rule) of interleaving scheme.

For specific LDPC sign indicating number and 32APSK modulation scheme, we define optimum and interweave and be discontinuous mapping means, can produce the optimal threshold of the corresponding LDPC sign indicating number that is obtained by the density evolution prediction.

As shown in Figure 7, this 32APSK bit-at every turn obtain five bit (b to the symbol mapped circuit _5i, b _5i+1, b _5i+2, b _5i+3, b _5i+4), and they are mapped as I value and Q value, i=0 wherein, 1,2 .....Mapping logic as shown in Figure 8.

In 32APSK, for i ∈ { i|0≤i≤N _{Ldpc_bits}-1, and imod5=0}, order $\left(\begin{array}{ccccc}{\tilde{b}}_i& {\tilde{b}}_{i+1}& {\tilde{b}}_{i+2}& {\tilde{b}}_{i+3}& {\tilde{b}}_{i+4}\end{array}\right)$ Be 5 bits of determining i code element.We specify N _OffsetWith the quantity of definition to the bit mapping of each code efficiency.Given LDPC sign indicating number and the flat level of mistake obtain optimum interleaving scheme by density evolution analysis.For LDPC sign indicating number, for i ∈ { i|0≤i≤N with efficient 2/3,3/4,4/5,5/6,13/15 and 9/10 _{Ldpc_bits}-1, and imod5=0} and j=0,1,2,3,4., the 32APSK interlacing rule is:

In table 1 " deviation value that interweaves among the 32APSK ", enumerated the bit offset number:.

Interlace offset values among [table 1] 32APSK

Efficient	N	offset
			3/4	72
4/5	80
		5/6	120
13/15	160
		9/10	192

So exemplarily described the present invention, should be appreciated that multiple other variation and modification in the spirit and scope of the present invention, to occur by preferred embodiment.Therefore, the purpose of claim of the present invention is all this modifications and changes that cover in true spirit of the present invention and the scope.

Claims (3)

1. the digital communication reflector of a 32APSK modulating mode, low-density checksum LDPC encoder and interleaver/modulator have wherein been adopted, LDPC encoder (502) will be encoded to the LDPC code word from the information bit of source (501), mapping from each block of information to each LDPC code word is by the parity matrix of LDPC sign indicating number or the generator matrix regulation of equivalence, being interweaved and modulated the LDPC code word by interleaver/modulator (503) is signal waveform, these signal waveforms are sent to transmitting antenna (504) and propagate into receiver, and wherein interleaver interweaves based on the LDPC coded-bit of following rule to the output of LDPC encoder:

B wherein _iBe the LDPC coded-bit of LDPC encoder output,

Be the bit of interleaver output, i ∈ { i|0≤i≤N _{Ldpc_bits}-1, and i mod 5=0}, j=0,1,2,3,4, Be the bracket function that returns the maximum integer that is less than or equal to x, N _{Ldpc_bits}The=15360th, the code word size of employed LDPC sign indicating number, and N _OffsetBe the deviant of different coding efficient, be defined as:

Efficient ?N _offset 3/4 ?72 4/5 ?80 5/6 ?120 13/15 ?160 9/10 ?192

。

2. the digital communication receiver of a 32APSK modulating mode, low-density checksum LDPC decoder and demodulator/deinterleaver have wherein been adopted, reception antenna (601) received signal waveform, and be distributed to demodulator/deinterleaver (602), by the demodulator demodulation and by the deinterleaver deinterleaves signal waveform, be distributed to the LDPC decoder (603) of the message that decoding iteratively receives afterwards, and the estimation of the code word that sends of output, wherein the deinterleaver LDPC coded-bit that interweaves by emitter terminals based on following rule decoding:

B wherein _iBe the LDPC coded-bit that the demodulator demodulation obtains,

Be the bit of deinterleaver output, i ∈ { i|0≤i≤N _{Ldpc_bits}-1, and i mod 5=0}, j=0,1,2,3,4, Be the bracket function that returns the maximum integer that is less than or equal to x, N _{Ldpc_bits}The=15360th, the code word size of employed LDPC sign indicating number, and N _OffsetBe the deviant of different coding efficient, be defined as:

Efficient N _offset 3/4 72 4/5 80 5/6 120 13/15 160 9/10 192

。

One kind in the 32APSK modulating system based on the interweave method of low-density checksum LDPC coded-bit of following rule:

B wherein _iBe the LDPC coded-bit,

Be the bit that obtains after interweaving, i ∈ { i|0≤i≤N _{Ldpc_bits}-1, and 2 i mod 5=0}, j=0,1,2,3,4,

Be the bracket function that returns the maximum integer that is less than or equal to x, N _{Ldpc_bits}The=15360th, the code word size of employed LDPC sign indicating number, and N _OffsetBe the deviant of different coding efficient, be defined as:

Efficient ?N _offset 3/4 ?72 4/5 ?80 5/6 ?120 13/15 ?160 9/10 ?192

。

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