CN101141188B - Method and apparatus for implementing cross matrix of optical synchronization digital transmission system - Google Patents
Method and apparatus for implementing cross matrix of optical synchronization digital transmission system Download PDFInfo
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Abstract
The present invention discloses a method and a device to realize cross matrix in optical synchronous digital transmission systems. The method comprises steps below: A first random access memory and a second random access memory (RAM) are arranged at both end of a time division multiplex matrix module and respectively stored with a same capacity of space division multiplex data of space division multiplex matrix. The first RAM, a time division multiplex data memory in the space division multiplex matrix module and the second RAM are cascaded. In addition, the space division multiplex data are cascaded with the time division multiplex data to search address and decode, thus obtaining final time division multiplex data. Data multiplex operation is carried out for the time division multiplex matrix module according to the final time division multiplex data. With lower logic demands, the present invention can be directly integrated into TUDX chips, thus saving considerable equipment cost and reducing equipment R&D cost and period and cost of later equipment maintenance.
Description
Technical field
The present invention relates to the Optical synchronization digital transmission technology in the communication technique field, particularly relate to the implementation method and the implement device of the cross matrix in a kind of optical synchronization digital transmission system.
Background technology
In SDH (digital synchronous system) Optical synchronization digital intersection equipment, professional allotment is all accomplished through cross board, and cross board is the veneer that is in SDH device core status.Two kinds of the cross matrix design branch AUDX (space division cross matrix) of SDH equipment and TUDX (cross-interaction matrix of time division); Wherein AUDX refer to AU (administrative unit) serve as intersect unit cross matrix, it serve as the cross matrix of intersection unit that TUDX refers to TU (tributary unit).
For transmission equipment; Space division cross is necessary indispensable functional module, and for more jumbo transmission equipment, the design demand of space division cross function occupies very large logical capacity; So generally all can the space division cross function be designed separately; Most of situation is to be designed to a space division cross plate separately, perhaps for low capacity integrated form equipment, can space division cross functional chip group and time-division interleaving function chipset be integrated on the veneer and design.
At present, along with the development of microelectric technique, it is increasing that the capacity of TUDX can design, even can accomplish that the business interface that this transmission equipment is all introduces in the design of TUDX, realizes that the full-time branch of this equipment intersects.
At this moment whether that also need the space division cross function? Answer is sure.Because the requirement of an APS (APS) switching time is arranged for transmission equipment, exactly when transmission path breaks down, it is normal that the service needed of whole network is recovered in 50ms.There is not the design of space division cross function if having only the time-division to intersect; Transmission path breaks down in the time of need carrying out the business switching; Board software just need carry out write operation to a large amount of TU intersection addresses, the time of labor, makes APS switching time index can't reach requirement.Such as switching for an AU business; Free when dividing cross matrix, only need software to write one and intersect order and get final product to the address of this AU, and if when not having the function of sky sub matrix to design; Software just need write to the register of all TU among this AU to intersect and order; Such as for TU12 be unit the time sub matrix design, need write 63 orders, 63 times time when being equivalent to spend free sub matrix design.
Since the space division cross function must design; Can construct the simple-interchange fork functional mode of under the situation that full-time branch intersects equipment so according to the functional requirement of SDH equipment; As shown in Figure 1, promptly respectively be connected in series a space division cross matrix A UDX who waits capacity in the front and back of cross-interaction matrix of time division TUDX.
Under normal conditions, the design of cross matrix is that crossing control data is write among the CM (controller), and the data flow to be intersected of all inputs is sent into buffer memory among the DM (high-speed cache), is crossed to corresponding output port according to the Data Control input traffic of CM.Like this, it is just as shown in Figure 2 respectively to be connected in series the function implementation model of an AUDX who waits capacity before and after the TUDX.Two AUDX wherein and the design of TUDX all need occupy very many logical resources.So, existing big capacity do not increase on the cross board in full-time minute extra chips just add the design of the AUDX of same capability be very the difficulty.For the equipment that full-time minute interleaving function is provided; Common design is in system, to increase a firm and hard existing AUDX of space division cross again; Perhaps design a veneer that space division cross functional chip and time-division functional chip are integrated again separately; Rather than common time-division cross board directly used as the cross board of system, this increases equipment cost and research and development maintenance cost greatly.
How can be on the basis of existing full-time minute cross board; Increase logic seldom is with regard to the function of the needed increase of realization system with the AUDX of capacity; Make this function can be integrated in the present TUDX chip; Reach full-time minute cross board and do not change the purpose that single plate hardware just directly is used as the cross board of system, become a challenging difficult problem of facing now.
Summary of the invention
The implementation method and the device that the purpose of this invention is to provide the cross matrix in a kind of optical synchronization digital transmission system; Solve prior art and realize that on the basis of time-division cross board the space division cross function needs very big logical resource, existing time-division cross board must be changed the technical problem that hardware just can divide in-one-board as the empty timesharing of full-time minute cross system.
To achieve these goals, the invention provides the implementation method of the cross matrix in a kind of optical synchronization digital transmission system, wherein, comprise the steps:
Wherein, The outgoing management unit number of space division cross matrix is represented in each address in the said random asccess memory; The input manager unit number that data represented said outgoing management unit in the said address is corresponding, thus make said space division cross data record outgoing management unit and the corresponding relation of input manager unit in the said random asccess memory.
Above-mentioned method; Wherein, Said time-division intersects each address in the data storage represents the output tributary unit number of cross-interaction matrix of time division; Said time-division intersects the high-order portion of the data in each address in the data storage represent input manager unit number, and the said time-division intersects the low portion representative of the data in each address in the data storage imports tributary unit number.
Above-mentioned method; Wherein, In step 3; Carrying out the cascade addressing decode obtains final time-division and intersects the process of data and comprise: obtained the said final time-division and intersected the administrative unit part of data by the addressing of contacting of the administrative unit data in each memory of cascade, get other crossing number of tributary unit level that the said time-division intersects in the data storage and intersect the tributary unit part of data according to obtaining the said final time-division.
Above-mentioned method; Wherein, Said polyphone addressing comprises: the administrative unit address number in the intersection data storage of corresponding said time-division of the data in each address of said second random asccess memory; The address of corresponding said first random asccess memory of high-order portion of the data in the said time-division intersection data storage, the administrative unit part of the corresponding said final time-division intersection data of the data in the address of said first random asccess memory.
In order to realize the object of the invention, the present invention also provides the implement device of the cross matrix in a kind of optical synchronization digital transmission system, wherein, comprises first random asccess memory, second random asccess memory and cross-interaction matrix of time division module; Said first random asccess memory and second random asccess memory are arranged on the two ends of said cross-interaction matrix of time division module, and the space division cross data of the space division cross matrix of capacity such as storage respectively; Time-division in said first random asccess memory, said cross-interaction matrix of time division module intersects data storage, the said second random asccess memory cascade and connects, and said cross-interaction matrix of time division module is carried out final time-division that the cascade addressing decode obtains and intersected data and carry out data cross and operate according to intersected data by said space division cross data and said time-division;
Wherein, The outgoing management unit number of space division cross matrix is represented in each address in the said random asccess memory; The input manager unit number that data represented said outgoing management unit in the said address is corresponding, thus make said space division cross data record outgoing management unit and the corresponding relation of input manager unit in the said random asccess memory.
Above-mentioned device; Wherein, Said time-division intersects each address in the data storage represents the output tributary unit number of cross-interaction matrix of time division; Said time-division intersects the high-order portion of the data in each address in the data storage represent input manager unit number, and the said time-division intersects the low portion representative of the data in each address in the data storage imports tributary unit number.
Above-mentioned device; Wherein, Said final time-division intersects the administrative unit part of data and is obtained by the addressing of contacting of the administrative unit data in each memory of cascade, and the said final time-division intersects the tributary unit of data partly gets the said time-division and intersect other crossing number certificate of tributary unit level in the data storage.
Above-mentioned device; Wherein, Said polyphone addressing comprises: said polyphone addressing comprises: the administrative unit address number in the intersection data storage of corresponding said time-division of the data in each address of said second random asccess memory; The address of corresponding said first random asccess memory of high-order portion of the data in the said time-division intersection data storage, the administrative unit part of the corresponding said final time-division intersection data of the data in the address of said first random asccess memory.
Technique effect of the present invention is:
Adopt the inventive method; Be equivalent to increase respectively the design of the AUDX of a capacity such as grade in the front and back of a TUDX; But owing to only carried out once identical crossed work with TUDX, thus the RAM of two storage AU intersection data on the logical foundations that is equivalent on the logical capacity at original TUDX, only increased, rather than increased by two AUDX that logic is in great demand; Its logic demand is very little; Can directly be integrated in the TUDX chip internal and accomplish, thereby the time-division cross board that reaches system need not to change the purpose that empty timesharing that hardware just can directly be used as full-time minute cross system divides in-one-board, has saved the large number quipments cost; Reduced the R&D costs and the cycle of equipment, the maintenance cost of post facility is declined to a great extent.
Fig. 1 is for respectively being connected in series a functional mode figure with capacity AUDX before and after the TUDX;
Fig. 2 is for respectively being connected in series a function implementation model figure with capacity AUDX before and after the TUDX;
Fig. 3 is for respectively being connected in series a function implementation model figure with capacity AUDX before and after the TUDX provided by the invention;
Fig. 4 is the intersection data path sketch map of the embodiment of the invention.
For making the object of the invention, technical scheme and advantage clearer, will combine accompanying drawing and specific embodiment to describe the present invention below.
The present invention sets up a kind of implementation model of algorithm cleverly; Feasible increase logical resource seldom; Just can realize two functions that wait the AUDX of capacity of serial connection, make this function can directly be integrated in the existing TUDX chip, like this in the front and back of jumbo TUDX; Realize in system under the situation of full-time branch intersection; The time-division cross board can be directly divides in-one-board to use as the empty timesharing of system, and plate that can unified platform product also can be saved a large amount of equipment costs and research and development maintenance cost.
The function implementation model of the inventive method is as shown in Figure 3; Mainly be on the basis of the logic of former TUDX; Increase by two block RAMs, store two intersection data that wait capacity AUDX respectively, then the storage time-division among the RAM of these two storage AUDX data and the former TUDX is intersected the RAM of data and carry out the cascade addressing decode; Calculate the intersection data of a final TUDX, carry out the data cross action of a TUDX according to these TUDX that calculates intersection data then.So for realize two functions that wait the AUDX of capacity of serial connection in the front and back of jumbo TUDX, the RAM of intersection data that has logically only increased AUDX such as capacity such as two storages grade is just passable.The logic demand is very little, can reach the purpose in the chip that is integrated into present TUDX.
For realizing that in the front and back of the TUDX of the cross-capacity that N AU arranged two of serial connections have the function of AUDX of the cross-capacity of N AU, concrete operations are narrated as follows step by step:
1) increases a RAM A, be used for storing the intersection data among No. 1 AUDX of cross-capacity of N AU.N address arranged, among corresponding No. 1 AUDX in each address output AU number, input AU number of corresponding No. 1 AUDX of the data in each address among the RAM A.Such as being crossed to b AU, being expressed as and in the b of address, writing data a for a AU.
2) increase a RAM C, be used for storing the intersection data among No. 2 AUDX of cross-capacity of N AU.N address arranged, among corresponding No. 2 AUDX in each address output AU number, input AU number of corresponding No. 2 AUDX of the data in each address among the RAM C.
3) RAM with store interleaving data among the former TUDX is defined as RAM B, and NXM address arranged among the RAM B, and (N representes to have the cross-capacity of N AU, and M representes M the intersection particle that have among each AU.If for the TUDX that presses the row cross-over design, M=270; For being the cross-over design of unit by TU12, M=63.For expressing conveniently; Below this TUDX of hypothesis is that adopting by TU12 is the pattern that unit intersects in the statement; M=63) output TU number among the corresponding TUDX in each address, the data in each address are divided into two parts, are respectively high position data part and low data part; The input AU of the corresponding TUDX of high position data part number, the input TU of the corresponding TUDX of low data part number.Such as for the b TU among a AU of TUDX, be crossed to the d TU among the c AU, can be expressed as at c
*High position data in the address of 63+d partly writes a, and low data partly writes b.
4) the data cascade addressing decode with RAM A, RAM B, RAM C is the intersection data of a TUDX.Concrete method is: the AU part of intersection data is obtained by the AU data polyphone addressing of three RAM, and the TU of intersection data partly gets other crossing number certificate of TU level among the RAM B.The polyphone addressing method of three grades of RAM is the AU address number among the corresponding RAM B of the data among the RAM C, and the high position data part among the RAM B is promptly imported the address among the corresponding RAM A of AU data, the AU part of the intersection data after last corresponding calculating of the data among the RAM A.
5) the intersection data that calculate according to three grades of RAM cascade decodings are carried out the data cross of TUDX.
Introduce an instance that utilizes the inventive method to carry out the time slot cross-over configuration below, as shown in Figure 4:
The configuration of No. 1 space division cross matrix be that No. 3 AU are crossed to AU No. 8, the data in the cross-interaction matrix of time division are No. 7 TU12 that No. 5 TU12 of No. 8 AU are crossed to No. 2 AU, the configuration of No. 2 space division cross matrixes be that No. 2 AU are crossed to AU No. 6.
Corresponding such cross-over configuration relation; The data and the address of in three RAM, storing are respectively: what the address of No. 8 AU outputs of the correspondence of RAM A write is 3; What the high position data of the address of No. 7 TU12 outputs of No. 2 AU of correspondence of RAM B partly write is 8; What low data partly write is 5, and what the address of No. 6 AU outputs of the correspondence of RAM C write is 2.
According to the inventive method, it calculates through being:
Because what the output interface of No. 2 space division cross matrixes was corresponding is total output interface of three cross matrixes, the configuration of No. 2 space division cross matrixes be that No. 2 AU are crossed to AU No. 6.Intersect data so need arrive to seek in the address of No. 2 AU of time-division cross matrix, and have No. 7 TU12 to dispose data among No. 2 AU in the cross-interaction matrix of time division, so the output interface of corresponding total intersection is No. 7 TU12 of No. 6 AU.No. 5 TU12 of low data that directly get for the TU of input interface number among the corresponding RAM B get final product; The AU data of input interface partly are 8 according to the high position data among the RAM B again; In the address of the output interface of No. 8 AU of RAM A, look for; And the address of No. 8 AU of the correspondence of RAMA output writes is 3, so AU number of the input interface that three grades of RAM cascade method for addressing calculate is 3.
The intersection result of the inputoutput data that the data computation of comprehensive three cross matrixes is come out is No. 7 TU12 that No. 5 TU12 of No. 3 AU are crossed to No. 6 AU, carries out the data cross action of conventional TUDX then according to this result of calculation.
After the inventive method is applied to the design example of time-division cross board; The capacity of the TUDX of the time-division cross board in the instance is 80G; Use if in power system capacity is the system of 80G, do the empty time-division cross board that divides, need to increase by the design of the AUDX of two 80G, the resource that occupies according to the AUDX of two 80G of conventional design is very large; Need system to increase a space division cross plate; Perhaps on the time-division cross board, increase separately design of the jumbo FPGA of a slice (field programmable gate array) again, therefore under the condition of not changing this time-division cross board hardware, plate can't be not only divides the time-division cross board as independent time-division cross board but also as the sky of 80G system.And employing the inventive method; It is just passable that the function design that increases by the AUDX of two 80G only needs to increase by two RAM, and the logic demand is very little, can be integrated in the inside of the TUDX of 80G easily; Can accomplish the versatility of this time-division cross board in the different capabilities system; Saved a large amount of equipment costs, R&D costs, and later maintenance cost.，
By on can know; Adopt the inventive method, increase a design that waits the AUDX of capacity respectively for front and back, owing to only carried out once identical crossed work with TUDX at a TUDX; So on the logical foundations that is equivalent on the logical capacity at original TUDX, only increased the RAM of two storage AU intersection data; Rather than having increased by two AUDX that logic is in great demand, the logic demand is very little, can directly be integrated in the TUDX chip internal and accomplish.Thereby the time-division cross board that reaches system need not to change the purpose that hardware just can be directly divides in-one-board as the empty timesharing of full-time minute cross system; Saved the large number quipments cost; Reduced the R&D costs and the cycle of equipment, the maintenance cost of post facility is declined to a great extent.
The above only is a preferred implementation of the present invention; Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; Can also make some improvement and retouching, these improvement and retouching also should be regarded as protection scope of the present invention.
Claims (8)
1. the implementation method of the cross matrix in the optical synchronization digital transmission system is characterized in that, comprises the steps:
Step 1 is arranged on the two ends of cross-interaction matrix of time division module with first random asccess memory and second random asccess memory, and the space division cross data of the space division cross matrix of capacity such as storage respectively;
Step 2 is carried out cascade with the intersection data storage of the time-division in said first random asccess memory, the said cross-interaction matrix of time division module, said second random asccess memory;
Step 3 is intersected data with said space division cross data and time-division and is carried out the cascade addressing decode, obtains the final time-division to intersect data, intersects data according to the said final time-division and carries out the data cross operation of said cross-interaction matrix of time division module;
The outgoing management unit number of space division cross matrix is represented in each address in said first and second random asccess memory; The input manager unit number that data represented said outgoing management unit number in the said address is corresponding, thus make said space division cross data record outgoing management unit and the corresponding relation of input manager unit in said first and second random asccess memory.
2. method according to claim 1; It is characterized in that; Said time-division intersects each address in the data storage represents the output tributary unit number of cross-interaction matrix of time division; Said time-division intersects the high-order portion of the data in each address in the data storage represent input manager unit number, and the said time-division intersects the low portion representative of the data in each address in the data storage imports tributary unit number.
3. method according to claim 2; It is characterized in that; In step 3; Carrying out the cascade addressing decode obtains final time-division and intersects the process of data and comprise: obtained the said final time-division and intersected the administrative unit part of data by the addressing of contacting of the administrative unit data in each memory of cascade, get other crossing number of tributary unit level that the said time-division intersects in the data storage and intersect the tributary unit part of data according to obtaining the said final time-division.
4. method according to claim 3; It is characterized in that; Said polyphone addressing comprises: the administrative unit address number in the intersection data storage of corresponding said time-division of the data in each address of said second random asccess memory; The address of corresponding said first random asccess memory of high-order portion of the data in the said time-division intersection data storage, the administrative unit part of the corresponding said final time-division intersection data of the data in the address of said first random asccess memory.
5. the implement device of the cross matrix in the optical synchronization digital transmission system is characterized in that, comprises first random asccess memory, second random asccess memory and cross-interaction matrix of time division module;
Said first random asccess memory and second random asccess memory are arranged on the two ends of said cross-interaction matrix of time division module, and the space division cross data of the space division cross matrix of capacity such as storage respectively;
Time-division in said first random asccess memory, said cross-interaction matrix of time division module intersects data storage, the said second random asccess memory cascade and connects, and said cross-interaction matrix of time division module is carried out final time-division that the cascade addressing decode obtains and intersected data and carry out data cross and operate according to intersected data by said space division cross data and time-division;
The outgoing management unit number of space division cross matrix is represented in each address in said first and second random asccess memory; The input manager unit number that data represented said outgoing management unit number in the said address is corresponding, thus make said space division cross data record outgoing management unit and the corresponding relation of input manager unit in said first and second random asccess memory.
6. device according to claim 5; It is characterized in that; Said time-division intersects each address in the data storage represents the output tributary unit number of cross-interaction matrix of time division; Said time-division intersects the high-order portion of the data in each address in the data storage represent input manager unit number, and the said time-division intersects the low portion representative of the data in each address in the data storage imports tributary unit number.
7. device according to claim 6; It is characterized in that; Said final time-division intersects the administrative unit part of data and is obtained by the addressing of contacting of the administrative unit data in each memory of cascade, and the said final time-division intersects the tributary unit of data partly gets the said time-division and intersect other crossing number certificate of tributary unit level in the data storage.
8. device according to claim 7; It is characterized in that; Said polyphone addressing comprises: the administrative unit address number in the intersection data storage of corresponding said time-division of the data in each address of said second random asccess memory; The address of corresponding said first random asccess memory of high-order portion of the data in the said time-division intersection data storage, the administrative unit part of the corresponding said final time-division intersection data of the data in the address of said first random asccess memory.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0796548B1 (en) * | 1994-05-25 | 2002-10-16 | Marconi Communications Limited | Non-blocking switching network |
| CN1545367A (en) * | 2003-11-19 | 2004-11-10 | 烽火通信科技股份有限公司 | Method for realizing large capacity synchronous optical network and SDH cross unit |
| CN1728617A (en) * | 2004-07-29 | 2006-02-01 | 中兴通讯股份有限公司 | Method for increasing utilization ratio of cross-interaction matrix of time division |
| CN1767418A (en) * | 2004-10-27 | 2006-05-03 | 中兴通讯股份有限公司 | Time slot collocating method for optimizing time-division resource |
-
2007
- 2007-05-23 CN CN2007100995240A patent/CN101141188B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0796548B1 (en) * | 1994-05-25 | 2002-10-16 | Marconi Communications Limited | Non-blocking switching network |
| CN1545367A (en) * | 2003-11-19 | 2004-11-10 | 烽火通信科技股份有限公司 | Method for realizing large capacity synchronous optical network and SDH cross unit |
| CN1728617A (en) * | 2004-07-29 | 2006-02-01 | 中兴通讯股份有限公司 | Method for increasing utilization ratio of cross-interaction matrix of time division |
| CN1767418A (en) * | 2004-10-27 | 2006-05-03 | 中兴通讯股份有限公司 | Time slot collocating method for optimizing time-division resource |
Non-Patent Citations (2)
| Title |
|---|
| 张金旗.同步光网络和同步数字系列大容量交叉的实现.光通信研究 总第124期.2004,(总第124期),第1-3页. |
| 张金旗.同步光网络和同步数字系列大容量交叉的实现.光通信研究 总第124期.2004,(总第124期),第1-3页. * |
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Application publication date: 20080312 Assignee: SHENZHEN ZTE MICROELECTRONICS TECHNOLOGY CO., LTD. Assignor: ZTE Corporation Contract record no.: 2017440020015 Denomination of invention: Method and apparatus for implementing cross matrix of optical synchronization digital transmission system Granted publication date: 20120509 License type: Common License Record date: 20170310 |