CN104462006A - Method and device for synchronizing configuration between multiple processor cores in system-level chip - Google Patents
Method and device for synchronizing configuration between multiple processor cores in system-level chip Download PDFInfo
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Abstract
The embodiment of the invention provides a method and device for synchronizing configuration between multiple processor cores in a system-level chip. The system-level chip comprises a synchronization module and the M processor cores, wherein M is larger than or equal to 2. The method includes the steps that the first processor core sends configuration change information to the synchronization module, wherein the first processor core is any processor core in the M processor cores, the configuration change information includes N configuration parameters to be configured and a to-be-stored address of the first configuration parameter to be configured, and N is larger than or equal to 1; the synchronization module receives the configuration change information sent by the first processor core, determines a register where each configuration parameter to be configured is to be stored according to the to-be-stored address of the first configuration parameter, and stores the N configuration parameters to be configured in the N determined registers in a one-to-one corresponding mode so as to complete the synchronization of the configuration between the M processor cores. Thus, the bus bandwidth occupied in the configuration synchronization process is reduced, and the utilization rate of the bus bandwidth is increased.
Description
Technical field
The embodiment of the present invention relates to communication technical field, particularly relates to configuration and synchronization method and equipment between the multiple processor cores in a kind of system level chip.
Background technology
System level chip is (English: System on Chip, be called for short: SoC) comprise multiple processor core and synchronization module, this synchronization module can by bus and these multiple processor cores interconnected, and there are access rights, the plurality of processor core comprises: central processing unit is (English: CPU), digital signal processor is (English: Digital Signal Processor, be called for short: DSP), hardware accelerator is (English: HardwareAccelerator, be called for short: HAC) and direct memory access (English: Direct Memory Access, be called for short: DMA) etc., when needing to be configured synchronous when between these processor cores, the processor core of initiating change configuration is configured this synchronization module, thus the configuration synchronization that can complete between each processor core.Concrete configuration process is, the processor core of initiating change configuration sends multiple configuration-direct to this synchronization module successively, each configuration-direct comprises parameter to be configured, then this synchronization module carries out relevant configuration according to the plurality of configuration-direct successively, then configuration successful response is returned, to complete configuration synchronization process to the core of this master control successively.
But in prior art in a layoutprocedure, the processor core of initiating change configuration needs to send multiple configuration-direct to this synchronization module, takies larger bus bandwidth, causes bus bandwidth utilization factor low.
Summary of the invention
The embodiment of the present invention provides configuration and synchronization method and equipment between the multiple processor cores in a kind of system level chip, for reducing the bus bandwidth taken in configuration synchronization process, improves the utilization factor of bus bandwidth.
First aspect, the embodiment of the present invention provides configuration and synchronization method between the multiple processor cores in a kind of system level chip, and described system level chip comprises synchronization module and M processor core, described M be more than or equal to 2 integer;
Described method comprises:
First processor core sends configuration change message to described synchronization module, described first processor core is the arbitrary processor core in a described M processor core, described configuration change message to comprise in N number of configuration parameter to be configured and described N number of configuration parameter to be configured the address to be stored of first configuration parameter to be configured, described N be more than or equal to 2 integer, described N number of configuration parameter to be configured be described first processor core need be configured synchronous configuration parameter with the processor core in a described M processor core except described first processor core;
Described synchronization module receives the described configuration change message that described first processor core sends;
Described synchronization module, according to the address to be stored of described first configuration parameter, determines the register that in described N number of configuration parameter to be configured, each configuration parameter to be configured is to be stored;
Described synchronization module, by described N number of configuration parameter to be configured, is stored in the described N number of register determined, to complete the configuration synchronization between a described M processor core correspondingly.
In the first possible implementation of first aspect, described synchronization module receives the configuration change message that first processor core sends, and comprising:
Described synchronization module receives the first message that described first processor core sends, and described first message comprises the first data and the first address;
When described synchronization module determines that described first address belongs to preset address, determine that described first message is described configuration change message, described first data are described N number of configuration parameter to be configured, and described first address is the address to be stored of first configuration parameter to be configured in described N number of configuration parameter to be configured.
In conjunction with the first possible implementation of first aspect or first aspect, in the implementation that the second of first aspect is possible, described synchronization module also comprises after receiving the configuration change message that first processor core sends:
Described synchronization module receives service message, and described service message is that in a described M processor core, arbitrary processor core sends;
When described synchronization module determine described service message do not meet described synchronous after configuration time, described synchronization module abandons described service message.
In conjunction with first aspect or the first possible implementation of first aspect or the possible implementation of the second of first aspect, in the third possible implementation of first aspect, the number of the configuration parameter to be configured that described configuration change message comprises is 4.
In conjunction with the first of first aspect or first aspect to any one in the third possible implementation, in the 4th kind of possible implementation of first aspect, described configuration change message is 128 bit informations.
In conjunction with the first of first aspect or first aspect to any one in the 4th kind of possible implementation, in the 5th kind of possible implementation of first aspect, described method, also comprises:
Described first processor core sends configuration to described synchronization module and reads message, and the address that message comprises the storage of in N number of configuration parameter to be read first configuration parameter to be read is read in described configuration;
Described synchronization module receives the described configuration reading message that described first processor core sends;
Described synchronization module, according to the address of the storage of the configuration parameter to be read of first in described N number of configuration parameter to be read, determines the register storing described N number of configuration parameter to be read;
Described N number of configuration parameter to be read, from the register of the described N number of configuration parameter to be read of described storage, is sent to described first processor core by described synchronization module.
Second aspect, the embodiment of the present invention provides a kind of system level chip, comprising: M processor core, synchronization module and bus, described M be more than or equal to 2 integer, described synchronization module is connected by described bus communication with a described M processor core;
First processor core, for sending configuration change message by described bus to described synchronization module, described first processor core is the arbitrary processor core in a described M processor core, described configuration change message to comprise in N number of configuration parameter to be configured and described N number of configuration parameter to be configured the address to be stored of first configuration parameter to be configured, described N be more than or equal to 2 integer, described N number of configuration parameter to be configured is that described first processor core needs to be configured synchronous configuration parameter with the processor core in a described M processor core except described first processor core,
Described synchronization module, for receiving the described configuration change message that described first processor core sends by described bus; According to the address to be stored of described first configuration parameter to be configured, determine the register that in described N number of configuration parameter to be configured, each configuration parameter to be configured is to be stored; And by described N number of configuration parameter to be configured, be stored in the described N number of register determined correspondingly, to complete the configuration synchronization between a described M processor core.
In the first possible implementation of second aspect, described synchronization module is used for the configuration change message being received the transmission of first processor core by described bus, comprising:
Described synchronization module, for being received the first message that described processor core sends by described bus, described first message comprises the first data and the first address; Determine whether described first address belongs to preset address; And when determining that described first address belongs to preset address, determine that described first message is described configuration change message, described first data are described N number of configuration parameter to be configured, and described first address is the address to be stored of first configuration parameter to be configured in the to be configured configuration parameter of described M.
In conjunction with the first possible implementation of second aspect or second aspect, in the implementation that the second of second aspect is possible, described synchronization module also for, after the configuration change message being received the transmission of first processor core by described bus, receive service message by described bus, described service message is that in a described M processor core, arbitrary processor core sends; And determine described service message whether meet described synchronous after configuration; When determine described service message do not meet described synchronous after configuration time, abandon described service message.
In conjunction with second aspect or the first possible implementation of second aspect or the possible implementation of the second of second aspect, in the third possible implementation of second aspect, the number of the configuration parameter to be configured that described configuration change message comprises is 4.
In conjunction with the first of second aspect or second aspect to any one in the third possible implementation, in the 4th kind of possible implementation of second aspect, described configuration change message is 128 bit informations.
In conjunction with the first of second aspect or second aspect to any one in the 4th kind of possible implementation, in the 5th kind of possible implementation of second aspect, described first processor core, also read message for sending configuration by described bus to described synchronization module, the address that message comprises the storage of in N number of configuration parameter to be read first configuration parameter to be read is read in described configuration;
Described synchronization module, message is read in the described configuration also sent for being received first processor core by described bus; And the address of storage according to the configuration parameter to be read of first in described N number of configuration parameter to be read, determine the register storing described N number of configuration parameter to be read; From the register of the described N number of configuration parameter to be read of described storage, by described bus, described N number of configuration parameter to be read is sent to described first processor core.
The embodiment of the present invention provides configuration and synchronization method and equipment between the multiple processor cores in a kind of system level chip, sends configuration change message by first processor core to synchronization module; Synchronization module is according to the address to be stored of described first configuration parameter, determine the register that in this N number of configuration parameter to be configured, each configuration parameter to be configured is to be stored, and by this N number of configuration parameter to be configured, be stored to correspondingly in this N number of register determined, thus complete the configuration synchronization between this M processor core.Because first processor endorses that multiple configuration parameter is sent to synchronization module by same configuration change message, the transmitting procedure of multiple configuration parameter only occupies a bus bandwidth, compared with prior art, the bus bandwidth taken is less, improves the utilization factor of bus bandwidth.Configuration synchronization between processor core is undertaken by message, substantially increases software efficiency.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the process flow diagram of configuration and synchronization method embodiment one between the multiple processor cores in present system level chip;
Fig. 2 is the process flow diagram of configuration and synchronization method embodiment two between the multiple processor cores in present system level chip;
Fig. 3 is the process flow diagram of configuration and synchronization method embodiment three between the multiple processor cores in present system level chip;
Fig. 4 is the structural representation of present system level chip embodiment one.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Fig. 1 is the process flow diagram of configuration and synchronization method embodiment one between the multiple processor cores in present system level chip, as shown in Figure 1, the system level chip of the present embodiment comprises synchronization module and M processor core, this M be more than or equal to 2 integer, the method for the present embodiment can comprise:
S101, first processor core send configuration change message to synchronization module.
In the present embodiment, each processor core in this system level chip can initiate to be configured synchronizing process with other processor core, this any one processor core sentencing in this system level chip is example, this any one processor core is called first processor core, when this first processor core needs to be configured synchronous with other processor core (processor core in this M processor core namely in this system level chip except this first processor core) in this system level chip, this first processor core sends configuration change message to the synchronization module in this system level chip, this configuration change message comprises the address to be stored of first configuration parameter in N number of configuration parameter and this N number of configuration parameter, this N be more than or equal to 2 integer, this N number of configuration parameter is that this first processor core needs to be configured synchronous configuration parameter with the processor core in this M processor core in this system level chip except this first processor core respectively.If this first processor core needs synchronous 4 configurations, then the configuration parameter that these 4 configure is carried at configuration change message and sends to synchronization module by this first processor core.Alternatively, this configuration change message is sent to this synchronization module by the bus communicated between this first processor core with this synchronization module by this first processor core.
S102, this synchronization module receive this configuration change message that this first processor core sends.
S103, this synchronization module, according to the address to be stored of first configuration parameter to be configured, determine the register that in N number of configuration parameter to be configured, each configuration parameter to be configured is to be stored.
In the present embodiment, this synchronization module receives this configuration change message that this first processor core sends, then from this configuration change message, this N number of configuration parameter to be configured and an address is obtained, this address is the address to be stored of first configuration parameter to be configured in this N number of configuration parameter to be configured, then this synchronization module determines a register according to the address to be stored of this first configuration parameter to be configured, and the address of this register is the address to be stored of this first configuration parameter to be configured.Because this N number of configuration parameter to be configured needs to be stored in respectively in N number of adjacent register, therefore, this synchronization module can determine the register that the next register of the register that this first configuration parameter to be configured stores stores as second configuration parameter to be configured, determine the register that the next register of the register that this second configuration parameter to be configured stores stores as the 3rd configuration parameter to be configured, determine the register that the next register of the register that the 3rd configuration parameter to be configured stores stores as the 4th configuration parameter to be configured, by that analogy, determine the register that the next register of the register that the individual configuration parameter to be configured of this N-1 stores stores as N number of configuration parameter to be configured.
S104, this synchronization module, by this N number of configuration parameter to be configured, are stored in this N number of register determined, to complete the configuration synchronization between this M processor core correspondingly.
In the present embodiment, this synchronization module is after determining the register that in this N number of configuration parameter to be configured, each configuration parameter to be configured stores, this synchronization module is by this each configuration parameter to be configured, one is stored in this each configuration parameter to be configured register to be stored correspondingly, thus the configuration synchronization completed in this system level chip between M processor core, namely complete the synchronous of above-mentioned N number of configuration.
The present embodiment, sends configuration change message by first processor core to synchronization module; Synchronization module is according to the address to be stored of described first configuration parameter, determine the register that in this N number of configuration parameter to be configured, each configuration parameter to be configured is to be stored, and by this N number of configuration parameter to be configured, be stored to correspondingly in this N number of register determined, thus complete the configuration synchronization between this M processor core.Because first processor endorses that multiple configuration parameter is sent to synchronization module by same configuration change message, the transmitting procedure of multiple configuration parameter only occupies a bus bandwidth, compared with prior art, the bus bandwidth taken is less, improves the utilization factor of bus bandwidth.Configuration synchronization between processor core is undertaken by message, substantially increases software efficiency.
And in prior art, configuration synchronization process complete and look on the bright side of things open once configuration synchronization time, processor core needs first to close last configuration synchronization event, after repeatedly configuring, again open synchronous event, configuration synchronization next time could be opened.And in the present embodiment, be configured synchronously by configuration change message, processor core can send configuration change message to open configuration synchronization next time at any time, centre eliminates the operation of closing and opening synchronous event, greatly save access time and expense, improve business processing speed, accelerate the traffic rate between multitasking.
Alternatively, the configuration change message in the present embodiment is 128 bit informations, and in prior art, a configuration order is 32 bit informations, and therefore, this configuration change message can comprise 4 configuration parameters.
Fig. 2 is the process flow diagram of configuration and synchronization method embodiment two between the multiple processor cores in present system level chip, as shown in Figure 2, the system level chip of the present embodiment comprises synchronization module and M processor core, this M be more than or equal to 2 integer, the method for the present embodiment can comprise:
S201, synchronization module receive the first message that first processor core sends, and this first message comprises the first data and the first address.
S202, when this synchronization module determines that this first address belongs to preset address, determine that this first message is this configuration change message, these first data are N number of configuration parameter to be configured, and this first address is the address to be stored of first configuration parameter to be configured in described N number of configuration parameter to be configured.
In the present embodiment, due in the present embodiment for being configured synchronous configuration change message and service message all belongs to message, when synchronization module receives a message, need to judge that this message is that service class message still configures class message.Particularly, this synchronization module receives the first message that this first processor core sends, this first message comprises data field and address field, this data field comprises the first data, this address field comprises the first address, this synchronization module judges whether this first address belongs to preset address, this preset address comprises the address of each register for storage configuration parameter, when this first address belongs to this preset address, illustrate and need data to be stored in register corresponding to this first address, thus can determine that this first message is configuration change message, these first data are N number of configuration parameter to be configured, this first address is the address to be stored of first configuration parameter to be configured in this N number of configuration parameter to be configured.When this synchronization module determines that this first address does not belong to this preset address, can determine that this first message is service message, the operation that synchronization module performs according to service message, similarly to the prior art, repeats no more herein.
S203, this synchronization module, according to the address to be stored of this first configuration parameter, determine the register that in this N number of configuration parameter to be configured, each configuration parameter to be configured is to be stored.
S204, this synchronization module, by this N number of configuration parameter to be configured, are stored in this N number of register determined, to complete the configuration synchronization between this M processor core correspondingly.
In the present embodiment, the specific implementation process of S203 and S204 see the relevant record of S103 and S104 in the inventive method embodiment one, can repeat no more herein.
The present embodiment, the first message of first processor core transmission is received by synchronization module, this first message comprises the first data and the first address, when determining that this first address belongs to preset address, determine that this first message is this configuration change message, these first data are N number of configuration parameter to be configured, and this first address is the address to be stored of first configuration parameter to be configured in described N number of configuration parameter to be configured; According to the address to be stored of this first configuration parameter, determine the register that in this N number of configuration parameter to be configured, each configuration parameter to be configured is to be stored; By this N number of configuration parameter to be configured, be stored in this N number of register determined correspondingly, to complete the configuration synchronization between this M processor core.Because first processor endorses that multiple configuration parameter is sent to synchronization module by same configuration change message, the transmitting procedure of multiple configuration parameter only occupies a bus bandwidth, compared with prior art, the bus bandwidth taken is less, improves the utilization factor of bus bandwidth.Configuration synchronization between processor core is undertaken by message, substantially increases software efficiency.
Alternatively, state on the basis of each embodiment of the method on the invention, this synchronization module also comprises after receiving the configuration change message of first processor core transmission: this synchronization module receives service message, and this service message is that in this M processor core, arbitrary processor core sends; When this synchronization module determine this service message do not meet this synchronous after configuration time, this synchronization module abandons this service message.In the present embodiment, after this synchronization module receives the configuration change message of this first processor core transmission, the service message that this first processor core sends can also be received, or receive the service message of other processor core transmission in this M processor core except this first processor core.This synchronization module need to determine whether this service message meet corresponding to this configuration change message synchronous after configuration, when this service message do not meet this synchronous after configuration, then this synchronization module abandons this service message; When this service message symbol this synchronous after configuration, this synchronization module carries out relevant treatment according to this service message, repeats no more herein similarly to the prior art.Wherein, judge this service message whether meet this synchronous after configuration a kind of feasible implementation in, this business module can obtain a part of data in this service message, such as 32 bit informations, judge that whether this 32 bit information is the presupposed information in this synchronous configuration, the configuration if so, then after this service message sign synchronization, if not, then this service message not symbol this synchronous after configuration.
Fig. 3 is the process flow diagram of configuration and synchronization method embodiment three between the multiple processor cores in present system level chip, as shown in Figure 3, the system level chip of the present embodiment comprises synchronization module and M processor core, this M be more than or equal to 2 integer, the method for the present embodiment can comprise:
S301, first processor core send configuration to synchronization module and read message.
In the present embodiment, each processor core in this system level chip can initiate to be configured synchronizing process with other processor core, this any one processor core sentencing in this system level chip is example, this any one processor core is called first processor core, when this first processor core needs to be configured synchronous with other processor core (processor core in this M processor core namely in this system level chip except this first processor core) in this system level chip, this sentences once needs to carry out N number of configuration synchronization to be example, N be more than or equal to 2 integer, this first processor endorses to obtain the configuration parameter of this N number of configuration current in system level chip.Particularly, this first processor core sends configuration to synchronization module and reads message, and the address that message comprises the storage of in N number of configuration parameter to be read first configuration parameter to be read is read in this configuration.
S302, this synchronization module receive this configuration reading message that this first processor core sends.
S303, this synchronization module, according to the address of the storage of the configuration parameter to be read of first in this N number of configuration parameter to be read, determine the register storing this N number of configuration parameter to be read.
In the present embodiment, this synchronization module receives this configuration reading message that this first processor core sends, then the address message is read from this configuration, this address is the address of the storage of first configuration parameter to be read in this N number of configuration parameter to be read, then this synchronization module determines a register according to the address of the storage of this first configuration parameter to be read, and the address of this register is the address of the storage of this first configuration parameter to be read.Because this N number of configuration parameter to be read needs to be stored in respectively in N number of adjacent register, therefore, this synchronization module can determine the register that the next register of the register that this first configuration parameter to be read stores stores as second configuration parameter to be read, determine the register that the next register of the register that this second configuration parameter to be read stores stores as the 3rd configuration parameter to be read, determine the register that the next register of the register that the 3rd configuration parameter to be read stores stores as the 4th configuration parameter to be read, by that analogy, determine the register that the next register of the register that the individual configuration parameter to be read of this N-1 stores stores as N number of configuration parameter to be read.
This N number of configuration parameter to be read, from the register of this N number of configuration parameter to be read of this storage, is sent to this first processor core by S304, this synchronization module.
In the present embodiment, this synchronization module can obtain the configuration parameter to be read stored in this N number of register from above-mentioned N number of register, then this N number of configuration parameter to be read is sent to this first processor core.Then, this first processor endorses to send configuration change message according to this N number of configuration parameter to be read to this synchronization module, how this first processor core determine the current process needing to send to the configuration parameter of synchronization module similarly to the prior art according to the configuration parameter stored in register, repeats no more herein.This first processor core follow-up and this synchronization module can perform the technical scheme of said method embodiment one or two of the present invention.
Alternatively, message is read in this configuration also can be 128 bit informations.Message is read in this configuration and above-mentioned configuration change message is configuration messages, wherein, when configuration messages comprises indication information, when this indication information indicates this configuration messages for changing configuration, this configuration messages is configuration change message, when this indication information indicates this configuration messages for reading configuration, this configuration messages is configuration reading message.
The present embodiment, sends configuration by first processor core to synchronization module and reads message; This synchronization module receives this configuration reading message that this first processor core sends; This synchronization module, according to the address of the storage of the configuration parameter to be read of first in this N number of configuration parameter to be read, determines the register storing this N number of configuration parameter to be read; From the register of this N number of configuration parameter to be read of this storage, this N number of configuration parameter to be read is sent to this first processor core.Endorse due to first processor and to read configuration parameter in multiple register to synchronization module to be read message by same configuration, the transmitting procedure of multiple configuration parameter only occupies a bus bandwidth, compared with prior art, the bus bandwidth taken is less, improves the utilization factor of bus bandwidth.
Fig. 4 is the structural representation of present system level chip embodiment one, as shown in Figure 4, the system level chip of the present embodiment can comprise: synchronization module 11, bus 12 and M processor core, a processor core in M processor core is only shown herein, this processor core is called first processor core 13, other processor core and the first processor core 13 of this M processor core are similar, this M be more than or equal to 2 integer, synchronization module 11 and first processor core are communicated to connect by bus 12; Alternatively, this system level chip can comprise storer (not shown), this storer is for storing configuration and synchronization method between the multiple processor cores in executive system level chip, and this storer is communicated to connect by bus 12 and synchronization module 11, first processor core 13.
Wherein, first processor core 13, for sending configuration change message by bus 12 to synchronization module 11, first processor core 13 is the arbitrary processor core in a described M processor core, described configuration change message to comprise in N number of configuration parameter to be configured and described N number of configuration parameter to be configured the address to be stored of first configuration parameter to be configured, described N be more than or equal to 2 integer, described N number of configuration parameter to be configured is that first processor core 13 needs to be configured synchronous configuration parameter with the processor core in M processor core except described first processor core,
Synchronization module 11, for receiving the described configuration change message that first processor core 13 sends by bus 12; According to the address to be stored of described first configuration parameter to be configured, determine the register that in described N number of configuration parameter to be configured, each configuration parameter to be configured is to be stored; And by described N number of configuration parameter to be configured, be stored in the described N number of register determined correspondingly, with the configuration synchronization between at least two processor cores described in completing.
Alternatively, the configuration change message that synchronization module 11 is sent for being received first processor core by bus 12, comprise: synchronization module 11, for being received the first message that described processor core sends by bus 12, described first message comprises the first data and the first address; Determine whether described first address belongs to preset address; And when determining that described first address belongs to preset address, determine that described first message is described configuration change message, described first data are described N number of configuration parameter to be configured, and described first address is the address to be stored of first configuration parameter to be configured in the to be configured configuration parameter of described M.
Alternatively, synchronization module 11 also for, after received the configuration change message that first processor core 13 sends by bus 12, receive service message by bus 12, described service message is arbitrary processor core transmission in a described M processor core; And determine described service message whether meet described synchronous after configuration; When determine described service message do not meet described synchronous after configuration time, abandon described service message.
Alternatively, the number of configuration parameter to be configured that described configuration change message comprises is 4.
Alternatively, described configuration change message is 128 bit informations.
Alternatively, first processor core 13, also reads message for sending configuration by bus 12 to synchronization module 11, and the address that message comprises the storage of in N number of configuration parameter to be read first configuration parameter to be read is read in described configuration;
Synchronization module 11, message is read in the described configuration also sent for being received first processor core by bus 12; And the address of storage according to the configuration parameter to be read of first in described N number of configuration parameter to be read, determine the register storing described N number of configuration parameter to be read; From the register of the described N number of configuration parameter to be read of described storage, by bus 12, described N number of configuration parameter to be read is sent to described first processor core.
The system level chip of the present embodiment, may be used for the technical scheme performing the above-mentioned each embodiment of the method for the present invention, it realizes principle and technique effect is similar, repeats no more herein.
Alternatively, the above-mentioned processor core mentioned can be CPU, DSP, HAC and DMA etc., and synchronization module can be the message managing module in system level chip.
One of ordinary skill in the art will appreciate that: all or part of step realizing above-mentioned each embodiment of the method can have been come by the hardware that programmed instruction is relevant.Aforesaid program can be stored in a computer read/write memory medium.This program, when performing, performs the step comprising above-mentioned each embodiment of the method; And aforesaid storage medium comprises: read-only memory is (English: Read-Only Memory, be called for short: ROM), random access memory (English: Random Access Memory, be called for short: RAM), magnetic disc or CD etc. various can be program code stored medium.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (12)
1. a configuration and synchronization method between the multiple processor cores in system level chip, is characterized in that, described system level chip comprises synchronization module and M processor core, described M be more than or equal to 2 integer;
Described method comprises:
First processor core sends configuration change message to described synchronization module, described first processor core is the arbitrary processor core in a described M processor core, described configuration change message to comprise in N number of configuration parameter to be configured and described N number of configuration parameter to be configured the address to be stored of first configuration parameter to be configured, described N be more than or equal to 2 integer, described N number of configuration parameter to be configured be described first processor core need be configured synchronous configuration parameter with the processor core in a described M processor core except described first processor core;
Described synchronization module receives the described configuration change message that described first processor core sends;
Described synchronization module, according to the address to be stored of described first configuration parameter, determines the register that in described N number of configuration parameter to be configured, each configuration parameter to be configured is to be stored;
Described synchronization module, by described N number of configuration parameter to be configured, is stored in the described N number of register determined, to complete the configuration synchronization between a described M processor core correspondingly.
2. method according to claim 1, is characterized in that, described synchronization module receives the configuration change message that first processor core sends, and comprising:
Described synchronization module receives the first message that described first processor core sends, and described first message comprises the first data and the first address;
When described synchronization module determines that described first address belongs to preset address, determine that described first message is described configuration change message, described first data are described N number of configuration parameter to be configured, and described first address is the address to be stored of first configuration parameter to be configured in described N number of configuration parameter to be configured.
3. method according to claim 1 and 2, is characterized in that, described synchronization module also comprises after receiving the configuration change message of first processor core transmission:
Described synchronization module receives service message, and described service message is that in a described M processor core, arbitrary processor core sends;
When described synchronization module determine described service message do not meet described synchronous after configuration time, described synchronization module abandons described service message.
4. the method according to claim 1-3 any one, is characterized in that, the number of the configuration parameter to be configured that described configuration change message comprises is 4.
5. the method according to claim 1-4 any one, is characterized in that, described configuration change message is 128 bit informations.
6. the method according to claim 1-5 any one, is characterized in that, described method, also comprises:
Described first processor core sends configuration to described synchronization module and reads message, and the address that message comprises the storage of in N number of configuration parameter to be read first configuration parameter to be read is read in described configuration;
Described synchronization module receives the described configuration reading message that described first processor core sends;
Described synchronization module, according to the address of the storage of the configuration parameter to be read of first in described N number of configuration parameter to be read, determines the register storing described N number of configuration parameter to be read;
Described N number of configuration parameter to be read, from the register of the described N number of configuration parameter to be read of described storage, is sent to described first processor core by described synchronization module.
7. a system level chip, is characterized in that, comprising: M processor core, synchronization module and bus, described M be more than or equal to 2 integer, described synchronization module is connected by described bus communication with a described M processor core;
First processor core, for sending configuration change message by described bus to described synchronization module, described first processor core is the arbitrary processor core in a described M processor core, described configuration change message to comprise in N number of configuration parameter to be configured and described N number of configuration parameter to be configured the address to be stored of first configuration parameter to be configured, described N be more than or equal to 2 integer, described N number of configuration parameter to be configured is that described first processor core needs to be configured synchronous configuration parameter with the processor core in a described M processor core except described first processor core,
Described synchronization module, for receiving the described configuration change message that described first processor core sends by described bus; According to the address to be stored of described first configuration parameter to be configured, determine the register that in described N number of configuration parameter to be configured, each configuration parameter to be configured is to be stored; And by described N number of configuration parameter to be configured, be stored in the described N number of register determined correspondingly, to complete the configuration synchronization between a described M processor core.
8. system level chip according to claim 7, is characterized in that, described synchronization module is used for the configuration change message being received the transmission of first processor core by described bus, comprising:
Described synchronization module, for being received the first message that described processor core sends by described bus, described first message comprises the first data and the first address; Determine whether described first address belongs to preset address; And when determining that described first address belongs to preset address, determine that described first message is described configuration change message, described first data are described N number of configuration parameter to be configured, and described first address is the address to be stored of first configuration parameter to be configured in the to be configured configuration parameter of described M.
9. the system level chip according to claim 7 or 8, it is characterized in that, described synchronization module also for, after the configuration change message being received the transmission of first processor core by described bus, receive service message by described bus, described service message is that in a described M processor core, arbitrary processor core sends; And determine described service message whether meet described synchronous after configuration; When determine described service message do not meet described synchronous after configuration time, abandon described service message.
10. the system level chip according to claim 7-9 any one, is characterized in that, the number of the configuration parameter to be configured that described configuration change message comprises is 4.
11. system level chips according to claim 7-10 any one, it is characterized in that, described configuration change message is 128 bit informations.
12. system level chips according to claim 7-11 any one, it is characterized in that, described first processor core, also read message for sending configuration by described bus to described synchronization module, the address that message comprises the storage of in N number of configuration parameter to be read first configuration parameter to be read is read in described configuration;
Described synchronization module, message is read in the described configuration also sent for being received described first processor core by described bus; And the address of storage according to the configuration parameter to be read of first in described N number of configuration parameter to be read, determine the register storing described N number of configuration parameter to be read; From the register of the described N number of configuration parameter to be read of described storage, by described bus, described N number of configuration parameter to be read is sent to described first processor core.
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