CN101114622A - Flip-chip type semiconductor packaging structure and chip bearing member - Google Patents
Flip-chip type semiconductor packaging structure and chip bearing member Download PDFInfo
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- CN101114622A CN101114622A CNA2006101078776A CN200610107877A CN101114622A CN 101114622 A CN101114622 A CN 101114622A CN A2006101078776 A CNA2006101078776 A CN A2006101078776A CN 200610107877 A CN200610107877 A CN 200610107877A CN 101114622 A CN101114622 A CN 101114622A
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- chip
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- type semiconductor
- bearing member
- packaging structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- Wire Bonding (AREA)
Abstract
A flip-chip typed semiconductor packaging structure with the related chip carrier is essentially characterized in that an edge of chip linking area of the chip carrier is provided with a groove which can be placed around the edges of the chip linking area or in the corner of the chip linking area, thus soft filler with low young modulus can fill the groove in order to be in connection with the flip-chip typed semiconductor chip in the chip linking area, and the filler with low young modulus absorbs thermal stress in order to avoid delamination between the filling glue at bottom of the chip and the chip.
Description
Technical field
The present invention relates to a kind of semiconductor package and chip bearing member thereof, relate in particular to a kind of flip-chip type semiconductor packaging structure and chip bearing member thereof.
Background technology
Chip upside-down mounting type (Flip-Chip) semiconductor package part is a kind of encapsulating structure that utilizes flip chip to electrically connect, it is electrically connected to the action face (Active Surface) of at least one chip on the surface of substrate (Substrate) by a plurality of conductive projections (Solder Bumps), this design not only can significantly reduce the packaging part volume, so that the ratio of semiconductor chip and substrate more becomes is approaching, simultaneously, also deduct existing bonding wire (Wire) design, promote electrically and can reduce impedance, therefore become the main flow encapsulation technology of chip of future generation and electronic component.
Consult Figure 1A and 1B, plane and generalized section for existing flip-chip type semiconductor packaging part, its with flip-chip type semiconductor chip 10 by a plurality of conductive projections 13 connect put and be electrically connected to this substrate 11 after, fill flip-chip bottom filler material (underfill) 12 in 11 of flip-chip type semiconductor chip 10 and substrates, intensity in order to coated with conductive projection 13 and increase conductive projection 13 can support this flip-chip type semiconductor chip 10 weight simultaneously.For example United States Patent (USP) the 6th, 225, and the 704,6,074,895,6,372, the 544 and the 5th, 218, No. 234 cases have all disclosed the technology of this Flip-Chip Using and flip-chip bottom filler.
Yet; relation because of flip-chip bottom filler material 12 surface tension effects; after this flip-chip bottom filler material 12 is filled; in the protection of adhering to that presents minimum corresponding to 10 jiaos of ends of flip-chip type semiconductor chip; simultaneously; because material thermal expansion coefficient (CTE) difference that this flip-chip type semiconductor chip 10 and substrate are 11; thermal stress that produces in the thermal cycle process of Chip Packaging and heat distortion amount and chip middle position distance is proportional, δ (deflection)=α (material thermal expansion coefficient) * L (with the material deformation amount be 0 distance) * △ t (temperature variation).That is the edge angle end of this flip-chip type semiconductor chip 10; because the distance that itself and chip center locate farthest; so suffered thermal stress and heat distortion amount maximum; this moment if flip-chip bottom filler material 12 can't provide the protection of capacity; promptly can cause the flip-chip bottom filler material 12 that is filled in periphery delamination (shown in the S of Figure 1B) to occur; have a strong impact on the effect of flip-chip bottom filler, more severe patient will cause the diffusion of delamination, and then influence the electrical of conductive projection 13.
Especially bad, because recently semiconductor chip is below live width 90 nanometers (nm) even during the Manufacturing Technology Development of 65 nanometers, 45 nanometers, 32 nanometers, dwindle the resistance time delay (RC Time Delay) that is caused in order to overcome live width, must import the dielectric layer material of low-k (Low k), can closely press close to mutually to allow the plain conductor in the chip, and prevent the problem of signal leakage and interference, and improve transmission rate relatively.Along with the low-k requirement of these dielectric layer material, the related dielectric layer material matter of deriving is hard, easy crisp characteristic, easily causes the delamination of dielectric layer all the better, influences the electrical quality of product.Lay the blame on its reason, mainly be still because the thermal stress that can't effectively solve, absorb in the manufacture process to be produced, thereby cause the delamination problems of chip internal layer.
In addition, consult Fig. 2, United States Patent (USP) the 6th, 734,567 are disclosed a kind of flip-chip type semiconductor packaging part, it is to set up a becket 24 to extend to substrate 21 inside on substrate 21 surfaces to prevent the filler delamination of flip-chip bottom, but this mode still can't prevent between flip-chip bottom filler and flip-chip type semiconductor chip 20 interfaces, reach the delamination problems of these flip-chip type semiconductor chip 20 internal layers.
In view of aforementioned disappearance, for reducing because of the different thermal stress issues that produced of thermal coefficient of expansion (CTE), industry satisfy to use the flip-chip bottom filler material of low Young's modulus (Young ' s modulus) to absorb thermal stress, but the flip-chip of low Young's modulus bottom filler material and the enough support strengths of conductive projection of flip-chip type semiconductor chip can't be provided; But relatively, carry out flip-chip bottom filler,, easily cause the flip-chip type semiconductor chip to be heated stress and delamination problems takes place though higher conductive projection support strength can be provided as adopting flip-chip bottom filler material than high Young's modulus; Therefore the corresponding chip that varies in size is with on substrate engages, and dissimilar chips is when engaging with substrate, promptly need spend a large amount of time, energy and test and remove to seek filler material bottom the optimum flip-chip, causes the raising of manufacturing time and expense.
Therefore; how effectively to avoid between flip-chip bottom filler and semiconductor chip or substrate, also or chip internal layer generation delamination problems; simultaneously also can provide the conductive projection of flip-chip type semiconductor chip effectively to protect, really be the urgent problem to be solved of relevant research and development field institute.
Summary of the invention
Because above-mentioned existing shortcoming, main purpose of the present invention provides a kind of flip-chip type semiconductor packaging structure and chip bearing member thereof, to prevent between flip-chip bottom filler and semiconductor chip or substrate, also or chip internal layer generation delamination problems.
Still a further object of the present invention provides a kind of flip-chip type semiconductor packaging structure and chip bearing member thereof, thereby can improve the conductive projection that supports with protection flip-chip type semiconductor chip.
Another object of the present invention provides a kind of flip-chip type semiconductor packaging structure and chip bearing member thereof, can avoid spending a large amount of time and cost and seek flip-chip bottom filler material to overcome between semiconductor chip and substrate the delamination problems because of thermal expansion coefficient difference was caused.
For reaching aforementioned and other purposes, the present invention discloses a kind of flip-chip type semiconductor packaging structure, comprise: chip bearing member, this chip bearing member is provided with at least one confession and connects the chip connecting area of putting semiconductor chip, and is formed with on this chip bearing member groove (groove) that should chip connecting area outer rim; The flip-chip type semiconductor chip connects the chip connecting area of putting and be electrically connected to this chip bearing member by a plurality of conductive projections; The inserts of low Young's modulus is filled in this groove; And flip-chip bottom filler material, be filled in the gap between this flip-chip type semiconductor chip and this chip bearing member.
The present invention also discloses a kind of chip bearing member that is used for flip-chip type semiconductor packaging structure, comprising: body; Default in the chip connecting area of this body surface, put the flip-chip type semiconductor chip for connecing; And groove, be located at this chip connecting area outer rim, for the inserts of filling low Young's modulus.
This chip bearing member can for example be a substrate, this groove is to be located at the groove that this substrate surface is refused layer, and this groove can be located on the outer rim all around of this chip connecting area or be located at four corners of this chip connecting area, connect the edge that places the flip-chip type semiconductor chip on this chip connecting area to correspond to, thereby by in this groove, filling the inserts of low Young's modulus (glass transition temperature (Tg) less than (25 ℃) Young's modulus value under 80 ℃ or the room temperature less than 2000Mpa), with the absorption thermal stress, and then avoid flip-chip type semiconductor die corner end delamination problems.
Therefore; flip-chip type semiconductor packaging structure of the present invention and chip bearing member thereof; it mainly is chip connecting area outer rim formation groove at chip bearing member; this groove can be located on this chip connecting area or be located at this chip connecting area corner; thereby in this groove, fill the soft inserts of low Young's modulus; for the edge position, angle that connects the flip-chip type semiconductor chip that places on this chip connecting area corresponding to this soft inserts top; thereby protect the angle edge of this flip-chip type semiconductor chip by the inserts of this low Young's modulus; and can absorb thermal stress; simultaneously; in between this flip-chip type semiconductor chip and chip bearing member, be filled with flip-chip bottom filler material in addition; and fill and be distributed between conductive projection; effectively protect conductive projection and carry this flip-chip type semiconductor chip; use preventing between flip-chip bottom filler and semiconductor chip or chip bearing member and chip internal layer generation delamination problems, and then avoid prior art cost plenty of time and cost to seek that the filler material causes not being inconsistent economical efficiency bottom the suitable flip-chip.
Description of drawings
Figure 1A is the floor map of existing flip-chip type semiconductor packaging part; And
Figure 1B is the 1B-1B generalized section of Figure 1A;
Fig. 2 is a United States Patent (USP) the 6th, 734, the flip-chip type semiconductor packaging part generalized section that is disclosed for No. 567;
Fig. 3 A and 3B are chip bearing member plane and the generalized section that is used for flip-chip type semiconductor packaging structure of the present invention;
Fig. 4 is the generalized section of flip-chip type semiconductor packaging structure of the present invention; And
Fig. 5 is the floor map that is used for another embodiment of chip bearing member of flip-chip type semiconductor packaging structure of the present invention.
The main element symbol description
10 flip-chip type semiconductor chips
11 substrates
12 flip-chips bottom filler material
13 conductive projections
20 flip-chip type semiconductor chips
21 substrates
24 beckets
30 flip-chip type semiconductor chips
31 substrates
311 chip connecting areas
312 grooves
313 sandwich layers
314 weld pads
315 refuse layer
32 flip-chips bottom filler material
33 conductive projections
The inserts of 35 low Young's moduluss
41 substrates
411 chip connecting areas
412 grooves
415 refuse layer
The S delamination
Embodiment
Below further specify characteristics of the present invention and function by the particular specific embodiment conjunction with figs..
Consult Fig. 3 A and 3B, be the chip bearing member schematic diagram that is used for flip-chip type semiconductor packaging structure of the present invention, wherein this Fig. 3 B generalized section that is corresponding diagram 3A.
This chip bearing member is a substrate 31, and this substrate 31 includes a body; Default in the chip connecting area 311 of this body surface, put the flip-chip type semiconductor chip for connecing; And groove 312, be located at this chip connecting area 311 outer rims, for the inserts of filling low Young's modulus.
The layer 315 of refusing that this substrate body can be for example covered this sandwich layer 313 and exposed outside those weld pads 314 by a sandwich layer 313, a plurality of weld pad 314 and of being located at this core layer surface is formed.This weld pad 314 is located in this chip connecting area 311, is able to be electrically connected to this weld pad 314 by a plurality of conductive projections for follow-up flip-chip type semiconductor chip; This is refused layer 315 and is covered on this substrate sandwich layer 313, and is formed with the groove 312 of ring-type corresponding to the periphery of this chip connecting area 311.
Other consults Fig. 4, and for showing the generalized section of flip-chip type semiconductor packaging structure of the present invention, it mainly is the formed encapsulating structure of package fabrication process that carries out the flip-chip type semiconductor chip with the substrate as Fig. 3 A and 3B.
As shown in the figure, this flip-chip type semiconductor packaging structure comprises: just like the chip bearing member of substrate 31, this substrate 31 is provided with at least one confession and connects the chip connecting area of putting semiconductor chip, and is formed with on this chip bearing member groove 312 that should chip connecting area outer rim; Flip-chip type semiconductor chip 30 connects the weld pad 314 of putting and be electrically connected to this substrate chip connecting area by a plurality of conductive projections 33; The inserts 35 of low Young's modulus is filled in this groove 312; And flip-chip bottom filler material 32, be filled in the gap of 31 of this flip-chip type semiconductor chip 30 and this substrates.
This flip-chip type semiconductor chip 30 can carry out the flip-chip manufacture process by a plurality of conductive projections 33, connect on the weld pad 314 of putting and be electrically connected at this chip connecting area with action face this flip-chip type semiconductor chip 30, and in this groove 312, fill low Young's modulus (as glass transition temperature (Tg) less than 80 ℃, or under the room temperature (25 ℃) Young's modulus value less than 2000Mpa) inserts 35, it for example is the flip-chip bottom filler material of silica gel (silicone), make the edge of these inserts 35 positions corresponding to this flip-chip type semiconductor chip 30, use the absorption thermal stress, and then avoid flip-chip type semiconductor die corner end delamination problems; Simultaneously owing to can be filled with filler material 32 bottom the general flip-chip in the gap of 31 of this flip-chip type semiconductor chip 30 and substrates (as its glass transition temperature (Tg) greater than 80 ℃; or under the room temperature (25 ℃) Young's modulus value greater than 2000Mpa); to coat these a plurality of conductive projections 33, use effective protection conductive projection 33 and carry this flip-chip type semiconductor chip 30.
Other consults Fig. 5, is the top view that is applied to chip bearing member second embodiment of flip-chip type semiconductor packaging structure of the present invention.
As shown in the figure, the chip bearing member and the previous embodiment of present embodiment are roughly the same, it is corners corresponding to chip connecting area 411 that main difference is to be formed at chip bearing member groove 412 as substrate 41, that is, refuse in this substrate 41 that the corner corresponding to the chip connecting area is formed with groove 412 in the layer 415, thereby for follow-up inserts of filling low Young's modulus in this groove 412, and then make and connect the inserts top that the semiconductor chip angle end correspondence that places on this chip connecting area is positioned at this low Young's modulus, and give the absorption thermal stress, avoid semiconductor chip angle end delamination problems.
Therefore; flip-chip type semiconductor packaging structure of the present invention and chip bearing member thereof; it mainly is chip connecting area outer rim formation groove at chip bearing member; this groove can be located on this chip connecting area or be located at this chip connecting area corner; thereby in this groove, fill the soft inserts of low Young's modulus; for the edge position, angle that connects the flip-chip type semiconductor chip that places on this chip connecting area corresponding to this soft inserts top; thereby protect the angle edge of this flip-chip type semiconductor chip by the inserts of this low Young's modulus; and can absorb thermal stress; simultaneously; in between this flip-chip type semiconductor chip and chip bearing member, be filled with flip-chip bottom filler material in addition; and fill and be distributed in conductive projection and ask; effectively protect conductive projection and carry this flip-chip type semiconductor chip; use preventing between flip-chip bottom filler and semiconductor chip or chip bearing member and chip internal layer generation delamination problems, and then avoid prior art cost plenty of time and cost to seek that the filler material causes not being inconsistent economical efficiency bottom the suitable flip-chip.
The above only is a preferred implementation of the present invention, be not in order to limit scope of the present invention, that is, the present invention in fact still can make other changes, therefore, as long as those skilled in the art still should be the claim of enclosing and contain not breaking away from all equivalence modifications of being finished under disclosed spirit and the technological thought or changing.
Claims (21)
1. flip-chip type semiconductor packaging structure comprises:
Chip bearing member, this chip bearing member is provided with at least one confession and connects the connecting area of putting the flip-chip type semiconductor chip, and is formed with on this chip bearing member groove that should chip connecting area outer rim;
The flip-chip type semiconductor chip connects on the chip connecting area of putting and be electrically connected at chip bearing member by a plurality of conductive projections;
The inserts of low Young's modulus is filled in this groove; And
Flip-chip bottom filler material fills the gap that is distributed between this flip-chip type semiconductor chip and this chip bearing member.
2. flip-chip type semiconductor packaging structure according to claim 1, wherein, this chip bearing member is a substrate, this substrate includes the groove that a body, defaults in the chip connecting area of this body surface and is located at this chip connecting area outer rim.
3. flip-chip type semiconductor packaging structure according to claim 2, wherein, the layer of refusing that this substrate body covers this sandwich layer by a sandwich layer, a plurality of weld pad of being located at this core layer surface and one and exposes outside these weld pads is formed.
4. flip-chip type semiconductor packaging structure according to claim 3, wherein, this weld pad is located in this chip connecting area, is able to be electrically connected to this weld pad by a plurality of conductive projections for the flip-chip type semiconductor chip.
5. flip-chip type semiconductor packaging structure according to claim 1, wherein, this groove is located at the periphery of this chip connecting area in the form of a ring with correspondence.
6. flip-chip type semiconductor packaging structure according to claim 1, wherein, this groove is located at the corner of this chip connecting area.
7. flip-chip type semiconductor packaging structure according to claim 1, wherein, the glass transition temperature Tg of this inserts is less than 80 ℃.
8. flip-chip type semiconductor packaging structure according to claim 1, wherein, the Young's modulus value of this inserts under room temperature is less than 2000Mpa.
9. flip-chip type semiconductor packaging structure according to claim 1, wherein, the glass transition temperature Tg of this flip-chip bottom filler material is greater than 80 ℃.
10. flip-chip type semiconductor packaging structure according to claim 1, wherein, the Young's modulus value of this flip-chip bottom filler material under room temperature is greater than 2000Mpa.
11. flip-chip type semiconductor packaging structure according to claim 1, wherein, the inserts of this low Young's modulus is a silica gel.
12. flip-chip type semiconductor packaging structure according to claim 1, wherein, this inserts position is corresponding to the edge of this flip-chip type semiconductor chip.
13. a chip bearing member comprises:
Body;
Default in the chip connecting area of this body surface, put the flip-chip type semiconductor chip for connecing; And
Groove is located at this chip connecting area outer rim, for the inserts of filling low Young's modulus.
14. chip bearing member according to claim 13, wherein, this chip bearing member is a substrate, and the layer of refusing that its body covers this sandwich layer by a sandwich layer, a plurality of weld pad of being located at this core layer surface and one and exposes outside these weld pads is formed.
15. chip bearing member according to claim 14, wherein, this weld pad is located in this chip connecting area, is able to be electrically connected to this weld pad by a plurality of conductive projections for the flip-chip type semiconductor chip.
16. chip bearing member according to claim 13, wherein, this groove is located at the periphery of this chip connecting area in the form of a ring with correspondence.
17. chip bearing member according to claim 13, wherein, this groove is located at the corner of this chip connecting area.
18. chip bearing member according to claim 13, wherein, the glass transition temperature Tg of this inserts is less than 80 ℃.
19. chip bearing member according to claim 13, wherein, the Young's modulus value of this inserts under room temperature is less than 2000Mpa.
20. chip bearing member according to claim 13, wherein, the inserts of this low Young's modulus is a silica gel.
21. chip bearing member according to claim 13, wherein, this inserts position is corresponding to the edge of flip-chip type semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101078776A CN101114622A (en) | 2006-07-27 | 2006-07-27 | Flip-chip type semiconductor packaging structure and chip bearing member |
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2006101078776A CN101114622A (en) | 2006-07-27 | 2006-07-27 | Flip-chip type semiconductor packaging structure and chip bearing member |
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| CN101114622A true CN101114622A (en) | 2008-01-30 |
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| CNA2006101078776A Pending CN101114622A (en) | 2006-07-27 | 2006-07-27 | Flip-chip type semiconductor packaging structure and chip bearing member |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102377919A (en) * | 2010-08-17 | 2012-03-14 | 深圳富泰宏精密工业有限公司 | Camera module and portable electronic device utilizing same |
| CN103325694A (en) * | 2012-03-21 | 2013-09-25 | 致伸科技股份有限公司 | Dispensing method used for flip chip manufacturing process |
| CN104465598A (en) * | 2014-12-19 | 2015-03-25 | 江苏长电科技股份有限公司 | Metal lead frame high thermal conductivity flip chip packaging structure and technological method thereof |
| CN107785332A (en) * | 2016-08-24 | 2018-03-09 | 南亚科技股份有限公司 | Semiconductor structure |
| CN108962764A (en) * | 2017-05-22 | 2018-12-07 | 中芯国际集成电路制造(上海)有限公司 | Forming method, semiconductor chip, packaging method and the structure of semiconductor structure |
| CN109558671A (en) * | 2018-11-27 | 2019-04-02 | 中南大学 | A kind of method of edge effect during simulation Flip Chip Underfill Technology |
| CN113517240A (en) * | 2021-05-21 | 2021-10-19 | 华天科技（昆山）电子有限公司 | Wafer fan-out type inverted packaging structure and manufacturing method thereof |
| CN115020396A (en) * | 2022-05-25 | 2022-09-06 | 杭州道铭微电子有限公司 | Chip packaging structure and packaging method |
| CN117558686A (en) * | 2023-09-28 | 2024-02-13 | 锐石创芯(重庆)科技有限公司 | Chip packaging structure and radio frequency front end module |
-
2006
- 2006-07-27 CN CNA2006101078776A patent/CN101114622A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102377919A (en) * | 2010-08-17 | 2012-03-14 | 深圳富泰宏精密工业有限公司 | Camera module and portable electronic device utilizing same |
| CN103325694A (en) * | 2012-03-21 | 2013-09-25 | 致伸科技股份有限公司 | Dispensing method used for flip chip manufacturing process |
| CN103325694B (en) * | 2012-03-21 | 2016-08-24 | 致伸科技股份有限公司 | Dispensing method for flip chip manufacturing process |
| CN104465598A (en) * | 2014-12-19 | 2015-03-25 | 江苏长电科技股份有限公司 | Metal lead frame high thermal conductivity flip chip packaging structure and technological method thereof |
| CN107785332A (en) * | 2016-08-24 | 2018-03-09 | 南亚科技股份有限公司 | Semiconductor structure |
| CN108962764A (en) * | 2017-05-22 | 2018-12-07 | 中芯国际集成电路制造(上海)有限公司 | Forming method, semiconductor chip, packaging method and the structure of semiconductor structure |
| CN108962764B (en) * | 2017-05-22 | 2020-10-09 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor structure, semiconductor chip, packaging method and structure |
| US11335648B2 (en) | 2017-05-22 | 2022-05-17 | Semiconductor Manufacturing International (Shanghai) Corporation | Semiconductor chip fabrication and packaging methods thereof |
| CN109558671A (en) * | 2018-11-27 | 2019-04-02 | 中南大学 | A kind of method of edge effect during simulation Flip Chip Underfill Technology |
| CN113517240A (en) * | 2021-05-21 | 2021-10-19 | 华天科技（昆山）电子有限公司 | Wafer fan-out type inverted packaging structure and manufacturing method thereof |
| CN115020396A (en) * | 2022-05-25 | 2022-09-06 | 杭州道铭微电子有限公司 | Chip packaging structure and packaging method |
| CN117558686A (en) * | 2023-09-28 | 2024-02-13 | 锐石创芯(重庆)科技有限公司 | Chip packaging structure and radio frequency front end module |
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