CN101064699B - Method for realizing easily secondary interleaver in time division duplexing synchronous CDMA system - Google Patents

Abstract

A simple realizing method of secondary interweaver in time division duplex synchronization code division multiple-address system, it is based on characters of secondary intertexture course: Matrix line is exchanged, the intertexture address of line head is value instructed in line exchanging mode, the intertexture address of element of adjacent row in every line of matrix is increased by degrees by 30, the intertexture address of void bit which is needed to be deleted is k=U, U+1, U+2, ..., R2XC2-1, secondary intertexture is realized easily. The invention can avoid fussy process course of traditional secondary intertexture, easy and convenient for realizing; at the same time, calculation of various secondary intertexture address can be realized in different intertexture length and different intertexture modes.

Description

The easy implementation method of secondary interleaver in the time division duplexing synchronous CDMA system

Technical field

The present invention relates to a kind of wireless communication system of being applied to, be particularly related to a kind of easy implementation method that is applied to the secondary interleaver in time division SCDMA (Time Division Synchronous Code-Division Multiple Access the is called for short TD-SCDMA) mobile communication system.

Background technology

It is a kind of block interleaving method that secondary interweaves, and performing step comprises: input bit is filled in the matrix, and inserts dummy bit, do exchange between row then, then take out bit sequence from matrix, the deletion of the dummy bit that will wherein fill at last obtains final output bit sequence.

According to the difference of interleave depth, secondary interweaves and can be divided into that frame interweaves and two kinds of time slot interleavings, promptly respectively the bit sequence of frame or time slot is carried out following steps and finishes interleaving process:

Step 1, matrix columns C is set ₂=30, each row of matrix are 0,1,2 according to order number consecutively from left to right ..., c ₂-1;

Step 2, ask the line number R of matrix ₂, R ₂For satisfying the smallest positive integral of following formula:

U≤R ₂×C ₂

Each row of matrix is 0,1,2 according to order number consecutively from top to bottom ..., R ₂-1, U represents the length of input bit sequence;

Step 3, with input bit sequence { x ₁, x ₂, x ₃..., x _UWrite R line by line ₂* C ₂Matrix in, first bit x ₁Insert the 0th row the 0th row:

$\left[\begin{array}{ccccc}{y}_1& y_2& y_3& \·\·\·& y_{C_2}\\ y_{(C_2+1)}& y_{(C_2+2)}& y_{(C_2+3)}& \·\·\·& y_{(2\×C_2)}\\ \·& \·& \·& \·& \·\\ \·& \·& \·& \·& \·\\ \·& \·& \·& \·& \·\\ y_{((R_2-1)\×C_2+1)}& y_{((R_2-1)\×C_2+2)}& y_{((R_2-1)\×C_2+3)}& \·\·\·& y_{(R_2\×C_2)}\end{array}\right]$

Wherein, work as R ₂* C ₂During=U, y then _k=x _k, k=1,2 ..., U; Work as R ₂* C ₂＞U, then fill with dummy bit remaining position in the matrix, that is:

y _k＝x _k， k＝1，2，...，U

y _k=0 or 1, k=U+1, U+2 ..., R ₂* C ₂

Step 4, based on the pattern＜P shown in the following table 1 ₂(j) 〉 _{J ∈ 0,1 ..., C2-1}}Carry out between matrix column exchanging, wherein P ₂(j) be j the preceding original column position of exchange row exchange;

Columns C 2	Switch mode＜P between row 2(0)，P 2(1)，...，P 2(C 2-1)>
		30	<0，20，10，5，15，25，3，13，23，8，18，28，1，11，21，6，16，26，4，14，24，19，9，29，12，2，7，22，27，17>

Switch mode between the row that table 1, secondary interweave

After that is to say that matrix is listed as exchange, the 0th row originally are in the 0th present column position, and the 20th row originally are in the 1st present column position, and the 10th row originally are in the 2nd present column position, and the like;

Bit after exchange note is made y _k', promptly the matrix after the exchange is as follows:

$\left[\begin{array}{ccccc}{\mathrm{<figure-callout\; id="1"\; label="y"\; filenames="H06126171720060522E000011.png"\; state="\{\{state\}\}">y</figure-callout>}}_1^{\&prime;}& y_2^{\&prime;}& y_3^{\&prime;}& \&CenterDot;\&CenterDot;\&CenterDot;& y_{C_2}^{\&prime;}\\ y_{(C_2+1)}^{\&prime;}& y_{(C_2+2)}^{\&prime;}& y_{(C_2+3)}^{\&prime;}& \&CenterDot;\&CenterDot;\&CenterDot;& y_{(2\&times;C_2)}^{\&prime;}\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;& \&CenterDot;\\ y_{((R_2-1)\&times;C_2+1)}^{\&prime;}& y_{((R_2-1)\&times;C_2+2)}^{\&prime;}& y_{((R_2-1)\&times;C_2+3)}^{\&prime;}& \&CenterDot;\&CenterDot;\&CenterDot;& y_{(R_2\&times;C_2)}^{\&prime;}\end{array}\right]$

Step 5, from row between the exchange after R ₂* C ₂Matrix in read the output bit sequence of block interleaver by row; And with in the output sequence between row before the exchange dummy bit filled up in the matrix delete i.e. corresponding bit y _k, the bit y of k＞U _k' need from the output bit sequence, delete; The final output sequence of secondary interleaver is expressed as z ₁, z ₂, z ₃..., z _U

After examining above-mentioned secondary interleaving process, the discovery secondary interweaves and has following characteristics:

1, the input bit sequence x of secondary interleaver ₁, x ₂, x ₃..., x _UMatrix address be k=0,1,2 ..., U-1, the address of the dummy bit sequence of filling is k=U, U+1, U+2 ..., R ₂* C ₂-1; Final output sequence z ₁, z ₂, z ₃..., z _UCorresponding interleaving address is intlv_addr (k), k=0, and 1,2 ..., U-1;

2, after the row exchange, the C of matrix the 0th row ₂The interleaving address of=30 elements just in time is the element＜P as shown in switch mode table 1 between row ₂(j) 〉 _{J ∈ 0,1 ..., C2-1}}

3, after the row exchange, the interleaving address of the element of adjacent lines is that increment increases progressively line by line with 30 in the every row of matrix;

4, after row exchanges, need the interleaving address of the dummy bit deleted to be in the matrix:

k＝U，U+1，U+2，...，R ₂×C ₂-1；

5, final output sequence z ₁, z ₂, z ₃..., z _UCorresponding interleaving address should satisfy:

intlv_addr(k)＜U，k＝0，1，2，...，U-1。

In the chnnel coding process, need carry out secondary to data and interweave; Interleaving process can read out realization with interleaving address again by data are write buffer with sequence address.

In the channel-decoding process, need carry out the secondary deinterleaving to data; The deinterleaving process can read out realization with sequence address again by data are write buffer with interleaving address.

So realize that secondary interweaves, the most critical issue of deinterleaving processing is the generation of secondary interleaving address.Traditional secondary interweaves, deinterleaving handle be by ask the matrix line number, write matrix, the complicated processes of filling dummy bit, rectangular array exchange, sensor matrix, deletion dummy bit finishes, and realizes comparatively complicated.

Summary of the invention

The object of the present invention is to provide the easy implementation method of secondary interleaver in a kind of time division duplexing synchronous CDMA system, it has avoided that traditional realization secondary interweaves asks the matrix line number, write matrix, fill the loaded down with trivial details processing procedure of dummy bit, rectangular array exchange, sensor matrix, deletion dummy bit, can realize easily and flexibly and use.

In order to solve the problems of the technologies described above, simultaneously according to the characteristics in the above-mentioned described secondary interleaving process, the invention provides the easy implementation method of secondary interleaver in a kind of time division duplexing synchronous CDMA system, it comprises following steps:

Step 1, input weaving length U promptly import input bit sequence x ₁, x ₂, x ₃..., x _ULength U;

Step 2, according to the first address table of each row of switch mode initialization matrix between row, i.e. the 0th row address table: column_addr[i of initialization matrix]=＜P ₂(i) 〉 _{I ∈ 0,1 ..., C2-1}}, wherein, C ₂=30, total columns of representing matrix, P ₂(i) expression i is listed in the preceding original column position of exchange;

Step 3, the first element of initialization matrix, promptly the interleaving address value of the 0th row the 0th column element is 0, i.e. intlv_addr[0]=column_addr[0]=0;

Step 4, whether be j element in the output sequence by the current processing element of the capable i row of leu time judgment matrix k, wherein, j ∈ (0,1 ..., U-1); If, then calculate its interleaving address value, and redirect execution in step 6; If not, then continue execution in step 5;

Step 5, by the first address table column_addr[i of each row] in read the first address of next column, the first address that is read is the interleaving address value of row header element for this reason, i.e. intlv_addr[j]=column_addr[i];

Step 6, according to weaving length U, judge whether to have calculated whole interleaving address of output sequence:

If j＜U-1 then returns step 4, continue interleaving address by the next matrix element of column count;

If j=U-1 then finishes to interweave computing.

Described step 4 also specifically comprises following steps:

Step 4.1, the interleaving address value of j-1 output sequence is added 30,, the interleaving address value of the element of the capable i row of k-1 is added 30, intlv_addr[j-1 is arranged promptly for the current processing element that is in the capable i row of matrix k]+30:

Step 4.2, judge intlv_addr[j-1]+whether 30 value greater than weaving length U:

If intlv_addr[j]＜U, then current processing element is a j element in the output sequence, calculates its interleaving address value, that is: intlv_addr[j]=intlv_addr[j-1]+30, and the direct execution in step 6 of redirect;

If intlv_addr[j]＞=U, then current processing element is the dummy bit that is packed into matrix, or exceeds the illegal address of matrix scope, execution in step 5.

The easy implementation method of secondary interleaver in the time division duplexing synchronous CDMA system provided by the invention has the following advantages:

1, simple and convenient, be beneficial to realization; This method can thoroughly avoid traditional asking the matrix line number, write matrix, fill the loaded down with trivial details processing procedure of dummy bit, rectangular array exchange, sensor matrix, deletion dummy bit.

2, because unique suction parameter of this method is weaving length U, so can unify frame interlace mode and time slot interleaving pattern, and the computational process of interleaving address under the different interleaving length, make that the calculating of interleaving address can shared same hardware module realize under frame interlace mode and the time slot interleaving pattern; As long as change the parameter weaving length U of input, promptly can be used for different interleaving length, the calculating of the secondary interleaving address under the different interleaving pattern.

Description of drawings

Fig. 1 is the flow chart of the easy implementation method of secondary interleaver in the time division duplexing synchronous CDMA system provided by the invention.

Embodiment

Following according to Fig. 1, better embodiment of the present invention is described.

As shown in Figure 1, be the flow chart of the easy implementation method of secondary interleaver in the time division duplexing synchronous CDMA system provided by the invention, it comprises following steps:

Step 1, input weaving length U promptly import input bit sequence x ₁, x ₂, x ₃..., x _ULength U, in the present embodiment, get U=100;

Step 2, according to the first address table of each row of switch mode initialization between row, i.e. the 0th row address table of initialization matrix:

$\mathrm{column}\_\mathrm{addr}\left[i\right]={<P_2\left(i\right)>}_{i\&Element;\{\mathrm{0,1},...,C_2-1\}}$

$=<\mathrm{0,20,10,5,15,25,3,13,23,8,13,28,1,11,21,6,16,26,4,14,24,19,9,29,12,2,7,22,27,17},>$

Wherein, C ₂=30, total columns of representing matrix, P ₂(i) expression i is listed in the preceding original column position of exchange, after just matrix was listed as exchange, the 0th row originally were in the 0th present column position, and the 20th row originally are in the 1st present column position, the 10th row originally are in the 2nd present column position, and the like;

Step 3, the first element of initialization matrix, promptly the interleaving address value of the 0th row the 0th column element is 0, i.e. intlv_addr[0]=column_addr[0]=0, and assignment i=0, j=0;

Step 4, whether be element in the output sequence by each current processing element in the leu time judgment matrix;

Step 4.1, make j=j+1=0+1=1; With j-1, just the interleaving address value of the 0th output sequence adds 30, promptly for the current processing element that is in matrix the 1st row the 0th row, the interleaving address value of the element of the 0th row the 0th row is added 30, and intlv_addr[j-1 is arranged]+30=0+30=30:

Step 4.2, judge intlv_addr[j-1]+whether 30 value greater than weaving length U: if intlv_addr[j]＜U, calculate intlv_addr[j]=intlv_addr[j-1]+30, and the direct execution in step 6 of redirect; If intlv_addr[j]＞=U, then execution in step 5;

According to step 4.1, because intlv_addr[j-1]+30 value is 30, so it is 30 less than weaving length U obtain the interleaving address value of the 1st output sequence, and direct execution in step 6;

Step 5, make i=i+1=0+1=1; First address table column_addr[i by each row] in read the first address of next column, this first address that reads is the interleaving address value of row header element for this reason, i.e. intlv_addr[j]=column_addr[i];

Step 6, according to weaving length U=100, judge whether to have calculated whole interleaving address of output sequence: if j＜U-1, then return step 4; If j=U-1 finishes to interweave computing;

According in the step 4, j=1 is significantly less than weaving length U=100, then returns execution in step 4;

Analogize according to said process, calculate interleaving address according to this, in the present embodiment, when the value of j is 4,7,10,14 ... the time, when execution in step 4.2, judge and to obtain intlv_addr[j-1]+situation more than or equal to weaving length U can appear in 30 value, illustrate that it is the illegal address that surpasses the matrix scope, or the dummy bit of filling, this moment execution in step 5, read the row first address 20,10,5,15 of next column ..., and respectively as the 4th, 7,10,14 ... the interleaving address of individual output sequence; When the value of j is U-1,, finish to interweave computing at promptly 99 o'clock.

The easy implementation method of secondary interleaver in the time division duplexing synchronous CDMA system provided by the invention has the following advantages:

1, simple and convenient, be beneficial to realization; This method can thoroughly avoid traditional asking the matrix line number, write matrix, fill the loaded down with trivial details processing procedure of dummy bit, rectangular array exchange, sensor matrix, deletion dummy bit.

2, because unique suction parameter of this method is weaving length U, so can unify frame interlace mode and time slot interleaving pattern, and the computational process of interleaving address under the different interleaving length, so that the calculating of interleaving address can share same hardware module and realizes under frame interlace mode and the time slot interleaving pattern; As long as change the parameter weaving length U of input, namely can be used for different interleaving length, the calculating of the secondary interleaving address under the different interleaving pattern.

Claims (1)

1. the easy implementation method of secondary interleaver in the time division duplexing synchronous CDMA system is characterized in that, comprises following steps:

Step 1, input weaving length U promptly import input bit sequence x ₁, x ₂, x ₃..., x _ULength U;

Step 2, according to the first address table of each row of switch mode initialization matrix between row, i.e. the 0th row address table of initialization matrix: $\mathrm{columm}\_\mathrm{addr}\left[i\right]={<P_2\left(i\right)>}_{i\&Element;\{\mathrm{0,1},...,C_2-1\}},$ Wherein, C ₂=30, total columns of representing matrix, P ₂(i) expression i is listed in the preceding original column position of exchange;

Step 3, the first element of initialization matrix, promptly the interleaving address value of the 0th row the 0th column element is 0, i.e. intlv_addr[0]=column_addr[0]=0;

Step 4, whether be j element in the output sequence by the current processing element of the capable i row of leu time judgment matrix k, wherein, j ∈ (0,1 ..., U-1); If, then calculate its interleaving address value, and redirect execution in step 6; If not, then continue execution in step 5;

Described step 4 comprises following steps:

Step 4.1, the interleaving address value of j-1 output sequence is added 30,, the interleaving address value of the element of the capable i row of k-1 is added 30, intlv_addr[j-1 is arranged promptly for the current processing element that is in the capable i row of matrix k]+30;

Step 4.2, judge intlv_addr[j-1]+whether 30 value greater than weaving length U:

If intlv_addr[j]＜U, then current processing element is a j element in the output sequence, calculates its interleaving address value, that is: intlv_addr[j]=intlv_addr[j-1]+30, and the direct execution in step 6 of redirect,

If intlv_addr[j]＞=U, then current processing element is the dummy bit that is packed into matrix, or exceeds the illegal address of matrix scope, execution in step 5;

Step 5, by the first address table column_addr[i of each row] in read the first address of next column, the first address that is read is the interleaving address value of row header element for this reason, i.e. intlv_addr[j]=column_addr[i];

Step 6, according to weaving length U, judge whether to have calculated whole interleaving address of output sequence:

If j＜U-1 then returns step 4, continue interleaving address by the next matrix element of column count;

If j=U-1 then finishes to interweave computing.

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