CN104617959A - Universal processor-based LDPC (Low Density Parity Check) encoding and decoding method - Google Patents

Abstract

The invention discloses an LDPC (Low Density Parity Check) encoding method. The method comprises the following steps: determining vectors p1 and p2 and obtaining an encoding result vector, wherein multiplication processing of any matrix and any vector during determination of the vectors p1 and p2 comprises the steps of taking each row of any matrix as a thread, multiplying the corresponding row of the matrix by any vector and constituting the multiplication results of all rows into a result vector; the multiplication operation of any row of any matrix by any vector comprises the steps of determining a vector starting position corresponding to each element j of the ith row of the matrix, performing left shift on data of length Z-Ai, j from a starting position in any vector through a single-instruction multiple-data stream mode, shifting the data of length Ai, j in front of the starting position to the space after the data subjected to left shift to obtain a vector shift result corresponding to the element j and adding the vector shift result of each element. Through the method, the encoding speed can be improved in a universal processor by using multi-thread and SIMD (Single Instruction Multiple Data) processing.

Description

A kind of LDPC coding and decoding method based on general processor

Technical field

The application relates to LDPC coding and decoding technology, particularly a kind of LDPC coding and decoding method based on general processor.

Background technology

LDPC code is the linear block codes that a kind of code length is larger.Its check matrix is also comparatively large, and nonzero element in check matrix is little, and namely the number of " 1 " is little, therefore claims low-density.

In the process realizing IEEE 802.11n WLAN (wireless local area network) host-host protocol, LDPC coding and decoding technology need be used, according to protocol requirement, wherein LDPC PPDU (Presentation Protocol Data Unit, presentation protocol data unit) generative process as follows, see Fig. 1:

(1) shortening bit is calculated

(1a) available bit number N is calculated _avbits, formula is:

N _pld＝length×8+16，

Wherein, if having STBC (Space-time block code) precoding, then flag bit m _sTBCbe 2, otherwise be 1; N _cBPSrepresent the number of coded bits of each symbol; Length represents the byte number of PSDU (presentation Service DataUnit), is the byte number of information bit position; N _pldrepresent total bit number of PSDU and SERVICE FIELD; R presentation code code check.

(1b) LDPC code word number N is calculated _cWwith code length L _lDPC

Work as N _avbitswhen≤648, code word number N _cWbe 1, and if N _avbits>=N _pldduring+912 × (1-R), code length L _lDPCbe 1296, otherwise code length L _lDPCbe 648; Work as 648<N _avbitswhen≤1296, code word number N _cWbe 1, and if N _avbits>=N _pldduring+1464 × (1-R), code length L _lDPCbe 1944, otherwise code length L _lDPCbe 1296; Work as 1296<N _avbitswhen≤1944, code word number N _cWbe 1, now code length L _lDPCbe 1944; Work as 1944<N _avbitswhen≤2592, code word number N _cWbe 2, and if N _avbits>=N _pldduring+2916 × (1-R), code length L _lDPCbe 1944, otherwise code length L _lDPCbe 1296; Work as N _avbitsduring >2592, code word number N _cWfor now code length L _lDPCbe 1944;

(1c) shortening bit number N is calculated _shrt, after shortening bit is filled into information bit position before LDPC coding:

N _shrt＝max(0,(N _CW×L _LDPC×R)-N _pld)

Work as N _shrtwhen=0, do not carry out benefit 0 and operate.Work as N _shrtduring >0, shorten bit at all N _cWindividual code word is evenly distributed, namely each code assignment to shortening bit number be if N _shrtmodN _cW≠ 0, wherein mod is remainder, i.e. N _shrtto N _cWremainder, then first more than other code words one of code word shortens bit.

(2) carry out LDPC coding, obtain check bit position.

(3) shortening bit is abandoned

(4) calculate punching bit position number and abandon punching bit position, calculating the rear punching bit position number N of LDPC coding according to following formula _punc:

N _punc＝max(0,(N _CW×L _LDPC)-N _avbits-N _shrt)

If or (N _punc>0.3 × N _cW× L _lDPC× (1-R)), increase N _avbitsthen N is recalculated according to following formula _punc:

N' _avbits＝N _avbits+N _CBPS×m _STBC，N _punc＝max(0,(N _CW×L _LDPC)-N' _avbits-N _shrt)

Punching bit position is at all N _cWindividual code word is evenly distributed, namely each code assignment to punching bit position number be if N _puncmodN _cW≠ 0, wherein mod is remainder, i.e. N _puncto N _cWremainder, then first code word punching bit position more than other code words.

(5) calculate repetition bits position, calculate repetition bits position number N according to following formula _rep:

N _rep＝max(0,N' _avbits-N _CW×L _LDPC×(1-R)-N _pld)

Repetition bits position is at all N _cWindividual code word is evenly distributed, namely each code assignment to repetition bits position number be if N _repmodN _cW≠ 0, wherein mod is remainder, i.e. N _repto N _cWremainder, then first code word repetition bits position more than other code words.Repetition bits position order from first bit of information bit position is chosen, until meet length requirement, repetition bits position is copied from the code word after the shortening bit removed.The repetition bits position selected is linked in sequence after check bit position.When needs punch, check bit position does not need repetition, and vice versa.

In LDPC PPDU generative process, LDPC coding method is the most important, and the codeword vector exported after LDPC coding is designated as c=(S, p ₁, p ₂), wherein S is information vector, p ₁and p ₂for code word verification vector, but because of the check matrix H of LDPC code comparatively large, the computing in cataloged procedure will be very loaded down with trivial details.Observe the check matrix provided in agreement can find out, its row weight average of the matrix under different code check R is 24, and its column weight is 24 × (1-R), according to the characteristic of check matrix H, is carried out following piecemeal $H\left(\begin{array}{ccc}A& B& T\\ F& D& E\end{array}\right),$ Be divided into matrix A, matrix B, matrix D, matrix E, matrix T and matrix F six submatrixs, wherein the structure of matrix B, matrix D, matrix E and matrix T is comparatively special, B=(1--... 0-...) ^t, D=(1), E=(-...-0), the structure irregularities of matrix A and matrix F, see agreement 802.11n.In addition, because check matrix H is larger, therefore, when representing check matrix, by a submatrix in an actual check matrix of element representation, particularly, in the method for expressing of check matrix H and matrix in block form A, B, D, E, T, F, "-" represents that this submatrix is null matrix, and " 0 " represents that this submatrix is unit matrix, and " constant C " represents that this submatrix is the matrix of consequence behind unit Matrix C time ring shift right position.Wherein the dimension of submatrix is that Z*Z, Z can determine according to code length in advance.By the way, the expression size of check matrix and each matrix in block form can be greatly reduced.

Under the prerequisite of known check matrix H and information vector S, determine that the concrete mode of codeword vector c is: according to check equations Hc ^t=0 ^tcan score solve an equation $\left\{\begin{array}{c}{\mathrm{AS}}^T+{\mathrm{Bp}}_1^T+{\mathrm{Tp}}_2^T=0\\ (-{\mathrm{ET}}^{-1}A+F)S^T+(-{\mathrm{ET}}^{-1}B+D)p_1^T=0\end{array}\right.,$ Can obtain after optimizing $\left\{\begin{array}{c}{p}_1^T=({\mathrm{ET}}^{-1}A+F)S^T\\ p_2^T=T^{-1}({\mathrm{AS}}^T+{\mathrm{Bp}}_1^T)\end{array}\right.,$ Obtain p ₁and p ₂after, codeword vector c=(S, p can be obtained ₁, p ₂).

With reference to the composition of the encoder of above-mentioned LDPC cataloged procedure see Fig. 2, wherein containing 4 kinds of functional modules: pre-encoding matrix generator, matrix multiplier, matrix adder and LDPC code word synthesizer.

6 pre-encoding matrix generator are had in this encoder, its input is a matrix, matrix A, matrix B, matrix D, matrix E, matrix T and matrix F six submatrixs respectively, its output is a matrix, be through the matrix after pre-encoding matrix generator process, its function is the mode stored by compression by the matrix of input, namely only deposits matrix non-zero element, input matrix is converted, obtains output matrix.

6 multipliers are had in this encoder, it has two inputs output, two inputs be respectively information vector S, matrix A, by the matrix after pre-encoding matrix generator process, by the matrix of consequence of other multipliers or by two in the matrix of consequence after adder, its output is a matrix, be the result vector after two inputs carry out multiplying, its function is that two inputs are carried out matrix multiplication operation and Output rusults matrix.

This encoder has 2 matrix adders, its input is two matrixes, and be matrix multiplier in encoder and export rear matrix, its output is a matrix, be the result after two input matrixes carry out addition of matrices, its function is that two input matrixes are carried out addition of matrices and Output rusults matrix.

Have 1 LDPC code word synthesizer in this encoder, its input is three vectors, is information vector S, code word verifies vectorial p ₁vectorial p is verified with code word ₂, its output is a vector, is codeword vector c, and its function is that information vector S, code word are verified vectorial p ₁vectorial p is verified with code word ₂three vector synthesis codeword vector c=(S, p ₁, p ₂) and codeword vector c.

Above-mentioned existing LDPC coding method and the corresponding encoder of being is formed.At receiving terminal, also needing the LDPC code word to receiving to carry out decoding, obtaining the information vector of rebuilding.Existing LDPC decoding technique, its key step is as follows:

(1) M checkpoint is divided into M _blayer, every layer comprises T check-node.Next, one deck connects the order execution decode procedure of one deck.In ground floor processing procedure, calculate the information of check-node and variable node, after ground floor decode procedure terminates, the second layer uses the information of the variable node obtained from ground floor to carry out initialization, and by that analogy;

(2) initialization: use LLRs (log-likelihood ratios, namely information to variable node value carry out initialization, and by all check-node information be set to 0, the iterations of decoding algorithm is I, and iterative process is carried out by row, the n ∈ N wherein in minimum-sum algorithm _mrepresent check matrix prototype H _bin [H _b] _m,nthe row of ≠ '-';

(3) minimize: variable node vector q _nring shift right position (shift count S (m, n)=[H _b] _m,n) deduct check-node information be there is vectorial t in result _nin, according to OMS (offset min-sum, namely value reuse characteristic, only need minimum value and the sub-minimum of element in compute vector;

(4) minimum value is selected: to n ∈ N _m, calculate and upgrade q _nwith value.

For realizing above-mentioned interpretation method, existing decoder, see Fig. 3, is made up of 4 parts, is respectively initialization translator unit, minimum value and sub-minimum selected cell, data brachymemma unit and cycle shift unit.

Initialization translator unit in this decoder, its input is a LDPC test matrix, its output is a test matrix after the process of initialization decoding unit, and its function to be carried out by test matrix storing conversion according to decoder input requirements and test matrix after output processing.

Minimum value in this decoder and sub-minimum selected cell, its input is two matrixes, one of them is through the test matrix after the process of initialization translator unit, another is LDPC code word matrix c, namely the LDPC code word matrix c after wireless channel transmission, its output is a matrix after minimum value and the process of sub-minimum selected cell, and its function is the minimum value of the difference calculated between variable node ring shift right position and check-node and sub-minimum and Output rusults matrix is supplied to data brachymemma unit and cycle shift unit.

The data brachymemma unit of this decoder, its input be one by the matrix exported after minimum value and the process of sub-minimum selected cell, its output is a matrix after data brachymemma cell processing, its function is the spilling for preventing check-node information, data brachymemma process is carried out to it, and Output rusults matrix is supplied to cycle shift unit.

The cycle shift unit of this decoder, its input is two matrixes, one of them is by the matrix exported after data brachymemma cell processing, another is by the matrix exported after minimum value and the process of sub-minimum selected cell, its output is a matrix after cycle shift unit process, its function adds calculate variable node matrix by minimum value matrix and check-node matrix being carried out step-by-step mould two, and output variable node matrix equation.

As mentioned above, the coding and decoding theory of current LDPC code is comparatively ripe, but because LDPC code is the linear block codes that a kind of code length is larger, check matrix is also larger, algorithm complex is very high, traditional LDPC coding and decoding mode is not well positioned to meet the throughput requirement of IEEE 802.11n system, has largely had influence on the performance of system.In existing high speed wireless access system, the realization of LDPC code is mostly based on FPGA (Field-Programmable GateArray, field programmable gate array) chip and DSP (Digital Signal Processor, Digital Signal Processing) chip.Although can be met the requirement of process and time delay in Modern High-Speed protocol of wireless local area network by previous methods, FPGA programming and professional DSP all more complicated, lack abundant programmed environment and debugging acid, applicability is general.

Summary of the invention

The application provides a kind of LDPC coding and decoding method based on general processor, can realize LDPC coding and decoding efficiently on aageneral-purposeaprocessor.

For achieving the above object, the application adopts following technical scheme:

Based on a LDPC coding method for general processor, comprising: obtain signal vector S to be encoded by signals collecting or reception, determine check matrix H and matrix in block form A, B, D, E, F and T, and preserve; According to $\left\{\begin{array}{c}{p}_1^T=({\mathrm{ET}}^{-1}A+F)S^T\\ p_2^T=T^{-1}({\mathrm{AS}}^T+{\mathrm{Bp}}_1^T)\end{array}\right.$ Determine vectorial p ₁and p ₂, and obtain coding result vector c=(S, the p of LDPC ₁, p ₂); Wherein, describedly vectorial p is determined ₁and p ₂arbitrary matrix of Shi Jinhang comprises with the process that is multiplied of arbitrary vector:

Using every a line of described arbitrary matrix as a thread, carry out the corresponding line of this matrix and the multiplication operations of described arbitrary vector, and the multiplied result of all row is combined formation result vector;

Wherein, every a line of described arbitrary matrix comprises with the multiplication operations of described arbitrary vector: the original position+A determining vectorial original position=described arbitrary vector that each element j of current i-th row of matrix is corresponding _i,j+ (j-1) * Z, by described arbitrary vector from described original position Z-A _i,jthe data of length are shifted left by the mode of single-instruction multiple-data stream (SIMD) SIMD, and A before described original position is started _i,jafter data after the data of length move to and shift left, obtain the vector shift result that described element j is corresponding; Again by vector shift results added corresponding for each element, as the multiplied result of described every a line and described arbitrary vector;

In the mode of described SIMD, will from described original position Z-A _i,jthe data of length are divided in units of length W section is right segment data is parallel carries out operation of shifting left, then by remaining (Z-A _i,j) data of modW length carry out operation of shifting left;

Z is the submatrix size of an element representative in described check matrix.

Preferably, when described arbitrary matrix is T ^-1time, described T ^-1every a line and the multiplication operations of corresponding vector time, only carry out T ^-1value is being multiplied of element and the corresponding vector of 0, and obtaining this value is the vector shift result that 0 element is corresponding, and vector shift result corresponding for all the other elements is set to null vector; Again by vector shift results added corresponding for each element, as the multiplied result of described every a line and described arbitrary vector.

Preferably, W segment data is shifted left after operation simultaneously to get a front Z data be valid data.

Preferably, described vector shift results added corresponding for each element to be comprised: vector shift result corresponding for each element is divided in units of length W section, by SIMD couple segment data is parallel carries out phase add operation, then by remaining (Z-A _i,j) data of modW length carry out phase add operation.

Preferably, described matrix A, B, D, E, F and T ^-1preserved by linear search table.

Based on a LDPC interpretation method for general processor, comprising: receive encoded LDPC code word signal c, determine check matrix H; Calculate variable node vector q as decode results by successive ignition, during each iteration, calculating temporary variable vector according to current variable node vector q and check-node vector r is and upgrade check-node vector r according to the vectorial t of described temporary variable, then according to check-node vector r and temporary variable vector t renewal variable node vector q be during first iteration, using character signal c as variable node vector q, verification knot vector r is set to 0; Wherein,

When each iterative computation temporary variable vector t, check-node vector r and variable node vector q, carry out computing and renewal using every a line of check matrix as a thread, obtain with often to go in corresponding vectorial t, q and r call number from arrive subvector; Wherein, i is the line index of check matrix, when the i-th row of corresponding described check matrix calculates temporary variable vector t, check-node vector r and variable node vector subvector corresponding to q, according to each non-"-" element H of this row of check matrix _i,jwith element H in corresponding compute vector t, q and r _i,jcorresponding call number from arrive subvector, then carry out successively connecting and obtain and often go corresponding subvector, during i=1, order

Calculate and H _i,jthe mode of corresponding temporary variable vector t subvector is: determine H _i,jcorresponding vectorial original position Z* (n-1)+H _i,n, original position described in vectorial q subvector corresponding for the i-th row is played length is or the data of 6 are copied to and H by the mode of SIMD _i,jthe beginning of corresponding temporary variable vector t subvector; At H _i,n≠ 0, H _i,n≠ '-' and (Z-H _i,n) modW ≠ 0 time, determine matrix M _{ldpcAssemble1}in with check matrix element H _i,jthe value of each element in corresponding row and will with element H _i,jin the subvector of corresponding current vectorial q, call number is each element copy to successively and H _i,jin the current location of corresponding temporary variable vector t subvector; Determine each element H again _i,jcorresponding secondary vector original position M _ldpcOffset2, described secondary vector original position is played length is data copied to and H by the mode of SIMD _i,jin the current location of corresponding temporary variable vector t subvector; Get and H _i,jfront Z position in corresponding temporary variable vector t subvector and take absolute value as with H _i,jeffective subvector of corresponding temporary variable vector t;

Work as H _i,n≠ 0, H _i,n≠ '-' and (Z-H _i,n) modW ≠ 0 time, work as H _i,n=0 or H _i,n='-' or (Z-H _i,n) modW=0 time, (M _ldpcOffset2) _i,j=Z* (n-1); k is that general processor once can deal with data amount size, and k is the fundamental unit size of SIMD process; Code length L _lDPCwhen=648, LdpcRemain=11; As code length L _lDPCwhen=1296, LdpcRemain=6; As code length L _lDPCwhen=1944, LdpcRemain=1; J is the index of each non-"-" element in this row all non-"-" element in the i-th row, and n is the i-th row jth column index of non-"-" element in check matrix.

Preferably, calculating with the mode of the check-node vector r subvector that often row is corresponding of check matrix is:

Write as V by with the check matrix temporary variable vector t subvector that often row is corresponding _{ldpcRowLength}(v) row and the matrix T of row _v, wherein, described matrix T _veach behavior described in temporary variable vector t subvector with element H _i,jcorresponding subvector, carries out cover when columns is inadequate;

To described matrix T _vbe worth most distribution, be worth variable vector m subvector matrix M most _v;

According to described matrix T _vcalculate intermediate variable vector s subvector matrix S _v;

According to described matrix M _vwith described matrix S _vthe element that middle index value is identical, determines an intermediary matrix R _v' in the element value of respective index value; Wherein, if matrix S _vin arbitrary element be less than 0, then get the complement of this arbitrary element and be added with this arbitrary element, using addition result as matrix R _v' in be worth the value of identical element with described arbitrary element index; If matrix S _vin arbitrary element equal 0, then this arbitrary element is added with 0, using addition result as matrix R _vin be worth the value of identical element with described arbitrary element index; If matrix S _vin arbitrary element >0, then in matrix M _vin get and be worth identical element with described arbitrary element index and be added with described arbitrary element, using addition result as matrix R _vin be worth the value of identical element with described arbitrary element index; Described operation of comparing and be added is undertaken by the mode of SIMD;

By SIMD mode by described matrix R _v' and matrix T _vthe element that middle index value is identical subtracts each other, using result as check-node vector r subvector matrix R _vthe element value of middle same index value; By described matrix R _vin front Z element of every row read the vectorial r subvector of composition check-node successively according to the mode of row major.

Preferably, be worth distribution described in most to comprise:

Described matrix T is determined by the mode of SIMD _vin minimum value of each row and sub-minimum and line index corresponding to minimum value; The minimum value obtained and sub-minimum are revised, all deducts default correction value β, when revised minimum value and sub-minimum are less than 0, are set to 0, otherwise remain unchanged;

According to described matrix T _vin the current minimum value of each row, sub-minimum and line index corresponding to minimum value, structure value variable vector m subvector matrix M _vthe row of middle same index, wherein, at M _varbitrary row in, be set to the element of the corresponding identical line index of current minimum value the minimum value determined, all the other elements be set to sub-minimum.

Preferably, the described mode by SIMD determines that the mode of each minimum value arranged and sub-minimum and corresponding line index comprises:

By described matrix T _veach row element be divided into individual sub-block, each sub-block comprises W base unit; In more described matrix T _vin the element of any two row time, compare W base unit by the mode of SIMD is disposable.

Preferably, described calculating intermediate variable vector s subvector matrix S _vcomprise:

For matrix T _vin each row, this row all elements is carried out xor operation, then by result and i-th ' row element XOR after to carry out with 0x7f or operate, general or operating result are as intermediate vector matrix S _vmiddle same index row i-th ' row element; Wherein, by described matrix T _veach row element be divided into individual sub-block, each sub-block comprises W base unit, when carrying out XOR/or operation, by XOR/or the operation of the disposable execution W base unit of the mode of SIMD.

Preferably, calculating and H _i,jcorresponding variable node vector q subvector comprises:

Determine H _i,jcorresponding vectorial original position Z* (n-1)+H _i,n, by SIMD mode by H _i,jcorresponding temporary variable vector t subvector and H _i,jcorresponding check-node vector r subvector is added, and original position described in result vector is played length is or the data of 5 are copied to and H by the mode of SIMD _i,jthe beginning of corresponding variable node vector q subvector; At H _i,n≠ 0, H _i,n≠ '-' and (Z-H _i,n) modW ≠ 0 time, determine matrix M _{ldpcAssemble1}in with check matrix element H _i,jthe value of each element in corresponding row and will with element H _i,jin the subvector of corresponding current vectorial q, call number is each element copy to successively and H _i,jin the current location of corresponding variable node vector q subvector;

Determine each element H _i,jcorresponding secondary vector original position M _ldpcOffset2, described secondary vector original position is risen length be 0 or data copied to and H by the mode of SIMD _i,jin the current location of corresponding variable node vector q subvector;

According to the cover number of LdpcRemain instruction, according to M _{ldpcAssemble1}in with check matrix element H _i,jin corresponding row, the value of element carries out cover.

Preferably, precalculate and preserve each element H _i,jcorresponding vectorial original position Z* (n-1)+H _i,nwith secondary vector original position M _ldpcOffset2, matrix M _{ldpcAssemble1}, the vectorial V that forms of the number of often going non-"-" element in check matrix _{ldpcRowLength}, M _{ldpcAssemble1}, LdpcRemain.

As seen from the above technical solution, the LDPC coding and decoding method in the application, can improve coding and decoding speed by SIMD instruction, multithreading and the mode such as to prestore.

Accompanying drawing explanation

Fig. 1 is the generative process schematic diagram of LDPC PPDU;

Fig. 2 is the encoder composition schematic diagram of LDPC cataloged procedure;

Fig. 3 is existing ldpc decoder schematic diagram;

Fig. 4 is the overview flow chart of coding method in the application;

Fig. 5 is that in the application LDPC coded treatment, compute codeword verifies vectorial p ₁computing schematic diagram;

Fig. 6 is that in the application LDPC coded treatment, compute codeword verifies vectorial p ₂computing schematic diagram;

Fig. 7 is the structural representation optimizing multiplier 1;

Fig. 8 is the structural representation optimizing multiplier 2;

Fig. 9 is the structural representation optimizing adder;

Figure 10 is that an element in matrix A is multiplied with the transposition of vectorial S the schematic diagram processed;

Figure 11 is the process schematic diagram of step 5 in the application LDPC coding method;

Figure 12 is the process schematic diagram of step 5 in the application LDPC interpretation method;

Figure 13 is the idiographic flow use figure of the application LDPC interpretation method;

Figure 14 is for the schematic flow sheet being worth allocation process most that a sub-block is carried out in the application LDPC interpretation method;

Figure 15 is the structural representation being once worth most distributive operation in LDPC interpretation method;

Figure 16 is the schematic flow sheet calculating intermediate variable vector in LDPC interpretation method for a sub-block;

Figure 17 is the structural representation of an intermediate vector calculating in LDPC interpretation method.

Embodiment

In order to make the object of the application, technological means and advantage clearly understand, below in conjunction with accompanying drawing, the application is described in further details.

The application provides the LDPC coding method and interpretation method that are applicable to realize in general processor.Coding method in the application and interpretation method are described below in detail.

According to the LDPC PPDU generation method in IEEE 802.11n agreement, codeword vector after coding is designated as c=(S, p ₁, p ₂), wherein S is information vector, p ₁and p ₂for code word verification vector, check matrix H is simplified six parts $H\left(\begin{array}{ccc}A& B& T\\ F& D& E\end{array}\right),$ Be divided into matrix A, matrix B, matrix D, matrix E, matrix F and matrix T six submatrixs.Before carrying out decoding, need extraneous input code length L _lDPC, encoder bit rate R and information vector S.The application optimizes LDPC coding method as follows according to the characteristic of general processor (GPP) chip architecture:

1, SIMD (Single Instruction Multiple Data is adopted, single-instruction multiple-data stream (SIMD)) operation method coding method is optimized, its essential concept is the effect processing to obtain parallel processing within a clock cycle of CPU to multiple data, and similarly is not common occupation mode---each clock cycle only carries out a data processing operation.Wherein will relate to used general processor once can deal with data amount size, and suppose that this size is K bit, the fundamental unit size of SIMD process is k, then once-through operation can deal with data amount

2, the information adopting the method for linear search table to optimize check matrix stores, and check matrix H is split into six parts $H\left(\begin{array}{ccc}A& B& T\\ F& D& E\end{array}\right),$ Be divided into matrix A, matrix B, matrix D, matrix E, matrix F and matrix T six submatrixs, and generate six linear search tables with these six submatrixs, reduce computation complexity.

3, adopt the method for multithreading, with the line number of check matrix H for Thread Count, be namely a thread with data line process in check matrix H, the process performing multiple thread at one time operates, and then the disposed of in its entirety performance of elevator system.

Fig. 4 is the general flow chart of coding method in the application, wherein, this coding method based on algorithm principle identical with current LDPC coding method, the specific implementation that difference is for coding method in general processor.Idiographic flow is as follows:

1, according to 802.11n agreement, different code length L _lDPCand different coding code check R correspond to different check matrix H.First, according to code length L _lDPCand encoder bit rate R, extract corresponding check matrix H, and initialization carried out to following parameters:

1.1 generator matrix A, matrix B, matrix D, matrix E, matrix F and matrix T ^-1six submatrixs, wherein () ^-1for inverse of a matrix, and it is stored in successively in linear search table, with the particular location of the method mark desired data of side-play amount, exchanges computation complexity for internal memory, improve the data processing speed of LDPC code coding method.

1.2 sizes generating submatrix representated by each element in selected check matrix H are Z.As code length L _lDPCwhen=648, Z=27; As code length L _lDPCwhen=1296, Z=54; As code length L _lDPCwhen=1944, Z=81.

2, according to GPP chip characteristic, the method of multithreading is adopted to be optimized coding method, with the line number of check matrix H for Thread Count, data line wherein in check matrix H is that a thread process step 3 is to step 4, perform the process operation of multiple thread at one time, namely the same time carries out the process of multiple step 3 to step 4, and then the disposed of in its entirety performance of elevator system.Following step 3 and step 4, be the idiographic flow of single thread process.

3, compute codeword verifies vectorial p ₁, multiplying wherein and add operation all adopt the operation method of SIMD to be optimized, and its computing schematic diagram is see Fig. 5, and idiographic flow is as follows:

3.1 matrix A are multiplied with the transposition of vectorial S, and result is vector, and vector length is equal with the line number of matrix A.

3.2 matrix T ^-1be multiplied with the transposition of step 3.1 acquired results vector, result is vector, vector length and matrix T ^-1line number equal.

3.3 matrix E are multiplied with the transposition of step 3.2 acquired results vector, and result is vector, and vector length is equal with the line number of matrix E.

3.4 matrix F are multiplied with the transposition of vectorial S, and result is vector, and vector length is equal with the line number of matrix F.

3.5 step 3.3 acquired results vectors and step 3.4 acquired results addition of vectors, result is code word and verifies vectorial p ₁.

4, compute codeword verifies vectorial p ₂, multiplying wherein and add operation all adopt the operation method of SIMD to be optimized, and its computing schematic diagram is see Fig. 6, and idiographic flow is as follows:

4.1 matrix B and vectorial p ₁transposition be multiplied, result be vector, vector length is equal with the line number of matrix B.

4.2 step 3.1 acquired results vectors and step 4.1 acquired results addition of vectors, result is vector.

4.3 matrix T ^-1be multiplied with the transposition of step 4.2 acquired results vector, result is code word and verifies vectorial p ₂.

5, LDPC code word vector c is assembled:

By gained vector according to S, p ₁, p ₂sequential storage, obtain LDPC code word vector c=(S, p ₁, p ₂).

In the coding method of above-mentioned the application, relate to two kinds of optimization multipliers and a kind of optimization adder, become respectively and optimize multiplier 1, optimize multiplier 2 and optimize adder.According to GPP chip architected features, optimize the operation method relating to the available SIMD of part of parallel work-flow in multiplier 1, optimization multiplier 2 and optimization adder and be optimized.Be introduced one by one below.

Optimize multiplier 1 and have two inputs output, optimize multiplier 1 schematic diagram see Fig. 7, in the step 3.1 of Optimized Coding, step 3.3, step 3.4 and step 4.1, involved matrix and multiplication of vectors computing all use and optimize multiplier 1.For step 3.1, the input optimizing multiplier 1 is the transposition of matrix A and vectorial S, and its specific implementation flow process is as follows:

1, judge whether the maximum number of lines reaching matrix A, if reach, then complete this operation; If do not reach, then carry out step 2.

2, the submatrix of the Z*Z in matrix A representated by first element is multiplied with the transposition of vectorial S.Because this submatrix is that the unit matrix of a Z*Z is through A _1,1(A _1,1the element of representing matrix A the first row first row) result behind secondary ring shift left position, be equivalent to carry out A to vectorial S so this submatrix is multiplied with the transposition of vectorial S _1,1secondary circulative shift operation.This operation can carry out SIMD optimization, and see Figure 10, concrete operations flow process is as follows:

2.1 calculate part 2 data length=(Z-A _1,1) (it is Z-A to modW _1,1to W delivery), and desired data initial value position=information vector s original position+A _1,1.

Desired data initial value position is risen by 2.2 the data copy of length is as the start position data of intermediate data;

2.3 couples of remaining (Z-A _1,1) a modW data carry out displacement copy, and " remainder " and " cover " in Figure 10 to be copied in output.In order to adapt to SIMD computing, input vector length is Z, and the large young pathbreaker of output vector is but in output vector, only have front Z element to be wherein valid data, and result data is stored in result vector register.

3, judge whether the maximum number of column reaching matrix A, if reach, then return step 1; If do not reach, then carry out step 4.

4, carry out the submatrix of the Z*Z in matrix A representated by next element to be multiplied with the transposition of vectorial S, concrete steps are with step 2.1,2.2,2.3, but transposition multiplied result does not need stored in result vector register, and perform step 5.

5, step 4 result of calculation be added with element in result vector register, two binary numbers are equivalent to two numbers and carry out xor operation, now can carry out SIMD optimization, and namely once-through operation can obtain W result, see Figure 11, and wherein (a ₁, a ₂..., a _w) represent step 4 result of calculation, (b ₁, b ₂..., b _w) representing element in result vector register, rectangle frame represents exclusive-OR operator, (y ₁, y ₂..., y _w) represent the result after computing, namely $(y_1,y_2,...,y_W)=(a_1\&CirclePlus;b_1,a_2\&CirclePlus;b_2,...,a_W\&CirclePlus;b_W),$ And be stored in result vector register, return step 3.

Optimize multiplier 2 and have two inputs output, optimize multiplier 2 schematic diagram see Fig. 8, matrix involved in the step 3.2 and step 4.3 of Optimized Coding and multiplication of vectors computing all use optimizes multiplier 2.Optimizing multiplier 2 is the special circumstances optimizing multiplier 1, and optimizing one of them input of multiplier 2 is matrix T ^-1, under different check matrix H, matrix matrix T ^-1the element in lower triangle is only had to be effective value.For step 3.2, the input optimizing multiplier 2 is matrix T _- ¹with the transposition of step 3.1 acquired results vector, its specific implementation flow process is as follows:

1, judge whether the maximum number of lines reaching matrix A, if reach, then complete this operation; If do not reach, then carry out step 2.

2, have can find out, matrix T ^-1upper triangle element is 0,

After the submatrix of the Z*Z representated by element " 0 " is multiplied with the transposition of step 3.1 acquired results vector in Fig. 4, result is still the latter, so to matrix T ^-1element " 0 " often in row is multiplied with the transposition of step 3.1 acquired results vector in Fig. 4, and according to the step 5 optimized in multiplier 1, is added by acquired results, returns step 1.

Optimize adder and have two inputs output, two inputs are vector, optimize adder schematic diagram see Figure 12, vector involved in the step 3.5 and step 4.2 of Optimized Coding and addition of vectors computing all use optimization adder.For step 3.5, the input optimizing adder is step 3.3 acquired results vector and step 3.4 acquired results vector, because input is binary number, two binary number additions equal two binary numbers and do xor operation, now SIMD optimization can be carried out, namely once-through operation can obtain W result, see Figure 11, and wherein (a ₁, a ₂..., a _w) represent step 3.3 acquired results vector, (b ₁, b ₂..., b _w) representing step 3.4 acquired results vector, rectangle frame represents exclusive-OR operator, (y ₁, y ₂..., y _w) represent the result after computing, namely $(y_1,y_2,...,y_W)=(a_1\&CirclePlus;b_1,a_2\&CirclePlus;b_2,...,a_W\&CirclePlus;b_W).$

The above-mentioned idiographic flow being LDPC coding method in the application.The interpretation method of the application to existing decoder is optimized, and optimizes interpretation method particular flow sheet see Figure 13.Before carrying out decoding, the external world need input code length L _lDPC, encoder bit rate R, coding after codeword vector c, maximum iteration time I and revise side-play amount β.Characteristic according to GPP chip framework is optimized as follows to LDPC interpretation method:

1, the operation method of SIMD is adopted to be optimized coding method, its essential concept is the effect processing to obtain parallel processing within a clock cycle of CPU to multiple data, and similarly is not common occupation mode---each clock cycle only carries out a data processing operation.Wherein will relate to used general processor once can deal with data amount size, and suppose that this size is K bit, the fundamental unit size of SIMD process is k, then once-through operation can deal with data amount

2, the part run optimized in interpretation method adopts the method for multithreading, with the line number of check matrix H for Thread Count, namely be a thread with the data line processed in check matrix H, perform the process operation of multiple thread at one time, and then the disposed of in its entirety performance of elevator system.

Below introduce the idiographic flow of interpretation method in the application, wherein, the general framework of interpretation method is identical with current interpretation method, specifically comprises: receive encoded LDPC code word signal c, determine check matrix H; Calculate variable node vector q as decode results by successive ignition, during each iteration, calculating temporary variable vector according to current variable node vector q and check-node vector r is and upgrade check-node vector r according to the vectorial t of temporary variable, then according to check-node vector r and temporary variable vector t renewal variable node vector q be the interpretation method difference with the prior art that the application provides is, the specific implementation in general processor is different.Concrete operation step is as follows:

1, according to 802.11n agreement, different code length L _lDPCand different coding code check R correspond to different check matrix H.First, according to code length L _lDPCand encoder bit rate R, extract corresponding check matrix H, parameters is carried out initialization, and it is stored in successively in linear search table, with the particular location of the method mark desired data of side-play amount, exchange computation complexity for internal memory, improve the data processing speed of LDPC code interpretation method:

1.1Z, in check matrix H namely, the size of submatrix representated by each element, is variable.As code length L _lDPCwhen=648, Z=27; As code length L _lDPCwhen=1296, Z=54; As code length L _lDPCwhen=1944, Z=81.

1.2LdpcRowNum, namely the line number of selected check matrix H, is variable.Work as code check time, LdpcRowNum=12; Work as code check time, LdpcRowNum=8; Work as code check time, LdpcRowNum=6; Work as code check time, LdpcRowNum=4.

1.3V _{ldpcRowLength}, namely often go the number of non-"-" element in selected check matrix H, the vector of to be length be 1*LdpcRowNum.

1.4LdpcBufferNum, namely storing register number needed for the selected each submatrix data of check matrix H, is variable.Its operational formula is

1.5LdpcRemain, i.e. one of variable needed for step 9 are variable.As code length L _lDPCwhen=648, LdpcRemain=11; As code length L _lDPCwhen=1296, LdpcRemain=6; As code length L _lDPCwhen=1944, LdpcRemain=1.

1.6LdpcRoundNum, i.e. one of variable needed for step 9 are variable.As code length L _lDPCwhen=648, LdpcRoundNum=27; As code length L _lDPCwhen=1296, LdpcRoundNum=22; As code length L _lDPCwhen=1944, LdpcRoundNum=17.

1.7V _{ldpcRowBuffer}, namely store selected check matrix H and often go register number needed for non-"-" data, the vector of to be length be 1*LdpcRowNum.Its operational formula is V _{ldpcRowBuffer}(v)=V _{ldpcRowLength}(v) * LdpcBufferNum (wherein V _{ldpcRowBuffer}v () represents v the element of vectorial LdpcRowBuffer, v correspond to the line number selecting check matrix H, as follows in like manner).

1.8M _ldpcOffset1, one of cycle offset namely calculated according to selected check matrix H, for step 4 and step 9, is LdpcRowNum*max (V _{ldpcRowLength}(v)) matrix (wherein max (V _{ldpcRowLength}(v)) represent amount of orientation V _{ldpcRowLength}the maximum of middle element, as follows in like manner).Its operational formula is (M _ldpcOffset1) _i,j=Z* (n-1)+H _i,n, wherein n represents the columns in selected check matrix H, and the position that the corresponding relation of j and n is selected check matrix H i-th row jth this check matrix H of non-"-" element place is that the i-th row n-th arranges, as follows in like manner.

1.9M _ldpcRound1, one of cycle-index namely calculated according to selected check matrix H, for step 4, is LdpcRowNum*max (V _{ldpcRowLength}(v)) matrix.Its operational formula is for work as H _i,n≠ 0 and H _i,n≠ '-' time, work as H _i,n=0 and H _i,n≠ '-' time, (M _ldpcRound1) _i,j=6.

1.10M _{ldpcAssemble1}, what namely calculate according to selected check matrix H supplies one of offset flag position, for step 4, is LdpcRowNum*max (V _{ldpcRowLength}(v)) matrix.Its operational formula is for work as H _i,n=0 and H _i,n≠ '-' time, (M _{ldpcAssemble1}) _i,j=0; Work as H _i,n≠ 0, H _i,n≠ '-' and (Z-H _i,n) modW=0 time, (M _{ldpcAssemble1}) _i,j=0; Work as H _i,n≠ 0, H _i,n≠ '-' and (Z-H _i,n) modW ≠ 0 time, (M _{ldpcAssemble1}) _i,j=1.

1.11M _{ldpcAssembleTable1}, namely calculate circulation according to selected check matrix H and supply side-play amount, for step 4 and step 9, for ( matrix (wherein for all elements in compute vector LdpcRowLength and),

1.12M _ldpcOffset2, one of cycle offset namely calculated according to selected check matrix H, for step 4 and step 9, is LdpcRowNum*max (V _{ldpcRowLength}(v)) matrix.Its operational formula is for working as (M _{ldpcAssemble1}) _i,jwhen=0, (M _ldpcOffset2) _i,j=Z* (n-1)+[W-Z+H _i,n+ (M _ldpcRound1) _i,j* W ^]; As (M _{ldpcAssemble1}) _i,jwhen=1, (M _ldpcOffset2) _i,j=Z* (n-1).

1.13M _ldpcRound2, one of cycle-index namely calculated according to selected check matrix H, for step 4, is LdpcRowNum*max (V _{ldpcRowLength}(v)) matrix.Its operational formula is

1.14M _ldpcRound3, one of cycle-index namely calculated according to selected check matrix H, for step 9, is LdpcRowNum*max (V _{ldpcRowLength}(v)) matrix.Its operational formula is for work as H _i,n≠ 0 and H _i,n≠ '-' time, work as H _i,n=0 and H _i,n≠ '-' time, (M _ldpcRound3) _i,j=5.

1.15M _{ldpcAssemble2}, what namely calculate according to selected check matrix H supplies one of offset flag position, for step 9, and same M _{ldpcAssemble1}.

1.16M _ldpcRound4, one of cycle-index namely calculated according to selected check matrix H, for step 9, is LdpcRowNum*max (V _{ldpcRowLength}(v)) matrix.Its operational formula is as i=0, (M _ldpcRound4) _i,j=0; When i ≠ 0,

2, judge whether to reach maximum iteration time I.If do not reach maximum iteration time I, then carry out step 3; If reach maximum iteration time I, then decoding terminates.

3, according to GPP chip characteristic, the method of multithreading is adopted to be optimized interpretation method, with the line number of check matrix H for Thread Count, data line wherein in check matrix H is that a thread process step 4 is to step 9, perform the process operation of multiple thread at one time, namely the same time carries out the process of multiple step 4 to step 9, and then the disposed of in its entirety performance of elevator system.Following step 4, to step 9, is the idiographic flow of single thread process.

4, calculate temporary variable vector t, to be length be for it vector.Wherein, this temporary variable vector comprises subvector corresponding to a line every with check matrix, and its call number is arrive this subvector comprises again and each non-"-" element H _i,jcorresponding subvector.(, only has non-"-" the element H in check matrix here _i,jhave corresponding subvector, "-" element in check matrix does not all have corresponding subvector in temporary variable vector, the vectorial r of check-node and variable node vector q.) particularly, with H _i,jthe computing formula of corresponding subvector t' is namely the value of temporary variable vector t subvector t' be in variable node vector q with element H _i,jcorresponding subvector q' according to after check matrix H i-th row jth column element value cyclic shift with check-node vector r in element H _i,jthe difference of corresponding subvector r'.If be now first time interative computation, variable node vector q is the codeword vector c after LDPC coding, and check-node vector r is initial condition, and now the computing formula of temporary variable vector t subvector t' is namely temporary variable vector t subvector t' is that variable node vector q subvector q' is according to result after check matrix H i-th row jth column element value cyclic shift.In order to adapt to SIMD computing, input variable knot vector q subvector q' and check-node vector r subvector r' length are Z, and exporting the large young pathbreaker of temporary variable vector t subvector t' is but in output subvector, only have front Z element to be wherein valid data.The computing of temporary variable vector t is often gone non-"-" element number with selected check matrix H and is circulated, and such as selected check matrix H i-th row jth non-"-" element will calculate the of temporary variable vector t arrive the element of position.Its concrete calculation procedure is as follows:

4.1 according to M _ldpcOffset1the cycle offset that selected check matrix H i-th row jth non-"-" element is corresponding is found out in matrix, the initial value position of desired data is found out, the cycle offset of the initial value position+correspondence of the initial value position=variable node vector q subvector q' of desired data in variable node vector q.

4.2 according to M _ldpcRound1matrix finds out cycle-index corresponding to selected check matrix H i-th row jth non-"-" element, by (M behind the initial value position of desired data _ldpcRound1) _i,j* W data copy in the current location of temporary variable vector t subvector t', and current location here refers to the original position of not yet copies data in subvector.

4.3 according to M _{ldpcAssemble1}matrix, judges whether to need to carry out padding operation.If (M _{ldpcAssemble1}) _i,j=1, then according to M _{ldpcAssembleTable1}side-play amount indicated in matrix carries out padding operation; If (M _{ldpcAssemble1}) _i,j=0, then do not need padding operation.Concrete padding operation comprises: determine matrix M _{ldpcAssemble1}in with check matrix element H _i,jthe value of each element in corresponding row and will with element H _i,jin the subvector of corresponding current vectorial q, call number is each element copy to successively and H _i,jin the current location of corresponding temporary variable vector t subvector; Wherein,

4.4 according to M _ldpcOffset2the cycle offset that selected check matrix H i-th row jth non-"-" element is corresponding is found out in matrix, the initial value position of desired data is found out, the cycle offset of the initial value position+correspondence of the initial value position=variable node vector q subvector q' of desired data in variable node vector q.

4.5 according to M _ldpcRound2matrix finds out cycle-index corresponding to selected check matrix H i-th row jth non-"-" element, by (M behind the initial value position of desired data _ldpcRound2) _i,j* W data copy in the current location of temporary variable vector t subvector t'.

If 4.6 now non-first time interative computations, then need to carry out temporary variable vector t subvector t'=temporary variable vector t subvector t'-check-node vector r subvector r' computing, being divided into W element by temporary variable vector t subvector t' and check-node vector r subvector r' all elements is one group, now SIMD optimization can be carried out, namely once-through operation can obtain the element in W temporary variable vector t, see Figure 11, wherein (a ₁, a ₂..., a _w) represent element in one group of temporary variable vector t, (b ₁, b ₂..., b _w) representing element in one group of check-node vector r, rectangle frame represents subtraction operator, (y ₁, y ₂..., y _w) represent the result after computing, i.e. (y ₁, y ₂..., y _w)=(a ₁-b ₁, a ₂-b ₂..., a _w-b _w); If be now first time interative computation, then carry out step 5.

5, the absolute value of all elements in temporary variable vector t subvector t' is calculated, and temporary variable vector after being designated as delivery | t|.Be divided into W element by temporary variable vector t subvector t' to be one group, now can to carry out SIMD optimization, namely once-through operation can obtain the element in W temporary variable vector t subvector t', see Figure 12, and wherein (c ₁, c ₂..., c _w) representing element in one group of temporary variable vector t subvector t', rectangle frame represents modulo operation device, (y ₁, y ₂..., y _w) represent temporary variable vector after delivery | t|, i.e. (y ₁, y ₂..., y _w)=(| c ₁|, | c ₂| ..., | c _w|).It can be used as the vector of the temporary variable after renewal t subvector t'.

6, be worth distributive operation most, and result be stored in value variable vector m matrix M.This process circulates with selected check matrix H line number, namely each to the V in temporary variable vector t _{ldpcRowLength}v () * W*LdpcBufferNum element operates, obtaining length is V _{ldpcRowLength}v the result of () * W*LdpcBufferNum is stored in value variable vector m.Once be worth most distributive operation schematic diagram see Figure 15, write as V by with the check matrix temporary variable vector t subvector t' that often row is corresponding _{ldpcRowLength}(v) row and the matrix T of row _v, wherein, matrix T _veach behavior temporary variable vector t subvector t' in element H _i,jcorresponding subvector, carries out cover when columns is inadequate; Most be worth distributive operation and compute matrix T _vin the minimum value of every column element and sub-minimum, distribute, and result be stored in value variable vector m subvector matrix M _v.Matrix T _voften row has LdpcBufferNum sub-block, has W base unit in each sub-block; Contrast the size of base unit in each row, draw minimum value wherein and sub-minimum, and record the line number of the place line number of this minimum value, i.e. index value; Variable vector m will be worth most according to index value to fill, if index value is different from the line number being worth most variable vector m, then insert the minimum value found out being worth most variable vector m, if index value is identical with the line number being worth most variable vector m, then insert the sub-minimum found out being worth most variable vector m.To find out the minimum value sub-minimum of a sub-block, its flow chart is see Figure 14, and concrete steps are as follows:

6.1 comparator matrix T _vthe size of the first row and corresponding base unit in first sub-block of the second row, by the line number of smaller value stored in index value, and smaller value is recorded as minimum value, higher value is recorded as sub-minimum, now SIMD optimization can be carried out, carry out twice computing, once get maximum, draw higher value between the two, once go minimum value, draw smaller value between the two, see Figure 11, wherein (a ₁, a ₂..., a _w) represent the element of the first row first sub-block, (b ₁, b ₂..., b _w) representing the element of the second row first sub-block, rectangle frame represents to be got maximum operation device or gets minimum operation device, (y ₁, y ₂..., y _w) represent the result after computing, i.e. (y ₁, y ₂..., y _w)=(max (a ₁, b ₁), max (a ₂, b ₂) ..., max (a _w, b _w)) or (y ₁, y ₂..., y _w)=(min (a ₁, b ₁), min (a ₂, b ₂) ..., min (a _w, b _w)).

6.2 judge whether to reach maximum cycle V _{ldpcRowLength}v (), if do not reach, then carry out step 6.3; If reach, then carry out step 6.6.

6.3 by matrix T _vnext line first sub-block and the minimum value of precedence record carry out getting maxima operation, this operation can carry out SIMD optimization, with step 6.1.

The sub-minimum of 6.4 results step 6.3 obtained and current record carries out getting minimum value and operates, and this operation can carry out SIMD optimization, with step 6.1, and result is designated as sub-minimum.

The minimum value of 6.5 results step 6.3 obtained and current record is carried out getting minimum value and is operated, and this operation can carry out SIMD optimization, with step 6.1, and result is designated as minimum value, the line number of this minimum value is recorded as index value simultaneously, returns step 6.2.

The minimum value of current record and sub-minimum are all deducted correction value β by 6.6, and this operation can carry out SIMD optimization, see Figure 11, and wherein (a ₁, a ₂..., a _w) represent the minimum value of precedence record or sub-minimum, (b ₁, b ₂..., b _w) represent correction value β also can be expressed as (β, β ..., β), rectangle frame represents subtraction operator, (y ₁, y ₂..., y _w) represent the result after computing, i.e. (y ₁, y ₂..., y _w)=(a ₁-β, a ₂-β ..., a _w-β), and be minimum value or sub-minimum by outcome record.

Minimum value and the sub-minimum of 6.7 pairs of current records are revised, and when the minimum value of current record or sub-minimum are less than zero, this value are set to zero, otherwise do not operate, and this operation can carry out SIMD optimization, see Figure 11, and wherein (a ₁, a ₂..., a _w) represent the minimum value of current record or sub-minimum, (b ₁, b ₂..., b _w) represent null value also can be expressed as (0,0 ..., 0), rectangle frame represents correction arithmetic unit, (y ₁, y ₂..., y _w) represent the result after computing, namely $y_i=\left\{\begin{array}{cc}\mathrm{if}\mathrm{}{a}_i<b_i,& a_i=0\\ \mathrm{else}& a_i=a_i\end{array}\right.,i=\mathrm{1,2},...,W,$ And be minimum value or sub-minimum by outcome record.

6.8 will be worth variable vector m most according to index value fills, if index value be worth most variable vector m subvector matrix M _vline number different, then in matrix M _vsame position insert the minimum value of current record, if index value be worth most variable vector m subvector matrix M _vline number identical, be then worth most variable vector m subvector matrix M _vsame position insert the sub-minimum of current record.By matrix M _vin element be worth variable vector m subvector most according to the formation that sequentially reads of row major.

7, intermediate variable vector s is calculated.This process circulates with selected check matrix H line number, namely each to the V in temporary variable vector t _{ldpcRowLength}v () * W*LdpcBufferNum element operates, obtaining length is V _{ldpcRowLength}v the result of () * W*LdpcBufferNum is stored in intermediate variable vector s.Temporary variable vector t, see Figure 17, is divided into V by an intermediate variable vector s computing schematic diagram _{ldpcRowLength}v () row, often row has LdpcBufferNum sub-block, has W base unit in each sub-block.To calculate the intermediate variable vector s of a sub-block, its flow chart is see Figure 16, and concrete operations flow process is as follows:

The first row first sub-block of temporary variable vector t and the second row first sub-block are carried out xor operation by 7.1, and this operation can carry out SIMD optimization, see Figure 11, and wherein (a ₁, a ₂..., a _w) represent the first row first sub-block, (b ₁, b ₂..., b _w) representing the second row first sub-block, rectangle frame represents exclusive-OR operator, (y ₁, y ₂..., y _w) represent the result after computing, namely $(y_1,y_2,...,y_W)=(a_1\&CirclePlus;b_1,a_2\&CirclePlus;b_2,...,a_W\&CirclePlus;b_W).$

7.2 judge whether to reach maximum cycle V _{ldpcRowLength}v (), if do not reach, then carry out step 7.3; If reach, then carry out step 7.4, and perform from the first row.

Temporary variable vector next line first sub-block of t and the result of step 7.1 are carried out xor operation by 7.3, and this operation can carry out SIMD optimization, see Figure 11, and wherein (a ₁, a ₂..., a _w) represent next line first sub-block, (b ₁, b ₂..., b _w) representing the result of step 7.1, rectangle frame represents exclusive-OR operator, (y ₁, y ₂..., y _w) represent the result after computing, namely $(y_1,y_2,...,y_W)=(a_1\&CirclePlus;b_1,a_2\&CirclePlus;b_2,...,a_W\&CirclePlus;b_W),$ Return step 7.2.

7.4 judge whether to reach maximum cycle V _{ldpcRowLength}v (), if do not reach, then carry out step 7.5; If reach, then carry out step 8.

Temporary variable vector current line first sub-block of t and the result of step 7.3 are carried out xor operation by 7.5, and this operation can carry out SIMD optimization.

7.6 by the result of step 7.5 with carry out or operate, this operation can carry out SIMD optimization, see Figure 11, and wherein (a ₁, a ₂..., a _w) represent the result of step 7.5, (b ₁, b ₂..., b _w) represent rectangle frame represents or arithmetic unit, (y ₁, y ₂..., y _w) represent the result after computing, i.e. (y ₁, y ₂..., y _w)=(a ₁| b ₁, a ₂| b ₂..., a _w| b _w), and by result stored in intermediate variable vector s the first sub-block in, return step 7.4.

8, calculation check knot vector r, to be length be for it vector.Wherein, this check-node vector comprises subvector corresponding to a line every with check matrix, and its call number is arrive this subvector comprises again and each non-"-" element H _i,jcorresponding subvector.The process of calculation check knot vector r circulates with selected check matrix H line number, namely each to the V in temporary variable vector t _{ldpcRowLength}v () * W*LdpcBufferNum element operates, obtaining length is V _{ldpcRowLength}v the result of () * W*LdpcBufferNum is stored in check-node vector r.When the calculation check matrix subvector that often row is corresponding calculates, with each non-"-" element H _i,jcorresponding subvector is that unit carries out, and calculating index is arrive vector in element.Below to calculate one and non-"-" element H _i,jcorresponding check-node vector r subvector r' is example, and its concrete operations flow process is as follows:

8.1 judge whether to reach maximum cycle V _{ldpcRowLength}v (), if do not reach, then carry out step 8.2; If reach, then carry out step 9.

8.2 will be worth variable vector m and H most _i,jcorresponding subvector and intermediate variable vector s and H _i,jcorresponding subvector carries out contrast operation, if intermediate variable vector s is less than zero, then result is the complement asked the value being worth most variable vector m, if intermediate variable vector s equals zero, then result is zero, if intermediate variable vector s is greater than zero, then result is to the value being worth most variable vector m.This operation can carry out SIMD optimization, see Figure 12, and wherein (a ₁, a ₂..., a _w) represent value variable vector m, (b ₁, b ₂..., b _w) representing intermediate variable vector s, rectangle frame represents contrast arithmetic unit, (y ₁, y ₂..., y _w) represent the result after computing, namely $y_i=\left\{\begin{array}{cc}\mathrm{if}{\mathrm{}b}_i<0,& a_i=\mathrm{NEG}\left(a_i\right)\\ f\mathrm{}{b}_i=0,& a_i=0\\ \mathrm{else}& a_i=a_i\end{array}\right.,i=\mathrm{1,2},...,W.$

The result of step 8.2 is added with intermediate variable vector s by 8.3.This operation can carry out SIMD optimization, see Figure 11, and wherein (a ₁, a ₂..., a _w) represent the result of step 8.2, (b ₁, b ₂..., b _w) representing intermediate variable vector s, rectangle frame represents adder calculator, (y ₁, y ₂..., y _w) represent the result after computing, i.e. (y ₁, y ₂..., y _w)=(a ₁+ b ₁, a ₂+ b ₂..., a _w+ b _w).

The result of step 8.3 and temporary variable vector t subvector t' are subtracted each other by 8.4.This operation can carry out SIMD optimization, see Figure 11, and wherein (a ₁, a ₂..., a _w) represent the result of step 8.3, (b ₁, b ₂..., b _w) representing temporary variable vector t, rectangle frame represents adder calculator, (y ₁, y ₂..., y _w) represent the result after computing, i.e. (y ₁, y ₂..., y _w)=(a ₁-b ₁, a ₂-b ₂..., a _w-b _w), and result is stored in check-node vector r, return step 8.1.

9, calculate variable node vector q, to be length be for it vector.Wherein, this variable node vector comprises subvector corresponding to a line every with check matrix, and its call number is arrive this subvector comprises again and each non-"-" element H _i,jcorresponding subvector q'.The computing formula of variable node vector q subvector q' is namely the value of variable node vector q subvector q' be temporary variable vector t subvector t' value with check-node vectorial r subvector r' value with, and according to the result after check matrix H i-th row jth column element value cyclic shift.In order to adapt to SIMD computing, input temporary variable vector t subvector t' and check-node vector r subvector r' length are Z, and the large young pathbreaker of output variable knot vector q subvector q' is but in output subvector, only have front Z element to be wherein valid data.The computing of variable node vector q is often gone non-"-" element number with selected check matrix H and is circulated, and such as selected check matrix H i-th row jth non-"-" element will calculate the of variable node vector q arrive the element of position.Its concrete calculation procedure is as follows:

9.1 according to M _ldpcOffset1the cycle offset that selected check matrix H i-th row jth non-"-" element is corresponding is found out in matrix, required original position is found out, the cycle offset of the initial value position+correspondence of required original position=variable node vector q subvector q' in variable node vector q.

Temporary variable vector t subvector t' is added with check-node vector r subvector r' by 9.2.This operation can carry out SIMD optimization, see Figure 11, and wherein (a ₁, a ₂..., a _w) represent temporary variable vector t, (b ₁, b ₂..., b _w) representing check-node vector r, rectangle frame represents adder calculator, (y ₁, y ₂..., y _w) represent the result after computing, i.e. (y ₁, y ₂..., y _w)=(a ₁+ b ₁, a ₂+ b ₂..., a _w+ b _w).

9.3 according to M _ldpcRound3matrix finds out cycle-index corresponding to selected check matrix H i-th row jth non-"-" element, by (M behind the initial value position of step 9.2 result data _ldpcRound1) _i,j* W data copy the required original position found out in step 9.1 to.

9.4 according to M _{ldpcAssemble2}matrix, judges whether to need to carry out padding operation.If (M _{ldpcAssemble2}) _i,j=1, then according to M _{ldpcAssembleTable1}side-play amount indicated in matrix carries out padding operation; If (M _{ldpcAssemble2}) _i,j=0, then do not need padding operation.

9.5 according to M _ldpcOffset2find out the cycle offset that selected check matrix H i-th row jth non-"-" element is corresponding in matrix, in variable node vector q, find out required original position, the cycle offset of the initial value position+correspondence of required original position=variable node vector q.

9.6 according to M _ldpcRound4matrix finds out cycle-index corresponding to selected check matrix H i-th row jth non-"-" element, by (M behind the initial value position of step 9.2 result data _ldpcRound4) _i,j* W data copy the required original position found out in step 9.5 to.

9.7 cover number needed for indicated by LdpcRemain, then according to M _{ldpcAssembleTable1}side-play amount indicated in matrix carries out complement operation to variable node vector q surplus element, returns step 2.

The above-mentioned LDPC coding&decoding method be in the application.

The coding and decoding theory of LDPC code is comparatively ripe, but because LDPC code is the linear block codes that a kind of code length n is larger, check matrix H is also larger, algorithm complex is very high, traditional LDPC coding and decoding mode is not well positioned to meet the throughput requirement of IEEE 802.11n system, has largely had influence on the performance of system.In existing high speed wireless access system, the realization of LDPC code is mostly based on fpga chip and dsp chip.Although can be met the requirement of process and time delay in Modern High-Speed protocol of wireless local area network by previous methods, FPGA programming and professional DSP all more complicated, lack abundant programmed environment and debugging acid, applicability is general.And based on GPP chip, developer can use common computer to use abundant instrument to develop, as C/C++ environment under the structure be familiar with and environment.The innovative point of this patent be exactly in GPP chip to the LDPC code in high speed wireless access system when using original coder, the characteristic according to GPP chip is optimized coding and decoding method.LDPC code due to IEEE802.11n is irregular LDPC codes, and the nonnegative value number that its check matrix prototype is often gone is not necessarily identical, so phase LDPC code Encoding Realization method than ever, the flexibility of GPP chip can have great advantage.In addition, consider the high speed development of CPU (Central Processing Unit, central processing unit), the data-handling capacity of GPP chip also can constantly promote.

First, SIMD instruction is adopted to realize the parallel processing of data.SIMD instruction set, Intel CPU adopted in this patent also can be called SSE (Streaming SIMD Extensions, instruction set) instruction set, its essential concept is the effect processing to obtain parallel processing within a clock cycle of CPU to multiple data, and similarly is not common occupation mode---each clock cycle only carries out a data processing operation.For the CPU of Nehalem framework, its process bit wide is 128 bits, for the CPU of Sandy Bridge framework, its process bit wide is 256 bits, namely for 8 bit fixed point numbers, the former can process 16 data within an instruction cycle, and the latter can process 32 data within an instruction cycle, theoretically, degree of parallelism be respectively 16 times parallel and 32 times walk abreast.But can be known by actual procedure simulation result, desirable parallel multiple often cannot be reached in the system operation of reality, one side is because of program and non-fully is made up of data manipulation flow process, further comprises a large amount of judgement statements, and these judge that statement cannot carry out parallel work-flow simultaneously.On the other hand, if adopt the SIMD instruction of 128 bit bit wides, for the check matrix of IEEE 802.11n standard, each submatrix size is not the multiple of 16, and therefore during last group data processing of each submatrix size, degree of parallelism is less than 16.

Secondly, by adopting the method for look-up table, namely initialization is carried out to multiple known parameter, and mark the particular location of desired data by the method for side-play amount, exchange computation complexity for internal memory, improve the data processing speed of LDPC code coding and decoding method.In LDPC code encoder, the block matrix needed for coding under different code check and code length condition can be calculated in advance, and be stored in LUTs (Look-Up-Table, look-up table), as long as table is read in when program brings into operation, without the need to double counting.

Finally, have employed the method for multithreading, perform more than one thread at one time, and then the disposed of in its entirety performance of elevator system.In LDPC co mpiler optimization code method, to the operation wherein in units of check matrix data line, be optimized by the method for multithreading, Thread Count is the line number of check matrix.

The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.

Claims (12)

1. based on a LDPC coding method for general processor, comprising: obtain signal vector S to be encoded by signals collecting or reception, determine check matrix H and matrix in block form A, B, D, E, F and T, and preserve; According to $\left\{\begin{array}{c}{p}_1^T=({\mathrm{ET}}^{-1}A+F)S^T\\ p_2^T=T^{-1}({\mathrm{AS}}^T+{\mathrm{Bp}}_1^T)\end{array}\right.$ Determine vectorial p ₁and p ₂, and obtain coding result vector c=(S, the p of LDPC ₁, p ₂); It is characterized in that, describedly determine vectorial p ₁and p ₂arbitrary matrix of Shi Jinhang comprises with the process that is multiplied of arbitrary vector:

Using every a line of described arbitrary matrix as a thread, carry out the corresponding line of this matrix and the multiplication operations of described arbitrary vector, and the multiplied result of all row is combined formation result vector;

Wherein, every a line of described arbitrary matrix comprises with the multiplication operations of described arbitrary vector: the original position+A determining vectorial original position=described arbitrary vector that each element j of current i-th row of matrix is corresponding _i,j+ (j-1) * Z, by described arbitrary vector from described original position Z-A _i,jthe data of length are shifted left by the mode of single-instruction multiple-data stream (SIMD) SIMD, and A before described original position is started _i,jafter data after the data of length move to and shift left, obtain the vector shift result that described element j is corresponding; Again by vector shift results added corresponding for each element, as the multiplied result of described every a line and described arbitrary vector;

In the mode of described SIMD, will from described original position Z-A _i,jthe data of length are divided in units of length W section is right segment data is parallel carries out operation of shifting left, then by remaining (Z-A _i,j) data of modW length carry out operation of shifting left;

Z is the submatrix size of an element representative in described check matrix.

2. method according to claim 1, is characterized in that, when described arbitrary matrix is T ^-1time, described T ^-1every a line and the multiplication operations of corresponding vector time, only carry out T ^-1value is being multiplied of element and the corresponding vector of 0, and obtaining this value is the vector shift result that 0 element is corresponding, and vector shift result corresponding for all the other elements is set to null vector; Again by vector shift results added corresponding for each element, as the multiplied result of described every a line and described arbitrary vector.

3. method according to claim 1 and 2, is characterized in that, shift left after operation to W segment data to get a front Z data be valid data simultaneously.

4. method according to claim 1 and 2, is characterized in that, describedly vector shift results added corresponding for each element is comprised: vector shift result corresponding for each element be divided in units of length W section, by SIMD couple segment data is parallel carries out phase add operation, then by remaining (Z-A _i,j) data of modW length carry out phase add operation.

5. method according to claim 1 and 2, is characterized in that, described matrix A, B, D, E, F and T ^-1preserved by linear search table.

6. based on a LDPC interpretation method for general processor, comprising: receive encoded LDPC code word signal c, determine check matrix H; Calculate variable node vector q as decode results by successive ignition, during each iteration, calculating temporary variable vector according to current variable node vector q and check-node vector r is and upgrade check-node vector r according to the vectorial t of described temporary variable, then according to check-node vector r and temporary variable vector t renewal variable node vector q be during first iteration, using character signal c as variable node vector q, verification knot vector r is set to 0; It is characterized in that,

When each iterative computation temporary variable vector t, check-node vector r and variable node vector q, carry out computing and renewal using every a line of check matrix as a thread, obtain with often to go in corresponding vectorial t, q and r call number from $\left[\underset{v=1}{\overset{i-1}{\mathrm{\&Sigma;}}}{V}_{\mathrm{LdpcRowLength}}\left(v\right)\right]\&times;Z$ Arrive $\left[\underset{v=1}{\overset{i-1}{\mathrm{\&Sigma;}}}{V}_{\mathrm{LdpcRowLength}}\left(v\right)\right]\&times;Z-1$ Subvector; Wherein, i is the line index of check matrix, when the i-th row of corresponding described check matrix calculates temporary variable vector t, check-node vector r and variable node vector subvector corresponding to q, according to each non-"-" element H of this row of check matrix _i,jwith element H in corresponding compute vector t, q and r _i,jcorresponding call number from $[j-1+\underset{v=1}{\overset{i-1}{\mathrm{\&Sigma;}}}{V}_{\mathrm{LdpcRowLength}}\left(v\right)]\&times;Z$ Arrive $[j+\underset{v=1}{\overset{i-1}{\mathrm{\&Sigma;}}}{V}_{\mathrm{LdpcRowLength}}\left(v\right)]\&times;Z-1$ Subvector, then carry out successively connecting and obtain and often go corresponding subvector, during i=1, order

Calculate and H _i,jthe mode of corresponding temporary variable vector t subvector is: determine H _i,jcorresponding vectorial original position Z* (n-1)+H _i,n, original position described in vectorial q subvector corresponding for the i-th row is played length is or the data of 6 are copied to and H by the mode of SIMD _i,jthe beginning of corresponding temporary variable vector t subvector; At H _i,n≠ 0, H _i,n≠ '-' and (Z-H _i,n) modW ≠ 0 time, determine matrix M _{ldpcAssemble1}in with check matrix element H _i,jthe value of each element in corresponding row and will with element H _i,jin the subvector of corresponding current vectorial q, call number is each element copy to successively and H _i,jin the current location of corresponding temporary variable vector t subvector; Determine each element H again _i,jcorresponding secondary vector original position M _ldpcOffset2, described secondary vector original position is played length is data copied to and H by the mode of SIMD _i,jin the current location of corresponding temporary variable vector t subvector; Get and H _i,jfront Z position in corresponding temporary variable vector t subvector and take absolute value as with H _i,jeffective subvector of corresponding temporary variable vector t;

Work as H _i,n≠ 0, H _i,n≠ '-' and (Z-H _i,n) modW ≠ 0 time, work as H _i,n=0 or H _i,n='-' or (Z-H _i,n) modW=0 time, (M _ldpcOffset2) _i,j=Z* (n-1); k is that general processor once can deal with data amount size, and k is the fundamental unit size of SIMD process; Code length L _lDPCwhen=648, LdpcRemain=11; As code length L _lDPCwhen=1296, LdpcRemain=6; As code length L _lDPCwhen=1944, LdpcRemain=1; J is the index of each non-"-" element in this row all non-"-" element in the i-th row, and n is the i-th row jth column index of non-"-" element in check matrix.

7. method according to claim 6, is characterized in that, calculates with the mode of the check-node vector r subvector that often row is corresponding of check matrix to be:

Write as V by with the check matrix temporary variable vector t subvector that often row is corresponding _{ldpcRowLength}(v) row and W* the matrix T of row _v, wherein, described matrix T _veach behavior described in temporary variable vector t subvector with element H _i,jcorresponding subvector, carries out cover when columns is inadequate;

To described matrix T _vbe worth most distribution, be worth variable vector m subvector matrix M most _v;

According to described matrix T _vcalculate intermediate variable vector s subvector matrix S _v;

According to described matrix M _vwith described matrix S _vthe element that middle index value is identical, determines an intermediary matrix R _v' in the element value of respective index value; Wherein, if matrix S _vin arbitrary element be less than 0, then get the complement of this arbitrary element and be added with this arbitrary element, using addition result as matrix R _v' in be worth the value of identical element with described arbitrary element index; If matrix S _vin arbitrary element equal 0, then this arbitrary element is added with 0, using addition result as matrix R _vin be worth the value of identical element with described arbitrary element index; If matrix S _vin arbitrary element >0, then in matrix M _vin get and be worth identical element with described arbitrary element index and be added with described arbitrary element, using addition result as matrix R _vin be worth the value of identical element with described arbitrary element index; Described operation of comparing and be added is undertaken by the mode of SIMD;

By SIMD mode by described matrix R _v' and matrix T _vthe element that middle index value is identical subtracts each other, using result as check-node vector r subvector matrix R _vthe element value of middle same index value; By described matrix R _vin front Z element of every row read the vectorial r subvector of composition check-node successively according to the mode of row major.

8. method according to claim 7, is characterized in that, described in be worth distribution most and comprise:

Described matrix T is determined by the mode of SIMD _vin minimum value of each row and sub-minimum and line index corresponding to minimum value; The minimum value obtained and sub-minimum are revised, all deducts default correction value β, when revised minimum value and sub-minimum are less than 0, are set to 0, otherwise remain unchanged;

According to described matrix T _vin the current minimum value of each row, sub-minimum and line index corresponding to minimum value, structure value variable vector m subvector matrix M _vthe row of middle same index, wherein, at M _varbitrary row in, be set to the element of the corresponding identical line index of current minimum value the minimum value determined, all the other elements be set to sub-minimum.

9. method according to claim 8, is characterized in that, the described mode by SIMD determines that the mode of each minimum value arranged and sub-minimum and corresponding line index comprises:

By described matrix T _veach row element be divided into individual sub-block, each sub-block comprises W base unit; In more described matrix T _vin the element of any two row time, compare W base unit by the mode of SIMD is disposable.

10. method according to claim 7, is characterized in that, described calculating intermediate variable vector s subvector matrix S _vcomprise:

For matrix T _vin each row, this row all elements is carried out xor operation, then by result and i-th ' row element XOR after to carry out with 0x7f or operate, general or operating result are as intermediate vector matrix S _vmiddle same index row i-th ' row element; Wherein, by described matrix T _veach row element be divided into individual sub-block, each sub-block comprises W base unit, when carrying out XOR/or operation, by XOR/or the operation of the disposable execution W base unit of the mode of SIMD.

11. methods according to claim 6, is characterized in that, calculate and H _i,jcorresponding variable node vector q subvector comprises:

Determine H _i,jcorresponding vectorial original position Z* (n-1)+H _i,n, by SIMD mode by H _i,jcorresponding temporary variable vector t subvector and H _i,jcorresponding check-node vector r subvector is added, and original position described in result vector is played length is or the data of 5 are copied to and H by the mode of SIMD _i,jthe beginning of corresponding variable node vector q subvector; At H _i,n≠ 0, H _i,n≠ '-' and (Z-H _i,n) modW ≠ 0 time, determine matrix M _{ldpcAssemble1}in with check matrix element H _i,jthe value of each element in corresponding row and will with element H _i,jin the subvector of corresponding current vectorial q, call number is each element copy to successively and H _i,jin the current location of corresponding variable node vector q subvector;

Determine each element H _i,jcorresponding secondary vector original position M _ldpcOffset2, described secondary vector original position is risen length be 0 or data copied to and H by the mode of SIMD _i,jin the current location of corresponding variable node vector q subvector;

According to the cover number of LdpcRemain instruction, according to M _{ldpcAssemble1}in with check matrix element H _i,jin corresponding row, the value of element carries out cover.

12., according to described method arbitrary in claim 6 to 11, is characterized in that, precalculate and preserve each element H _i,jcorresponding vectorial original position Z* (n-1)+H _i,nwith secondary vector original position M _ldpcOffset2, matrix M _{ldpcAssemble1}, the vectorial V that forms of the number of often going non-"-" element in check matrix _{ldpcRowLength}, M _{ldpcAssemble1}, LdpcRemain.