CN101047371A - Full digital sliding pulse signal generator - Google Patents
Full digital sliding pulse signal generator Download PDFInfo
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- CN101047371A CN101047371A CNA2007100486664A CN200710048666A CN101047371A CN 101047371 A CN101047371 A CN 101047371A CN A2007100486664 A CNA2007100486664 A CN A2007100486664A CN 200710048666 A CN200710048666 A CN 200710048666A CN 101047371 A CN101047371 A CN 101047371A
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Abstract
A slip pulse signal generator of digital type is prepared as using pulse frequency generating circuit to provide clock reference for whole system, using MCU control unit to set all parameters for whole system, using EPGA control unit to control step amplitude generating circuit based on reference of said clock, using internal time sequence module of FPGA control unit to generate control signal for controlling pulse generating circuit to generate pulse signal and realizing design of maximum pulse amplitude control circuit by FPGA control unit in order to achieve purpose of controlling slip signal maximum amplitude.
Description
Technical field
The present invention is the signal source of a kind of amplitude/frequency spectrum (as nuclear spectrum) analytical instrument special use, and it can export maximum impulse variable-magnitude, changeable frequency, the variable burst pulse sequence of pulse duration.Be specifically designed to the key technical indexes such as differential linearity, integral linearity, road drift of calibration multichannel pulse scope-analyzer, also can test the wide and threshold drift in threshold value linearity, the road of single channel pulse height analyzer etc.In addition, this instrument can also use as the standard frequency pulse generator.
Background technology
The present invention is according to the needs of practical application, and the energy spectrometer that is primarily aimed in the nuclear technology is developed design.The slippage signal that produces can detect the nuclear spectrum measurement instrument, to check its performance quality.
In view of also not occurring this series products in the market, some also just rests on the technical merit stage in the early time, mainly uses discrete component to form, and precision is lower, parameter area is narrower, and uses inconvenience, can not satisfy the needs of current application.And the present invention has adopted present more advanced computer technology, utilize the high speed of microprocessor, data processing and control ability produce the pulse signal of total control easily, the parameters index all is greatly improved, man-machine control is convenient, directly perceived, can be applied to the many fields that comprise nuclear technology well
Summary of the invention
The objective of the invention is to produce maximum impulse variable-magnitude, changeable frequency, the variable sliding pulse of pulse duration.The slippage signal that its produces has high accuracy, high stability, and the total digitalization operation, have simultaneously in light weight, volume is little, the reliability advantages of higher.
The present invention is achieved in that
The present invention has adopted the technical method based on the full digital sliding pulse signal generator of multiprocessor (FPGA+MCU) technology, instrument by frequency generating circuit 1, ladder amplitude produce circuit 2, pulse-generating circuit 3, maximum output swing control circuit 4, FPGA control system 5, MCU control system 6 totally six parts form.Pulse frequency produces circuit 1 and provides clock reference for whole system, FPGA control system 5 clock benchmark is at this moment controlled ladder amplitude generation circuit 2 down, output amplitude increases progressively the ladder range signal of (successively decreasing), inside tfi module by FPGA control system 5 produces control signal simultaneously, control impuls produces circuit 3 and produces pulse signal, at last by the design of FPGA realization to maximum impulse amplitude control circuit 4, to reach the controlled purpose of slippage signal amplitude peak, the setting of all parameters all realizes by MCU control system 6 and finishes.
Whole instrument has adopted FPGA control system 6 and MCU control system 5 to jointly control mechanism, realize the intelligent parameters that the slippage instrument is set by MCU control system 5, finish by communication protocol simultaneously and FPGA control system 6 between transmission, and the operation of control whole system, FPGA control system 6 is utilized the characteristics of its high-speed parallel, finish the specific implementation of each functional module in the system, alleviated the work load of MCU, also guaranteed the precision of instrument.
The ladder amplitude produces circuit 2 and has adopted the DAC chip under the control of FPGA control system 5 reference voltage source to be carried out the dividing potential drop realization, the DAC chip adopts 14 interpolation formula digital to analog converters, conversion is fast settling time, the ladder number of the relative slippage signal of figure place is more, helps improving the performance of whole slippage signal.
Pulse-generating circuit 3 has adopted high-speed analog switch, and it carries out turn-on and turn-off under the control of FPGA control system 6, and the stairstep signal that the ladder amplitude is produced circuit 2 outputs is sampled, and pulse duration is controlled realization by the FPGA internal counter.Advantages such as high-speed analog switch has conducting, turn-offs weak point settling time, and conducting resistance is low.
Maximum impulse amplitude control circuit 4 is made up of 0P operational amplifier, precision resistance network, analog switch etc., and the gating by analog switch in the FPGA control system 6 controlling resistance networks is to realize the different multiplication factor of operational amplifier.
Sliding pulse signal generator of the present invention, the implementation method that adopted FPGA to combine with the MCU multiprocessor by both sharing out the work and help one another, has realized the index request of whole system bandwidth (20MHz), high accuracy, high stability.
Description of drawings:
Fig. 1 is a structured flowchart of the present invention.
Fig. 2 is frequency generating circuit 1 structured flowchart.
Fig. 3 produces circuit 2 structured flowcharts for the ladder amplitude.
Fig. 4 is pulse-generating circuit 3 structured flowcharts.
Fig. 5 is maximum output swing control circuit 4 structured flowcharts.
Fig. 6 is MCU and FPGA interface circuit figure
Fig. 7 is frequency generating circuit 1 practical circuit diagram
Fig. 8 produces circuit diagram for the ladder amplitude pulses
Fig. 9 is maximum output swing control circuit 4 practical circuit diagram
Embodiment
1, whole instrument has adopted FPGA control system 6 and MCU control system 5 to jointly control mechanism, realize the intelligent parameters that the slippage instrument is set by MCU control system 5, finish by communication protocol simultaneously and FPGA control system 6 between transmission, and the operation of control whole system, FPGA control system 6 is utilized the characteristics of its high-speed parallel, finish the specific implementation of each functional module in the system, alleviated the work load of MCU, also guaranteed the precision of instrument.As shown in Figure 6.
2, frequency generating circuit 1
Frequency generating circuit theory diagram such as Fig. 2 produce the 20MHz clock signal by active crystal oscillator, send into FPGA control system 6, through its inner phase-locked loop (PLL) module frequency multiplication to 100MHz.Simultaneously, FPGA control system 6 produces the clock signal of whole system each several part under the control of MCU control system 5, comprises that the ladder amplitude produces the reference clock of Direct Digital frequency synthesis (DDS) chip in circuit 2, the frequency generating circuit 1.This frequency producing method has been given up traditional phase-locked loop circuit design, but adopts the DDS chip, and circuit structure is simple, realizes having guaranteed the high stability of frequency simultaneously, the precision height than being easier to.
The signal frequency of frequency reference output can be given by following formula:
In the formula: f
CpBe system clock frequency, Δ F is a signal frequency resolution, F
OBe output signal frequency, M is a frequency control word.By the value of setpoint frequency control word and system clock, just can produce the output of required frequency signal.
The side circuit of frequency generating circuit 1 correspondence as shown in Figure 7, this circuit has adopted the AD9850 chip, AD9850 output two complementary current IOUT, IOUTB send into internal comparator by the VINP pin behind resistance sampling, utilize its inner high-speed comparator directly to export square wave, shake less.AD9850 full scale output current (Full Scale Current) is regulated by an outer meeting resistance RSET, and regulating the pass is I
OUT=32 * (1.248V/R
SET), R
SETRepresentative value be 3.9k Ω.FPGA and AD9850 adopt the parallel interface mode here, as DDS_D0～DDS_D7 among Fig. 6.AD9850 output signal frequency (MHz of unit) is:
F
out＝(ΔPhase×CLKIN)/2
32
Δ Phase=32 position phase control words wherein, CLKIN=input reference clock (MHz of unit).
3, the ladder amplitude produces circuit 2
Be illustrated in figure 3 as the theory diagram that the ladder amplitude produces circuit, improve reference voltage for the DAC chip by reference voltage base, FPGA control system 6 is under the control of the frequency reference of frequency generating circuit 1 output and MCU control system 5, write the amplitude control word to the DAC chip, to realize that DAC chip output amplitude increases progressively the signal of (successively decreasing), handle output ladder range signal again through the OP operational amplifier.
The specific implementation circuit adopts the AD9774 chip as shown in Figure 8, and it is 14, current-output type DAC, and the present invention has only utilized it high 10, low 4 need not, purpose is to improve the linearity of AD9774.The AD9774 output current is: I
OUTA=(N/16383) * I
OUTFS, and I
OUTFS=(32 * V
REF)/R
SET=(32 * 1.2)/1.91k=20mA, promptly the full scale electric current is 20mA.N is the digital quantity of input in the formula, and the electric current output that the digital quantity of change input just can obtain varying in size converts voltage to through the OPA642 operational amplifier.Output current relational expression by above AD9774 is known: the maximum output voltage through amplifier OPA642 is approximately V
OUT=I
OUTA* 50=1V.
4, pulse-generating circuit 3
The pulse-generating circuit theory diagram as shown in Figure 4, its design philosophy has been to adopt high-speed analog switch under the control of microcontroller the ladder range signal that the ladder amplitude produces circuit 2 outputs to be sampled.FPGA control system 6 is under the control of the frequency reference of frequency generating circuit 1 output and MCU control system 5, produce the trigger impulse of high-speed analog switch, to control its break-make, utilize the FPGA internal counter to control the time of high-speed analog switch conducting and shutoff simultaneously, i.e. the width of control wave.This design philosophy adds the high-speed analog switch conducting, turn-offs short advantage settling time owing to utilized FPGA high speed, parallel, makes that the porch of exporting is very precipitous, and the stability of signal is also high.
Side circuit adopts the high performance analog switch MAX4715 of MAXIM company as shown in Figure 8, has conducting, turn-offing settling time, short (switch conduction is T settling time to the maximum
On=18ns, switch turn-off and are T settling time to the maximum
Off=12ns), low (the switch conduction resistance R of conducting resistance
On=1.2 Ω (+1.8V power supply), 0.4 Ω (+3V power supply)) advantage such as.
5, the maximum output swing control circuit 4
Fig. 5 is the theory diagram of maximum output swing control circuit, and its design philosophy is the open-loop gain A that changes operational amplifier by the ratio of the two arm resistance values that change the OP operational amplifier
0Thereby, by V
Out=A
0* V
InObtain the signal output of changes in amplitude.Its process is that FPGA control system 6 is under the control of MCU control system 5, realize the turn-on and turn-off of analog switch, the turn-on and turn-off of analog switch have changed the equiva lent impedance of precision resistance network, thereby changed the open-loop gain Ao of OP operational amplifier, realized the purpose of maximum output swing control.
Its physical circuit realizes as shown in Figure 9, the precision resistance network using error be millesimal resistance, add 4 analog switches, cooperate the OP operational amplifier to realize amplifying.Analog switch adopts the MAX312 chip of MAXIM company as analog switch, the low (R of its conducting resistance
On=10 Ω), and a chip comprises 4 groups of analog switches (SPST), saved the area of circuit board, also reduced interference each other.The OP operational amplifier adopts OPA642.
By circuit as can be known the OPA642 multiplication factor be: A
0=1+Rf/R1, R1=10k here, preceding step voltage is input as 1V.So:
When Rf=0, A
0=1, output voltage V
Out=1V;
When Rf=1k, A
0=1.1, output voltage V
Out=1.1V;
When Rf=2k, A
0=1.2, output voltage V
Out=1.2V;
…
When Rf=10k, A
0=2.0, output voltage V
Out=2.0V;
Known by last calculating: the maximum impulse amplitude is 1.0V-2.0V, stepping 0.1V.
The utilization effect
In sum, all design philosophys of the present invention are fine has realized every index request of whole system, and because it has adopted advanced technology, cooperate perfect mentality of designing, finally make the digitlization sliding pulse signal generator on frequency, have broadband, high accuracy, high stability, precision height on amplitude, and the technology of total digitalization have won user's consistent favorable comment.
Claims (6)
1, the present invention relates to a kind of technical method of the full digital sliding pulse signal generator based on multiprocessor (FPGA+MCU) technology, instrument by frequency generating circuit 1, ladder amplitude produce circuit 2, pulse-generating circuit 3, maximum output swing control circuit 4, FPGA control system 5, MCU control system 6 totally six parts form.Pulse frequency produces circuit 1 and provides clock reference for whole system, FPGA control system 5 clock benchmark is at this moment controlled ladder amplitude generation circuit 2 down, output amplitude increases progressively the ladder range signal of (successively decreasing), inside tfi module by FPGA control system 5 produces control signal simultaneously, control impuls produces circuit 3 and produces pulse signal, at last by the design of FPGA realization to maximum impulse amplitude control circuit 4, to reach the controlled purpose of slippage signal amplitude peak, the setting of all parameters all realizes by MCU control system 6 and finishes.
2, according to claim 1, it is characterized in that whole instrument has adopted FPGA control system 6 and MCU control system 5 to jointly control mechanism, realize the intelligent parameters that the slippage instrument is set by MCU control system 5, finish by communication protocol simultaneously and FPGA control system 6 between transmission, and the operation of control whole system, FPGA control system 6 is utilized the characteristics of its high-speed parallel, finish the specific implementation of each functional module in the system, alleviate the work load of MCU, also guaranteed the precision of instrument.
3, according to claim 1, it is characterized in that frequency generating circuit 1 is mainly by active crystal oscillator, DDS chip and peripheral circuit thereof, the inner frequency multiplication of phase locked loop module of FPGA three parts such as (PLL) are formed, active crystal oscillator produces the square wave (duty ratio 50%) of 20MHz, through the inner PLL frequency multiplication of FPGA to 100MHz, reference clock as the DDS chip, the DDS chip is under the effect of FPGA control system 6, for the instrument each several part produces high-quality clock signal, the DDS chip of employing has low-power consumption, chip integration becomes high-speed comparator, advantages such as good dynamic characteristics.
4, according to claim 1, it is characterized in that the ladder amplitude produces circuit 2 and adopted the DAC chip under the control of FPGA control system 5 reference voltage source to be carried out the dividing potential drop realization, the DAC chip adopts 14 interpolation formula digital to analog converters, conversion is fast settling time, the ladder number of the relative slippage signal of figure place is more, helps improving the performance of whole slippage signal.
5, according to claim 1, it is characterized in that pulse-generating circuit 3 has adopted high-speed analog switch, it carries out turn-on and turn-off under the control of FPGA control system 6, the stairstep signal that the ladder amplitude is produced circuit 2 outputs is sampled, and pulse duration is controlled realization by the FPGA internal counter.Advantages such as high-speed analog switch has conducting, turn-offs weak point settling time, and conducting resistance is low.
6, according to claim 1, it is characterized in that maximum impulse amplitude control circuit 4 is made up of OP operational amplifier, precision resistance network, analog switch etc., the gating by analog switch in the FPGA control system 6 controlling resistance networks is to realize the different multiplication factor of operational amplifier.
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| CN200710048666A CN100578933C (en) | 2007-03-19 | 2007-03-19 | Full digital sliding pulse signal generator |
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| CN102130688A (en) * | 2010-01-20 | 2011-07-20 | 上海华虹Nec电子有限公司 | Resistance network type digital to analog converter structure |
| CN102193106A (en) * | 2010-03-18 | 2011-09-21 | 长江大学 | Method for generating frequency sweeping signal special for controllable seismic source |
| CN102468847A (en) * | 2010-11-03 | 2012-05-23 | 北京普源精电科技有限公司 | Square wave output method and device |
| CN102035507B (en) * | 2009-09-30 | 2013-01-02 | 联咏科技股份有限公司 | Frequency generation device |
| CN103078612A (en) * | 2012-12-31 | 2013-05-01 | 西安奇维科技股份有限公司 | Method for generating pulse signal by using analog switch |
| CN103176503A (en) * | 2011-12-21 | 2013-06-26 | 北京普源精电科技有限公司 | Digital display scope (DDS) signal generator and amplitude control method thereof |
| CN103248356A (en) * | 2013-05-20 | 2013-08-14 | 上海理工大学 | Counter based on phase-lock loop pulse interpolation technology and realization method |
| CN104467748A (en) * | 2014-11-11 | 2015-03-25 | 绵阳市维博电子有限责任公司 | Fast edge pulse generator based on optoelectronic isolation |
| CN107834354A (en) * | 2017-10-26 | 2018-03-23 | 山东海富光子科技股份有限公司 | A kind of signal generator applied to high-peak power laser |
| CN109085395A (en) * | 2018-07-24 | 2018-12-25 | 中国兵器装备集团自动化研究所 | A kind of high pressure is fastly along negative pulse generating device |
| CN110212892A (en) * | 2019-06-06 | 2019-09-06 | 国网福建省电力有限公司电力科学研究院 | A kind of high-precision electric energy meter variable thresholding integral differential pulse generation method |
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| CN102035507B (en) * | 2009-09-30 | 2013-01-02 | 联咏科技股份有限公司 | Frequency generation device |
| CN102130688B (en) * | 2010-01-20 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | Resistance network type digital to analog converter structure |
| CN102130688A (en) * | 2010-01-20 | 2011-07-20 | 上海华虹Nec电子有限公司 | Resistance network type digital to analog converter structure |
| CN102193106A (en) * | 2010-03-18 | 2011-09-21 | 长江大学 | Method for generating frequency sweeping signal special for controllable seismic source |
| CN102468847A (en) * | 2010-11-03 | 2012-05-23 | 北京普源精电科技有限公司 | Square wave output method and device |
| CN102468847B (en) * | 2010-11-03 | 2016-04-06 | 北京普源精电科技有限公司 | The output intent of square wave and device |
| CN103176503A (en) * | 2011-12-21 | 2013-06-26 | 北京普源精电科技有限公司 | Digital display scope (DDS) signal generator and amplitude control method thereof |
| CN103176503B (en) * | 2011-12-21 | 2017-08-25 | 北京普源精电科技有限公司 | A kind of DDS signal generator and its amplitude control method |
| CN103078612A (en) * | 2012-12-31 | 2013-05-01 | 西安奇维科技股份有限公司 | Method for generating pulse signal by using analog switch |
| CN103248356B (en) * | 2013-05-20 | 2016-01-20 | 上海理工大学 | A kind of counter and implementation method based on adopting phase-locked loop pulse interpolation technology |
| CN103248356A (en) * | 2013-05-20 | 2013-08-14 | 上海理工大学 | Counter based on phase-lock loop pulse interpolation technology and realization method |
| CN104467748A (en) * | 2014-11-11 | 2015-03-25 | 绵阳市维博电子有限责任公司 | Fast edge pulse generator based on optoelectronic isolation |
| CN107834354A (en) * | 2017-10-26 | 2018-03-23 | 山东海富光子科技股份有限公司 | A kind of signal generator applied to high-peak power laser |
| CN109085395A (en) * | 2018-07-24 | 2018-12-25 | 中国兵器装备集团自动化研究所 | A kind of high pressure is fastly along negative pulse generating device |
| CN110212892A (en) * | 2019-06-06 | 2019-09-06 | 国网福建省电力有限公司电力科学研究院 | A kind of high-precision electric energy meter variable thresholding integral differential pulse generation method |
| CN110212892B (en) * | 2019-06-06 | 2022-10-04 | 国网福建省电力有限公司电力科学研究院 | High-precision electric energy meter variable threshold value integral differential pulse generation method |
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