CN101040255A - 用于控制处理器与外设之间的通信的控制器和方法 - Google Patents
用于控制处理器与外设之间的通信的控制器和方法 Download PDFInfo
- Publication number
- CN101040255A CN101040255A CNA2005800333600A CN200580033360A CN101040255A CN 101040255 A CN101040255 A CN 101040255A CN A2005800333600 A CNA2005800333600 A CN A2005800333600A CN 200580033360 A CN200580033360 A CN 200580033360A CN 101040255 A CN101040255 A CN 101040255A
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- memory
- memory bank
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- peripheral hardware
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 230000002093 peripheral effect Effects 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims description 7
- 238000004891 communication Methods 0.000 title abstract description 5
- 239000000872 buffer Substances 0.000 claims abstract description 48
- 238000012545 processing Methods 0.000 claims abstract description 19
- 238000013507 mapping Methods 0.000 abstract description 4
- 230000003139 buffering effect Effects 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000000284 extract Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
- G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/383—Operand prefetching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Multimedia (AREA)
- Computer Hardware Design (AREA)
- Information Transfer Systems (AREA)
- Advance Control (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Multi Processors (AREA)
- Executing Machine-Instructions (AREA)
Abstract
Description
Claims (5)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04103727 | 2004-08-03 | ||
EP04103727.6 | 2004-08-03 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101040255A true CN101040255A (zh) | 2007-09-19 |
CN100533371C CN100533371C (zh) | 2009-08-26 |
Family
ID=35169523
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2005800333600A Expired - Fee Related CN100533371C (zh) | 2004-08-03 | 2005-07-22 | 用于控制处理器与外设之间的通信的控制器和方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US8099533B2 (zh) |
EP (1) | EP1776632B1 (zh) |
JP (1) | JP2008509470A (zh) |
CN (1) | CN100533371C (zh) |
AT (1) | ATE550720T1 (zh) |
WO (1) | WO2006016298A1 (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105760317A (zh) * | 2014-11-07 | 2016-07-13 | 联发科技股份有限公司 | 数据写***和用于核心处理器的数据写方法 |
CN109154916A (zh) * | 2016-08-22 | 2019-01-04 | 惠普发展公司,有限责任合伙企业 | 连接的设备的信息 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0732659B1 (en) * | 1995-03-17 | 2001-08-08 | LSI Logic Corporation | Controlling (n+i) I/O channels with (n) data managers in a homogeneous software programming environment |
US5907702A (en) * | 1997-03-28 | 1999-05-25 | International Business Machines Corporation | Method and apparatus for decreasing thread switch latency in a multithread processor |
WO2001038970A2 (en) | 1999-11-22 | 2001-05-31 | Ericsson Inc | Buffer memories, methods and systems for buffering having seperate buffer memories for each of a plurality of tasks |
US6988122B2 (en) * | 2001-01-09 | 2006-01-17 | International Business Machines Corporation | Ferris-wheel queue |
US7145913B2 (en) * | 2001-02-15 | 2006-12-05 | The Board Of Trustees Of The University Of Illinois | Thread based scalable routing for an active router |
US6845501B2 (en) * | 2001-07-27 | 2005-01-18 | Hewlett-Packard Development Company, L.P. | Method and apparatus for enabling a compiler to reduce cache misses by performing pre-fetches in the event of context switch |
US7136991B2 (en) | 2001-11-20 | 2006-11-14 | Henry G Glenn | Microprocessor including random number generator supporting operating system-independent multitasking operation |
US7113985B2 (en) * | 2002-10-15 | 2006-09-26 | Intel Corporation | Allocating singles and bursts from a freelist |
US7143267B2 (en) * | 2003-04-28 | 2006-11-28 | International Business Machines Corporation | Partitioning prefetch registers to prevent at least in part inconsistent prefetch information from being stored in a prefetch register of a multithreading processor |
-
2005
- 2005-07-22 WO PCT/IB2005/052477 patent/WO2006016298A1/en active Application Filing
- 2005-07-22 US US11/573,194 patent/US8099533B2/en active Active
- 2005-07-22 EP EP05774328A patent/EP1776632B1/en active Active
- 2005-07-22 JP JP2007524442A patent/JP2008509470A/ja not_active Withdrawn
- 2005-07-22 AT AT05774328T patent/ATE550720T1/de active
- 2005-07-22 CN CNB2005800333600A patent/CN100533371C/zh not_active Expired - Fee Related
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105760317A (zh) * | 2014-11-07 | 2016-07-13 | 联发科技股份有限公司 | 数据写***和用于核心处理器的数据写方法 |
CN105760317B (zh) * | 2014-11-07 | 2018-10-16 | 联发科技股份有限公司 | 数据写***和用于核心处理器的数据写方法 |
CN109154916A (zh) * | 2016-08-22 | 2019-01-04 | 惠普发展公司,有限责任合伙企业 | 连接的设备的信息 |
Also Published As
Publication number | Publication date |
---|---|
EP1776632B1 (en) | 2012-03-21 |
CN100533371C (zh) | 2009-08-26 |
US8099533B2 (en) | 2012-01-17 |
ATE550720T1 (de) | 2012-04-15 |
EP1776632A1 (en) | 2007-04-25 |
JP2008509470A (ja) | 2008-03-27 |
US20110099304A1 (en) | 2011-04-28 |
WO2006016298A1 (en) | 2006-02-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: NXP CO., LTD. Free format text: FORMER OWNER: KONINKLIJKE PHILIPS ELECTRONICS N.V. Effective date: 20080404 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20080404 Address after: Holland Ian Deho Finn Applicant after: Koninkl Philips Electronics NV Address before: Holland Ian Deho Finn Applicant before: Koninklijke Philips Electronics N.V. |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090826 Termination date: 20130722 |