ATE550720T1 - System, controller und verfahren zur steuerung der kommunikation zwischen einem prozessor und einer externen peripherievorrichtung - Google Patents

System, controller und verfahren zur steuerung der kommunikation zwischen einem prozessor und einer externen peripherievorrichtung

Info

Publication number
ATE550720T1
ATE550720T1 AT05774328T AT05774328T ATE550720T1 AT E550720 T1 ATE550720 T1 AT E550720T1 AT 05774328 T AT05774328 T AT 05774328T AT 05774328 T AT05774328 T AT 05774328T AT E550720 T1 ATE550720 T1 AT E550720T1
Authority
AT
Austria
Prior art keywords
processor
peripheral device
addr
controller unit
controller
Prior art date
Application number
AT05774328T
Other languages
English (en)
Inventor
Chee Ng
Nitin Kabra
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE550720T1 publication Critical patent/ATE550720T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Multimedia (AREA)
  • Information Transfer Systems (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AT05774328T 2004-08-03 2005-07-22 System, controller und verfahren zur steuerung der kommunikation zwischen einem prozessor und einer externen peripherievorrichtung ATE550720T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP04103727 2004-08-03
PCT/IB2005/052477 WO2006016298A1 (en) 2004-08-03 2005-07-22 Controller and a method of for controlling the communication between a processor and an external peripheral device

Publications (1)

Publication Number Publication Date
ATE550720T1 true ATE550720T1 (de) 2012-04-15

Family

ID=35169523

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05774328T ATE550720T1 (de) 2004-08-03 2005-07-22 System, controller und verfahren zur steuerung der kommunikation zwischen einem prozessor und einer externen peripherievorrichtung

Country Status (6)

Country Link
US (1) US8099533B2 (de)
EP (1) EP1776632B1 (de)
JP (1) JP2008509470A (de)
CN (1) CN100533371C (de)
AT (1) ATE550720T1 (de)
WO (1) WO2006016298A1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9658976B2 (en) * 2014-11-07 2017-05-23 Mediatek Inc. Data writing system and method for DMA
US10585674B2 (en) * 2016-08-22 2020-03-10 Hewlett-Packard Development Company, L.P. Connected devices information

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0732659B1 (de) * 1995-03-17 2001-08-08 LSI Logic Corporation (n+i) Ein/Ausgabekanälesteuerung, mit (n) Datenverwaltern, in einer homogenen Software-Programmierbetriebsumgebung
US5907702A (en) * 1997-03-28 1999-05-25 International Business Machines Corporation Method and apparatus for decreasing thread switch latency in a multithread processor
WO2001038970A2 (en) 1999-11-22 2001-05-31 Ericsson Inc Buffer memories, methods and systems for buffering having seperate buffer memories for each of a plurality of tasks
US6988122B2 (en) * 2001-01-09 2006-01-17 International Business Machines Corporation Ferris-wheel queue
US7145913B2 (en) * 2001-02-15 2006-12-05 The Board Of Trustees Of The University Of Illinois Thread based scalable routing for an active router
US6845501B2 (en) * 2001-07-27 2005-01-18 Hewlett-Packard Development Company, L.P. Method and apparatus for enabling a compiler to reduce cache misses by performing pre-fetches in the event of context switch
US7136991B2 (en) 2001-11-20 2006-11-14 Henry G Glenn Microprocessor including random number generator supporting operating system-independent multitasking operation
US7113985B2 (en) * 2002-10-15 2006-09-26 Intel Corporation Allocating singles and bursts from a freelist
US7143267B2 (en) * 2003-04-28 2006-11-28 International Business Machines Corporation Partitioning prefetch registers to prevent at least in part inconsistent prefetch information from being stored in a prefetch register of a multithreading processor

Also Published As

Publication number Publication date
EP1776632B1 (de) 2012-03-21
CN100533371C (zh) 2009-08-26
US8099533B2 (en) 2012-01-17
EP1776632A1 (de) 2007-04-25
JP2008509470A (ja) 2008-03-27
CN101040255A (zh) 2007-09-19
US20110099304A1 (en) 2011-04-28
WO2006016298A1 (en) 2006-02-16

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