CN101022695B - Circuit embedded in dielectric layer non-core band thin base sheet and manufacting method - Google Patents
Circuit embedded in dielectric layer non-core band thin base sheet and manufacting method Download PDFInfo
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- CN101022695B CN101022695B CN2007100896974A CN200710089697A CN101022695B CN 101022695 B CN101022695 B CN 101022695B CN 2007100896974 A CN2007100896974 A CN 2007100896974A CN 200710089697 A CN200710089697 A CN 200710089697A CN 101022695 B CN101022695 B CN 101022695B
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Abstract
A coreless thin substrate with circuit embedded in dielectric layer consists of multiple first patternized dielectric layer embedded with circuits and at least one second patternized dielectric layer embedded with conduction components. It is featured as setting said second patternized dielectric layer between said first patternized dielectric layers and using thermal lamination process to conduct circuits on said first patternized dielectric layers by said conduction components on said second patternized dielectric layer for making said substrate be outline of thin and flat. In one embodiment, the first patternized dielectric layer is a negative image ink jetting printing layer, and these circuits are exposed on an upper surface and a down surface of the patternized dielectric layer.
Description
Technical field
The invention relates to multilayer circuit board, particularly be embedded in the centreless thin base sheet and the manufacture method thereof of dielectric layer relevant for a kind of circuit.
Background technology
In each electronic product, all can use the connection of multilayer circuit board as electrical signals conduction, power supply supply, ground connection.Along with the microminiaturization development trend of electronic product, wish that multilayer circuit board can more and more approach and the circuit densification.Usually multilayer circuit board can be divided into staked type (lamination) and additional layers (build-up) according to its processing procedure.
The what is called mode of coinciding is the circuit board that several are made of core layer (core layer) and surface lines layer, through hot laminating (thermal lamination) step, be combined into multilayer circuit board, and be to be provided with the complete insulating barrier of polymerization not between these circuit boards.It is to comprise on the circuit board of core layer and surface lines layer printing successively one to form insulating barrier and form line layer with electroplating that what is called increases layer mode.No matter be that staked type or additional layers all need be with at least one circuit board that comprises core layer as coinciding monomer or increase a layer carrier, so multilayer circuit board have thicker thickness.And because the surface of core layer is to be a uneven surface, therefore the feasible line layer that is formed on the core layer, also uneven situation can take place, and behind the core layer that successively forms multilayer, insulating barrier and line layer, the thickness of multilayer circuit board is uncontrollable, and can cause the air spots of multilayer circuit board smooth.
Relevant staked type multilayer circuit board and additional layers multilayer circuit board have been disclosed as Taiwan letters patent numbers No. 1236324 " circuit board insulation layer structure and utilize this insulating barrier to form the method for making of circuit board ".In addition, Taiwan patent announcement No. 585016 " Layer increasing method of multilayer board and structure thereof " then discloses a kind of using with and increases the multilayer board that floor and the mode of coinciding are made, so in above-mentioned known multilayer circuit plate structure, all must use core layer, and circuit all be relief on the surface of core layer, have adverse influence for the thinning of circuit board and planarization design.
Fig. 1 is a kind of schematic cross-section of known staked type multilayer circuit board.This multilayer circuit board 100 is coincided by several core substrate 110 heat and forms, and is to be provided with insulating barrier 120 between these core substrates 110.Each core substrate 110 is to include core layer 111 and several are convexly set in a upper surface of this core layer 111 and the line layer 112,113 of a lower surface, in core substrate 110, utilize via 114 to electrically connect same core substrate 110 line layers 112,113.In heat coincided process, this insulating barrier 120 was for incomplete polymeric material layer (being the B stage), and with these core substrates 110 of gluing, and this insulating barrier 120 is to flow to fill up the space of internal layer circuit layer 112,113 and these vias 114.Right uncontrollable in order to these insulating barrier 120 thickness of the different core substrate 110 that is electrically insulated.In addition, the operation that coincides of known heat only reaches the mechanical adhesion of different core substrate 110, after heat coincides, 110 of different core substrates still do not have to electrically connect to close, must carry out a through hole in addition and form step, to form a suitable through hole 130, this through hole 130 is to run through these core substrates 110 and this insulating barrier 120, and in this through hole 130, electroplate a metal level, to electrically connect these core substrates 110, outer surface at these core substrates 110 respectively forms a welding cover layer 140 (solder mask) at last, to form this multilayer circuit board 100.Because this multilayer circuit board 100 of known staked type is complicated because of manufacturing process, therefore causes cost of manufacture to improve, and have thicker degree.
Summary of the invention
Main purpose of the present invention is that the centreless thin base sheet and the manufacture method thereof that provide a kind of circuit to be embedded in dielectric layer is provided, this substrate is to utilize chimeric several first pattern dielectric layer and at least one chimeric second pattern dielectric layer by several feed-through assemblies by several circuits to be formed, wherein this second pattern dielectric layer is to be arranged between these first pattern dielectric layer, and with electrically conduct these circuits of these first pattern dielectric layer of these feed-through assemblies, to omit the through hole processing procedure after the known hot laminating and to have the outward appearance of thinning more and planarization.
A time purpose of the present invention is that the centreless thin base sheet that provides a kind of circuit to be embedded in dielectric layer is provided, manufacture method and circuit embedded structure thereof, wherein these first pattern dielectric layer are the ink-jet printed layer that can be negative-appearing image (negative image), its pattern image is opposite with these circuits of same layer, so that these circuits are embedded in these first pattern dielectric layer, and the thickness of these first pattern dielectric layer be with the thickness of these circuits that are embedded in these first pattern dielectric layer for consistent, so that these circuits can flatly be exposed to a upper surface and a lower surface of these first pattern dielectric layer, do not need to use known core layer to carry out complicated basal plate making process step in order to when carrying out hot laminating (thermal lamination), electrically connecting these circuits and these feed-through assemblies.
According to the present invention, the centreless thin base sheet that a kind of circuit is embedded in dielectric layer mainly comprises several chimeric first pattern dielectric layer and at least one chimeric second pattern dielectric layer that feed-through assembly is arranged that circuit is arranged.Wherein, this second pattern dielectric layer is to be arranged between these first pattern dielectric layer, and through hot laminating, these circuits of these first pattern dielectric layer so that these feed-through assemblies electrically conduct.So can omit the through hole processing procedure after the known hot laminating and have the outward appearance of thinning more and planarization.
Description of drawings
Fig. 1 is the schematic cross-section of known staked type multilayer circuit board.
Fig. 2 is that a kind of circuit is embedded in the schematic cross-section of the centreless thin base sheet of dielectric layer according to a specific embodiment of the present invention.
Fig. 3 A to 3C is according to a specific embodiment of the present invention, the wherein chimeric schematic cross-section of first pattern dielectric layer in ink jet printing process that circuit is arranged of this centreless thin base sheet.
Fig. 4 A to 4B is according to a specific embodiment of the present invention, the wherein chimeric schematic cross-section of second pattern dielectric layer in forming process that feed-through assembly is arranged of this centreless thin base sheet.
Figure 5A to 5B is according to a specific embodiment of the present invention, the schematic cross-section of this centreless thin base sheet in the hot laminating process.
The primary clustering symbol description
100 multilayer circuit boards
110 core substrates, 111 core layers, 112 line layers
113 line layers, 114 vias
120 insulating barriers, 130 through holes, 140 welding cover layers
200 centreless thin base sheets
210 first pattern dielectric layer, 211 circuits, 212 interconnection pads
213 first outer connection pad 214 upper surfaces 215 lower surfaces
216 exposed surfaces
220 second pattern dielectric layer
221 feed-through assemblies, 222 upper surfaces, 223 lower surfaces
230 the 3rd pattern dielectric layer, 231 second outer connection pads
241 first welding cover layers, 242 second welding cover layers
251 first electrodeposited coatings, 252 second electrodeposited coatings
310 carriers, 320 carriers
Embodiment
One embodiment of the invention are described as follows.As shown in Figure 2, the centreless thin base sheet 200 that a kind of circuit is embedded in dielectric layer is mainly to comprise several first pattern dielectric layer 210 and at least one second pattern dielectric layer 220, and this second pattern dielectric layer 220 is to be arranged between these first pattern dielectric layer 210.
Each first pattern dielectric layer 210 is chimeric several circuits 211 that have, and these circuits 211 can be connected to several also for being embedded in the interconnection pad 212 in these first pattern dielectric layer 210.In addition, be positioned at 210 chimeric first outer connection pads 213 that have several to connect these circuits 211 of wherein outermost first pattern dielectric layer.Because these circuits 211, these interconnection pads 212 and these first outer connection pads 213 are to be embedded in these first pattern dielectric layer 210, therefore make these first pattern dielectric layer 210 have a comparatively smooth upper surface 214 and a lower surface 215.In order accurately to form above-mentioned embedded lines 211, preferably, these first pattern dielectric layer 210 are the ink-jet printed layer that can be negative-appearing image (negative image), its pattern image is opposite with these circuits 211 that are positioned at one deck, its material can be selected not non-conductive printing ink or the non-conductive adhesive before the polymerization such as PI (polyimide), PET for use, and to have multistage slaking characteristic be preferable.These circuits 211, these interconnection pads 212 and these first outer connection pads 213 then can be the ink-jet printed layer of an erect image (positive image), its material can be selected electrically conductive ink for use, and electrically conductive ink can and be made up of as the polymerizer of resinae the trickle conducting particles of high-load, and wherein conducting particles is to select silver powder, copper powder, carbon dust or other electric conductive polymer or the like for use.The thickness of these first pattern dielectric layer 210 is consistency of thickness of these circuits 211, these interconnection pads 212 and these the first outer connection pads 213 that are embedded in these first pattern dielectric layer 210 with it, one-tenth-value thickness 1/10 is approximately between 8～50 microns, so that these circuits 211, these interconnection pads 212 and these first outer connection pads 213 can be exposed to this upper surface 214 and this lower surface 215 (exposed surface 216 shown in 3C figure) of these first pattern dielectric layer 210, be electrically conducted in order to upper and lower layer.
This second pattern dielectric layer 220 is chimeric several feed-through assemblies 221 that have, and these feed-through assemblies 221 are these circuits 211 of these first pattern dielectric layer 210 of electrically conducting.These feed-through assemblies 221 can be selected from one of them of conductor bolt, plated-through-hole and interior connection gasket, if it is preferable selecting for use plated-through-hole then to fill up hole with electrically conductive ink, these feed-through assemblies are a upper surface 222 and a lower surface 223 that are exposed to this second pattern dielectric layer 220.The material of these feed-through assemblies 221 can be electrically conductive ink or conducting metal.In the present embodiment, these feed-through assemblies 221 can be the embedding kenel, and this second pattern dielectric layer 220 also can chimericly have other circuit (figure do not draw), but these circuits should with these circuits 211 of this first pattern dielectric layer 210 for be not connected, staggered or overlapping, in case short circuit.Preferably, this second pattern dielectric layer 220 is the ink-jet printed layer for a negative-appearing image, with the position and the size of these feed-through assemblies 221 of accurate definition, make that these feed-through assemblies 221 can be in alignment with these interconnection pads 212 or these first outer connection pads 213 of these first pattern dielectric layer 210.This second pattern dielectric layer 220 is to select non-conductive printing ink or non-conductive adhesive (NCP or NCF, Non-Conductive Paste/Film) for use.Preferably, second pattern dielectric layer 220 is to can be non-conductive adhesive, and its cure shrinkage can be promoted these feed-through assemblies 221 for these interconnection pads 212 of corresponding these first pattern dielectric layer 210 or the electrical contact of these first outer connection pads 213.
This centreless thin base sheet 200 can include first welding cover layer 241 in addition, it is to be formed on outermost these first pattern dielectric layer 210, and at least the part appear these first outer connection pad 213, the first electrodeposited coatings 251 be formed at one of these first outer connection pads 213 appear the surface.Preferably, this centreless thin base sheet 200 can include one the 3rd pattern dielectric layer 230 in addition, and it is to be positioned at a lateral surface of this second pattern dielectric layer 220 and chimeric several second outer connection pads 231 to be arranged.And one second welding cover layer 242 is to be formed at the 3rd pattern dielectric layer 230, and the part appears these second outer connection pads 231 at least.And with one second electrodeposited coating 252 be formed at these second outer connection pads 231 appear the surface.
Therefore, this centreless thin base sheet 200 does not need core layer and does not have the circuit of relief, has the outward appearance of thinning more and planarization.In addition, compared to the box-like multilayer circuit board of tradition stratum, this centreless thin base sheet 200 in hot laminating the time can reach mechanical adhesion and levels electrically conducts, need not hot repressing carries out through hole after closing and forms operation, have processing procedure and simplify and the effect that reduces manufacturing cost, and in the layout of circuit and design, bigger space and elasticity are arranged.
The manufacture method of this centreless thin base sheet 200 is described as follows:
As shown in Figure 3A, one first pattern dielectric layer 210 is formed on the carrier 310 in the inkjet printing mode, this first pattern dielectric layer 210 is the ink-jet printed layer for negative-appearing image (negative image), wherein this carrier 310 is can be preferably a heat to discharge glued membrane (thermal release film), in order to peeling off of back processing procedure.When inkjet printing, this first pattern dielectric layer 210 is that prebake conditions makes this first pattern dielectric layer 210 become B stage characteristic to reach partially polymerized immediately for the A stage can liquidly apply.Shown in Fig. 3 B, can utilize the inkjet printing mode to form several circuits 211, these circuits 211 are the ink-jet printed layer for an erect image (positive image), it is to be embedded in the space of this first pattern dielectric layer 210.Then, shown in Fig. 3 C, remove this carrier 310, to form chimeric this first pattern dielectric layer 210 that these circuits 111 are arranged.Therefore can make by above-mentioned processing procedure and have the pattern dielectric layer that various circuit changes.
Shown in Fig. 4 A, second pattern dielectric layer 220 is to be formed on another carrier 320 in the inkjet printing mode, and this second pattern dielectric layer 220 is ink-jet printed layer of negative-appearing image (negative image).Shown in Fig. 4 B, form several feed-through assemblies 221 in the space of this second pattern dielectric layer 220.Remove this carrier 320 again, to form chimeric this second pattern dielectric layer 220 that these feed-through assemblies 221 are arranged.
Shown in Fig. 5 A, under a heating and the environment of exerting pressure, hot laminating (thermal lamination) these first pattern dielectric layer 210 and this second pattern dielectric layer 220, wherein this second pattern dielectric layer 220 is to be arranged between these first pattern dielectric layer 210.Shown in Fig. 5 B, can make these first pattern dielectric layer 210 and this second pattern dielectric layer 220 be complete polymerization.And by electrically conduct these circuits 211 of these first pattern dielectric layer 210 of these feed-through assemblies 221.At last, form above-mentioned this welding cover layer 241,242 and these electrodeposited coatings 251,252 and promptly can be made into this centreless thin base sheet 200.
Protection scope of the present invention is as the criterion when looking the claim scope person of defining, and anyly knows this skill person, and any variation and the modification done without departing from the spirit and scope of the present invention all belong to protection scope of the present invention.
Claims (10)
1. a circuit is embedded in the centreless thin base sheet of dielectric layer, comprises:
Several first pattern dielectric layer, it is chimeric several circuits that has;
At least one second pattern dielectric layer, it is chimeric several feed-through assemblies that has;
One first welding cover layer, it is formed on outermost described first pattern dielectric layer, and the local at least first outer connection pad that is embedded in described outermost described first pattern dielectric layer that appears; And
One first electrodeposited coating, it is formed on the described first outer connection pad;
Wherein, described second pattern dielectric layer and described first pattern dielectric layer are crisscross arranged, and the described feed-through assembly of this second pattern dielectric layer is the described circuit of described first pattern dielectric layer of electrically conducting;
The thickness of described first pattern dielectric layer is the consistency of thickness of corresponding chimeric described circuit with it,
Wherein said circuit is exposed to the upper surface and the lower surface of described first pattern dielectric layer, and described feed-through assembly is exposed to a upper surface and a lower surface of described second pattern dielectric layer,
Wherein, described first pattern dielectric layer is the ink-jet printed layer of negative-appearing image, and the pattern image of the ink-jet printed layer of this negative-appearing image is opposite with the described circuit that is positioned at one deck,
Wherein, this second pattern dielectric layer is to be non-conductive adhesive.
2. circuit as claimed in claim 1 is embedded in the centreless thin base sheet of pattern dielectric layer, and wherein outermost described first pattern dielectric layer is the more chimeric first outer connection pad that has several to connect described circuit.
3. circuit as claimed in claim 1 is embedded in the centreless thin base sheet of pattern dielectric layer, and other includes one the 3rd pattern dielectric layer, and it is positioned on the lateral surface of this second pattern dielectric layer and chimeric several second outer connection pads is arranged; Also comprise
One second welding cover layer, it is formed on the 3rd pattern dielectric layer, and the part appears the described second outer connection pad at least;
One second electrodeposited coating, it is formed on the described second outer connection pad.
4. a circuit is embedded in the manufacture method of the centreless thin base sheet of dielectric layer, comprises:
Several first pattern dielectric layer are provided, and it is chimeric several circuits that has;
At least one second pattern dielectric layer is provided, and it is chimeric several feed-through assemblies that has;
Form one first welding cover layer on outermost described first pattern dielectric layer, and the part appears the first outer connection pad at least;
Form one first electrodeposited coating outside described first on the connection pad; And
Described first pattern dielectric layer of hot laminating and this second pattern dielectric layer, wherein said second pattern dielectric layer and described first pattern dielectric layer are crisscross arranged, and make the electrically conduct described circuit of described first pattern dielectric layer of described feed-through assembly,
Wherein, the thickness of described first pattern dielectric layer is embedded in the consistency of thickness of the described circuit of described first pattern dielectric layer with it,
Wherein, feed-through assembly is exposed to a upper surface and a lower surface of described second pattern dielectric layer,
Wherein, described first pattern dielectric layer is to be formed on the carrier in negative-appearing image inkjet printing mode,
Wherein, outermost described first pattern dielectric layer is the more chimeric first outer connection pad that has several to connect described circuit.
5. circuit as claimed in claim 4 is embedded in the manufacture method of the centreless thin base sheet of dielectric layer, and wherein this carrier is to discharge glued membrane for heat.
6. circuit as claimed in claim 4 is embedded in the manufacture method of the centreless thin base sheet of dielectric layer, and wherein said circuit is to be formed on this first pattern dielectric layer in erect image inkjet printing mode.
7. circuit as claimed in claim 4 is embedded in the manufacture method of the centreless thin base sheet of dielectric layer, and wherein this second pattern dielectric layer is to form in the inkjet printing mode.
8. circuit as claimed in claim 4 is embedded in the manufacture method of the centreless thin base sheet of dielectric layer, and wherein said feed-through assembly is upper surface and the lower surface that is exposed to this second pattern dielectric layer.
9. circuit as claimed in claim 4 is embedded in the manufacture method of the centreless thin base sheet of dielectric layer, and wherein this second pattern dielectric layer is a non-conductive adhesive.
10. circuit as claimed in claim 4 is embedded in the manufacture method of the centreless thin base sheet of dielectric layer, and other comprises: one the 3rd pattern dielectric layer is provided, and it is to be positioned at a lateral surface of this second pattern dielectric layer and chimeric several second outer connection pads to be arranged; Also comprise
Form one second welding cover layer on the 3rd pattern dielectric layer, and the part appears the described second outer connection pad at least
Form one second electrodeposited coating outside described second on the connection pad.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100896974A CN101022695B (en) | 2007-03-27 | 2007-03-27 | Circuit embedded in dielectric layer non-core band thin base sheet and manufacting method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100896974A CN101022695B (en) | 2007-03-27 | 2007-03-27 | Circuit embedded in dielectric layer non-core band thin base sheet and manufacting method |
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| CN101022695A CN101022695A (en) | 2007-08-22 |
| CN101022695B true CN101022695B (en) | 2011-05-25 |
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| TWI629737B (en) * | 2016-11-24 | 2018-07-11 | 原通科技股份有限公司 | Method for fabricating signal testing component |
| CN111916354B (en) * | 2019-05-07 | 2022-08-30 | 欣兴电子股份有限公司 | Circuit carrier plate and manufacturing method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1315246A (en) * | 1999-09-16 | 2001-10-03 | 株式会社东芝 | 3-D structure and producing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1315246A (en) * | 1999-09-16 | 2001-10-03 | 株式会社东芝 | 3-D structure and producing method thereof |
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| CN101022695A (en) | 2007-08-22 |
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