CN100573849C - 用于形成具有鳍状结构的半导体元件的方法 - Google Patents
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Abstract
本发明公开了一种用于形成具有鳍状结构的半导体元件的方法。所述方法包括:(a)在硅基板的上形成元件隔离膜,以界定有源区域;(b)蚀刻形成栅极的区域的硅基板以形成沟槽;(c)选择性地蚀刻与沟槽两侧相邻的元件隔离膜,(d)在所产生的结构的整个表面的上形成栅极氧化膜;(e)在所产生的结构的整个表面的上沉积电极材料以形成一栅极电极;以及(f)在该栅极电极的侧壁的上形成栅极分隔物。
Description
技术领域
本发明总体涉及一种用于形成具有鳍状结构的半导体元件的方法,并且更明确地说,其涉及一种用于形成具有鳍状结构的半导体元件的方法,该方法包括利用凹形栅极掩模来蚀刻硅基板并且在具有双氧化膜结构的元件隔离膜的上执行选择性的蚀刻工艺。
背景技术
一种用于形成具有鳍状结构的半导体元件的公知的方法如下所述地被执行。
首先,元件隔离氧化膜形成在硅基板上,并且离子接着被注入到单元区域中,以形成阱。
有源区域的硅基板利用凹形栅极掩模而被蚀刻。
该元件隔离氧化膜利用鳍状掩模而被蚀刻。
栅极氧化膜形成在所产生的结构的整个表面上。
多晶硅层、硅化钨层以及硬式掩模氮化膜沉积在所产生的结构的整个表面的上,以形成栅极电极。
由于该元件隔离氧化膜是根据该公知的方法而利用鳍状掩模被过度蚀刻以形成鳍状结构,因此在伪(dummy)鳍状中的多晶硅会影响到有源存储节点,因而使得电气特性劣化。再者,由于该凹形栅极掩模以及鳍状掩模两者都被使用,因此其工艺是复杂的,因而精确度会劣化。
发明内容
本发明的各种实施例涉及提供一种用于形成具有鳍状结构的半导体元件的方法,该方法包括利用凹形栅极掩模来蚀刻硅基板,并且在具有双氧化膜结构的元件隔离膜的上以快速的氧化膜蚀刻速度以及慢速的氧化膜蚀刻速度来执行选择性的蚀刻工艺,由此简化该工艺并且最大化电流驱动的操作。
根据本发明的一个实施例,一种用于形成具有鳍状结构的半导体元件的方法包含(a)在硅基板的上形成元件隔离膜,以界定有源区域;(b)蚀刻该有源区域的形成栅极的区域的硅基板以形成沟槽;(c)选择性地蚀刻与该沟槽的两侧相邻的元件隔离膜;(d)在所产生的结构的整个表面的上形成栅极氧化膜;(e)在所产生的结构的整个表面的上沉积电极材料以形成栅极电极;以及(f)在该栅极电极的侧壁的上形成栅极分隔物。
附图说明
本发明的其它特点及优点将会在阅读以下的详细说明以及在参照附图之后变得明显,在该附图中:
图1是根据本发明的一个实施例,在形成具有鳍状结构的半导体元件的栅极线后的平面图;
图2至8b是描绘根据本发明的一个实施例的一种用于形成具有鳍状结构的半导体元件的方法的横截面图(在此,图2、3、4a、5a、6a、7及8a是在图1中所示的X轴方向上的横截面图,而图4b、5b、6b及8b是在图1中所示的Y轴方向上的横截面图);以及
图9a与图9b是描绘根据本发明的另一实施例的一种用于形成具有鳍状结构的半导体元件的方法的图。
附图标记说明
100有源区域
110第一氧化膜
120第二氧化膜
130沟槽
140沟槽边界的第一氧化膜蚀刻部分
150沟槽边界的第二氧化膜蚀刻部分
160第二氧化膜的上方的蚀刻部分
170栅极氧化膜
180多晶硅层
190硅化钨层
200硬式掩模氮化膜
210选择性的热氧化膜
220栅极缓冲氧化膜
230栅极分隔物氮化膜
240圆形的沟槽
具体实施方式
本发明将会详细地参考附图加以描述。只要有可能的话,相同的参考标号将会贯穿附图被利用来指示相同或类似的元件。
请参照图2,一个用于在硅基板的上形成元件隔离膜的区域被蚀刻以界定有源区域100,并且第一氧化膜110以及第二氧化膜120依序地沉积在该区域上,以形成双氧化膜。
优选的是,第一氧化膜110以及第二氧化膜120的厚度范围是从300至
优选的是,第一氧化膜110包含具有快速的湿式蚀刻的速度的氧化膜,并且第二氧化膜120包含具有慢速的湿式蚀刻的速度的氧化膜。优选的是,该具有快速的湿式蚀刻的速度的氧化膜包含SOD(旋涂式电介质)氧化膜,而该具有慢速的湿式蚀刻的速度的氧化膜系包含HDP(高密度等离子体)氧化膜。
请参照图3,氧化膜125形成在有源区域100上。接着,离子被注入到单元区域的有源区域100中以形成阱。此外,离子被注入到周边的区域中以形成阱。氧化膜125被用来避免由该离子注入的工艺所导致对有源区域100的损害。优选的是,氧化膜125具有厚度范围是从30至
请参照图4a与4b,该硅基板的有源区域100的形成栅极的区域利用凹形栅极掩模而被蚀刻,以形成沟槽130。
优选的是,用于形成沟槽130的蚀刻步骤是干式蚀刻的工艺。
优选的是,沟槽130的底部具有正方形或是圆形的形状。
沟槽130的形成可扩大源极与漏极的长度。
请参照图5a与5b,选择性的湿式蚀刻的工艺在沟槽130的边界的元件隔离膜上执行,以形成鞍形(saddle)鳍状架构。
该鞍形鳍状结构指一种结构,其中有源区域在垂直于栅极线的方向(X轴方向)上具有凹形栅极结构,并且在栅极线方向(Y轴方向)上具有鳍状结构,该鳍状结构为栅极氧化膜以及栅极电极覆盖有源区域。
如图5b中所示,沟槽130的边界的第一氧化膜110选择性地通过湿式蚀刻的工艺来加以蚀刻(移除材料140)。
接着,第二氧化膜120相邻于第一氧化膜110的一个角通过湿式蚀刻的工艺而被蚀刻(移除材料150)。
如图5a与5b中所示,第二氧化膜120的上方的部分以及有源区域100的上方的氧化膜125亦通过湿式蚀刻的工艺而被蚀刻(移除材料160)预设的深度(亦即,移除预设的厚度)。
由于第一氧化膜110的湿式蚀刻的速度比第二氧化膜120的湿式蚀刻的速度快,所以第一氧化膜110比第二氧化膜120被蚀刻得多。其产生的结果是在图5b中所示的相邻于有源区域100的开口140。
请参照图6a与6b,栅极氧化膜170形成在所产生的结构的整个表面的上。
请参照图7,多晶硅层180、硅化钨层190以及硬式掩模氮化膜200依序地沉积在所产生的结构的整个表面的上,以形成栅极电极。
光致抗蚀剂图案形成在硬式掩模氮化膜200上,以蚀刻硬式掩模氮化膜200。接着,该光致抗蚀剂图案被移除,并且硅化钨层190以及多晶硅层180利用剩余的硬式掩模氮化膜200的图案作为掩模而被蚀刻。
请参照图8a与8b,选择性的热氧化膜210形成在露出的多晶硅层180以及硅基板100的侧壁上。
栅极缓冲氧化膜220以及栅极分隔物氮化膜230依序地沉积在所产生的结构的整个表面上,并且接着被蚀刻以形成栅极分隔物。
图9a与图9b是描绘根据本发明的另一实施例的用于形成具有鳍状结构的半导体元件的方法的横截面图。图9a是在X轴方向上的横截面图,而图9b是在Y轴方向上的横截面图。
请参照图9a与9b,尽管其结构实质上是类似于参考图8a与8b所述的组件,但是沟槽130的底部具有圆形的形状240。
如上所述,在根据本发明的一个实施例的一种用于形成具有鳍状结构的半导体元件的方法中,硅基板利用凹形栅极掩模而被蚀刻,并且选择性的蚀刻工艺在具有双氧化膜结构的元件隔离膜的上进行,由此来简化工艺并且避免有源存储节点的劣化。于是,鳍状结构在改善的元件的电流驱动的操作下形成。
先前针对本发明的各种实施例的说明已经为了举例及说明的目的而被提供。其并非意欲全部列举出或是将本发明仅限于所揭露的明确的形式,而是依据上述的教示或是从本发明的实施都可以得到对其的修改与变化。因此,这些实施例被选择与描述以便于解释本发明的原理以及其实际的应用,以使得本领域的技术人员能够在各种的实施例中以及在适合所思及的特定用途的各种修改下利用本发明。
Claims (10)
1.一种用于形成具有鳍状结构的半导体元件的方法,所述方法包括:
(a)在硅基板的上形成元件隔离膜,以界定有源区域,其中所述元件隔离膜具有包含依序被沉积的第一氧化膜以及第二氧化膜的双氧化膜结构,所述第一氧化膜具有比所述第二氧化膜更快的湿式蚀刻的速度;
(b)蚀刻所述有源区域的一个形成栅极的区域的硅基板,以形成沟槽;
(c)根据在所述第一氧化膜以及第二氧化膜之间的蚀刻速度差,选择性地湿式蚀刻与所述沟槽的两侧相邻的元件隔离膜;
(d)在步骤(c)产生的结构的整个表面的上形成栅极氧化膜;
(e)在步骤(d)产生的结构的整个表面的上沉积电极材料,以形成栅极电极;以及
(f)在所述栅极电极的侧壁的上形成栅极分隔物。
3.根据权利要求1的方法,其中所述第一氧化膜包含旋涂电介质氧化膜,并且所述第二氧化膜包含高密度等离子体氧化膜。
5.根据权利要求1的方法,其中所述沟槽的底部具有正方形或圆形的形状。
7.根据权利要求1的方法,其中步骤(c)的蚀刻在BOE或HF溶液中进行。
9.根据权利要求1的方法,其在步骤(e)之后还包括形成选择性的热氧化膜,其中所述选择性的热氧化膜被形成在栅极电极的侧壁以及所述硅基板上。
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KR100577562B1 (ko) * | 2004-02-05 | 2006-05-08 | 삼성전자주식회사 | 핀 트랜지스터 형성방법 및 그에 따른 구조 |
KR100799121B1 (ko) * | 2005-12-22 | 2008-01-29 | 주식회사 하이닉스반도체 | 벌브 리세스 게이트를 갖는 반도체 소자의 제조방법 |
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-
2005
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2006
- 2006-04-17 TW TW095113623A patent/TWI317977B/zh not_active IP Right Cessation
- 2006-04-26 CN CNB2006100770539A patent/CN100573849C/zh not_active Expired - Fee Related
- 2006-04-27 US US11/411,864 patent/US7566621B2/en not_active Expired - Fee Related
- 2006-05-29 JP JP2006148488A patent/JP2007184518A/ja not_active Ceased
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KR100720232B1 (ko) | 2007-05-23 |
CN1992201A (zh) | 2007-07-04 |
TWI317977B (en) | 2009-12-01 |
US7566621B2 (en) | 2009-07-28 |
JP2007184518A (ja) | 2007-07-19 |
US20070155148A1 (en) | 2007-07-05 |
TW200725745A (en) | 2007-07-01 |
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