CN100539117C - Introduce method and structure that the high K medium material is used to strengthen the SRAM operation - Google Patents
Introduce method and structure that the high K medium material is used to strengthen the SRAM operation Download PDFInfo
- Publication number
- CN100539117C CN100539117C CN200510114904.8A CN200510114904A CN100539117C CN 100539117 C CN100539117 C CN 100539117C CN 200510114904 A CN200510114904 A CN 200510114904A CN 100539117 C CN100539117 C CN 100539117C
- Authority
- CN
- China
- Prior art keywords
- medium
- interconnection
- sram cell
- sram
- zone
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
A kind of mixing interconnection structure, it has the interconnection capacitance amount higher than other zone in one group of zone of identical microelectronic chip.The several method that is used to make this structure is provided.Described the circuit of this mixing interconnection structure and implemented, it allows to increase static noise surplus and the leakage that reduces in the sram cell, and the public power voltage of SRAM in this chip and logic.Allow the advantage of the method for these circuit of combination to be, in this chip, have higher interconnection speed of performance and excellent mechanical robustness.
Description
Technical field
The present invention relates to be used for the formation of back-end process (BEOL) interconnection structure of the advanced microelectronic chip of microprocessor, microcontroller, communication, drawing etc.The invention particularly relates to by allowing in the SRAM zone in this chip optionally the interconnection environment of high-capacitance more to improve the method for sram cell performance in this chip.
Background technology
The restriction that is subjected to array leakage and reads stability, CMOS sram cell device threshold voltage (VT) reduces more lentamente than logic, thereby need independent, higher supply voltage (VDD-CELL), in little how much sram cell transistors, to exist under the situation that VT more and more serious, at random rises and falls, obtains higher static noise surplus (SNM) and read electric current (IREAD) and lower read the electric current variation.Yet second array of power supply changes into the metal line track still less that more input and output (I/O) required and be used for other chip functions, and described function for example power, overall signal and clock distributes, and it all directly influences cost.Secondly, higher/pair unit power supply causes (i) whole components owing to the subarray of the inaccessible of arrogant L2 cache memory under enable mode, and has more leakage; And (ii) bigger switch power, influence is used for the battery life of portable use unfriendly, and the cost of encapsulation high-performance computed table and server product.
In the application YOR9200300292US1 of the application author's common pending trial, new circuit engineering has been proposed, wherein allow the single VDD SRAM of running under logical consistency voltage, wherein the static noise surplus in cell read current and unit is depicted as usually and has higher/couple VDD SRAM.Fig. 1 a, 1b and 2 show illustrative circuitry and implement.Fig. 3 has schematically shown the physical implementation of sram cell interconnection, wherein shows the array of word line (WL) and relevant power line (PL).In 65nmCMOS SOI technology, implement, and do not change CMOS technology and material or routine, single VTSRAM unit, be connected across the voltage automatic biasing on the power rails (rails) of the sram cell of selection, to allow at the voltage that is higher than VDD of word line (WL) active period with at At All Other Times the voltage that is lower than 2VT.Based on the breadboardin data, Fig. 4 shows " bootstrapping (bootstrapping) ", under this circuit is implemented supply voltage is increased 17%.Bootstrapping cell row power supply and the actual earthed voltage of regulon subarray, allow above-mentioned " conversion zone (Transregional) " SRAM operation, cause nearly sub-threshold data storage and high threshold visit, to always leak and reduce 10X, and IREAD and SNM improved 7% and 18% respectively, wherein overall area general (overhead) is less than 13%.
Thereby apparent, " transition region " SRAM operation allows logic VDD compatibility, lower leakage and higher unit to read stability, and does not reduce performance.The benefit of this bootstrap effect by allow to strengthen be used to select the WL of delegation's sram cell and be used for to power line (PL) that this row provides power between capacitive couplings, can enlarge markedly than described benefit of the prior art.By between the WL of SRAM subarray and PL line, introducing more high K medium material, be the method that obtains this effect to allow the stronger capacitive couplings between WL and the PL.Yet, use the medium of higher k to be harmful to chip performance in other zone of chip (logic and interconnect area), postpone because the capacitance of the increase in these zones converts the RC of increase to, thereby slowed down interconnect speed.In the present invention, proposed to allow more high capacitance coupling and be structure in other zone, thereby overcome this problem than low-voltage capacity in the sram cell zone.Several methods that are used to make this structure also are provided.
Summary of the invention
Thereby, an object of the present invention is to provide a kind of chip interconnection structure, it allows the hybrid system of inter-metal medium (IMD), described IMD i.e. high k or superelevation k medium in the intermetal gap between WL and PL feature, Fig. 5 provides low k or ultralow k medium to separate other regional interconnection line simultaneously.Hereinafter for convenience of description, at random high k is defined as 7＜k＜4, k is defined as k with superelevation〉7, will hang down k and be defined as 4＜k＜2.0, and ultralow k will be defined as k＜2.Another object of the present invention is the optimum benefit that realizes in the above-mentioned SRAM performance array, keeps the mechanical robustness and the low effective interconnection capacitance of chip simultaneously, to minimize the interconnect delay in other zone on the chip.Another object of the present invention provides the method that is used to make above-mentioned mixing interconnection structure.
Below with reference to following one group of accompanying drawing these and other feature of the present invention is described in more detail.
Description of drawings
Fig. 1 a and 1b are the schematic circuit that transition region SRAM implements, and show bootstrapping being higher than the PL of VDD, and utilize the PFET diode stack to regulate VGND.(the prior art patent application YOR9200300292US1 of the groups of people among the inventor);
The bootstrapping method (the prior art patent application YOR9200300292US1s of groups of people in the inventor) of Fig. 2 on PL, schematically showing with the circuit form of implementation;
Fig. 3 is the physical implementation (the prior art patent application YOR9200300292US1 of the groups of people among the inventor) on a pair of PL line of booting;
Fig. 4 is the breadboardin of explanation transition region SRAM operation, wherein uses the insulating material (the prior art patent application YOR9200300292US1s of groups of people in the inventor) identical with other zone between WL and PL;
Fig. 5 is the enhancing physical implementation according to bootstrapping method of the present invention of proposition, wherein use the medium of higher k between WL and PL path, and other the regional (not shown) in chip area uses low k dielectric;
Fig. 6 schematically describes etch-back and Integrated Solution (the U.S. Patent application 200040087135A1 of the groups of people among the inventor) is filled in the gap;
Fig. 7 has schematically shown first method of the present invention, wherein utilizes EBGF and stops lithography step manufacturing mixing SRAM interconnection structure;
Fig. 8 has schematically shown second method of the present invention that hereinafter will describe;
Fig. 9 has schematically shown the third party's method of the present invention that hereinafter will describe.
Embodiment
The present invention utilizes etch-back and gap to fill (EBGF) Integrated Solution (the U.S. Patent application 200040087135A1 of some among this author) or its modification, has proposed the manufacturing of above-mentioned mixed structure.
In the EBGF scheme that schematically shows as Fig. 6, at first in compact medium 600 (being generally the higher material of k, for example oxide, SiCOH, fine and close spin-coating glass etc.), make interconnection wiring 500, Fig. 6 a.Utilize then line itself as etching mask from etching compact medium between the gap between line, to make the structure shown in Fig. 6 b.The medium of the lower k of deposition (be generally the dielectric material 550 of low k or very low k, be generally porous, thereby make the k value low) then to 1.6, thus shown in Fig. 6 c fill etched groove.Cover then by this structure of chemico-mechanical polishing (CMP) technology complanation, and with dielectric passivation 650, thus the EBGF structure of formation shown in Fig. 6 d.Compact medium 600 is counted as Supporting Media, and is used to provide mechanical robustness, because low k IMD550 is mechanically frangible usually.
In first method of the present invention, as shown in Figure 7, in conjunction with stopping that simply lithography step uses the EBGF method, described step is protected the sram cell zone, and wherein WL and PL line utilize the photoresist mask location, thereby compact medium is stayed between these lines.Fig. 7 .1 shows the vertical view of the structure after the standard manufacture in fine and close and firm BEOL medium 600.In order to simplify, interconnection line is not shown.Then, shown in Fig. 7 .2, utilization has the exposure that stops mask and protects the sram cell zones by photoresist 100.Then, shown in Fig. 7 .3, the firm BEOL medium of etch-back in the zone that is not subjected to stopping the mask protection is peeled off resist then.At last, utilization is carried out the gap filling than the zone that firm BEOL medium 600 has 550 pairs of etch-back of medium of lower k, and the parallel planesization of going forward side by side is shown in Fig. 7 .4.For example, mechanically robust BEOL medium 600 can be selected from: silica, fluorided silica comprises the organic silicic acid salt medium of silicon, carbon, oxygen and hydrogen.Gap filled media 550 can be that k＜2.5 preferably are lower than the organosilicate of 2 porous or fine and close form and organic media for example polyimides, poly (arylene ether) and celelular silica.In addition, can also protect for example chip incision site, joint or detection pad and cutting raceway groove by stopping photoetching, thereby the protection Supporting Media is to prevent to cut or engage the crack that causes.Stop that mask and relevant photoetching can be quite lax primitive rules than the minimum ground rule of the technology that is used for manufacturing cell, thereby can significantly not increase cost.By like this, can the firm mixed structure of manufacturing machine, wherein the k of the IMD in the WL/PL gap is up to 4, and the k of the IMD in the residue interconnect area is low to moderate 1.6.This allows the bootstrap voltage mode of the increase in the sram cell, and it is realized by the higher Cc value from high k material, keeps the high speed (low-voltage capacity) of the interconnection wiring Anywhere on the chip simultaneously.
In second method of the present invention; proposed to utilize low k dielectric 700 (for example the organosilicate of porous and fine and close form and organic media for example polyimides, poly (arylene ether) and celelular silica) to make interconnection structure, utilize stop Etching mask 100 protections except that the WL/PL gap area All Ranges, the low k dielectric between the etching WL/PL line and utilize the high K medium 750 filling gaps parallel planesization of going forward side by side.Fig. 8 has schematically shown this technological process (having omitted interconnection line in order to simplify equally).In this case, can utilize the material of very high k to carry out the gap filling, described material is titanium dioxide, zirconia, hafnium oxide and silicate thereof, barium strontium salt, barium titanate zirconates etc. for example, and it for example can handle deposition by the collosol and gel that utilizes metal alkoxide solution.These films can have the k value up to 20-40, thereby enlarge markedly the capacitance that can obtain between WL and PL.Total interconnection capacitance amount and mechanical robustness will be by the low k dielectric decisions that is used for making initial configuration before EBGF.
In third party's method of the present invention, schematically show as Fig. 9, utilize the robust support medium 600 that has usually the moderate k in 2.5 to 4.0 scope to make interconnection, Fig. 9 .1 (note,, omitted interconnection line) for simplicity of illustration.Robust support medium 600 can be selected from silica, fluorided silica, comprises silicon, the organic silicic acid salt medium of carbon, oxygen and hydrogen.Stop in the photoetching first, shown in Fig. 9 .2, the WL in the SRAM zone of only exposing and PL zone, and utilize photoresist figure 100 to stop remaining areas.Carry out first etch-back (Fig. 9 .3), utilize then as high k in above-mentioned first modification or superelevation k medium 750 and fill gaps, carry out the CMP complanation afterwards, Fig. 9 .4 robust support medium 600.Thereby medium 750 can for example be selected from titanium dioxide, zirconia, hafnium oxide and silicate thereof, barium strontium salt, barium titanate zirconates etc., and it can handle deposition by the collosol and gel that utilizes metal alkoxide solution.Then, form second and stop photoresist figure 110, it protects whole SRAM WL/PL zone and cutting raceway groove and bond pad, Fig. 9 .5.Etch-back is not subjected to stopping the robust support medium 600 (Fig. 9 .6) in the zone of figure 110 protections; utilize low k or ultralow k medium 550 to fill the gap then; the parallel planesization of going forward side by side; such interconnect area will be formed; it has low-down capacitance; thereby and have very low wiring delay, a Fig. 9 .7.Medium 550 can be selected from k＜2.5 and preferably be lower than the organosilicate of 2 porous or fine and close form and organic media for example polyimides and poly (arylene ether) and celelular silica.The network of Fig. 9 .7 is in conjunction with the mechanical robustness that is provided by robust support medium 600, significantly reduced interconnect delay, this fills 550 by ultralow k medium gap and realizes, and the very large capacitance that is coupled in the sram cell zone, this realizes by the high k in this zone or superelevation k gap filled media 750.Owing to need additional step, the cost of this modification may be a little more than the cost of other two kinds of modification, but has obtained higher levels of overall performance, and can prove, and is used for more high performance cost and pays and be worth.
In cubic method of the present invention, utilize suitable exposure method to adjust low k or ultralow k IMD zone in the sram cell zone separately, carry out optional thermal annealing then, described method is selected from ion and injects, photon radiation is from liquid, steam or based on the chemosmosis of the transmission medium of supercritical liq.Can make basic interconnection structure self by previously described standard dual damascene technology or EBGF technology.After making interconnection structure, stop photoetching, in order to the Zone Full of protecting with photoresist except that the sram cell zone.Then, carry out adjusting process, to allow IMD is converted to the material of higher k.Peel off and stop resist, and utilize the medium set-up procedure to continue to make the technology of other layer for the SRAM zone that is included in the additional interconnection level that needs.
The structure that obtains by the invention described above method has higher interconnection capacitance amount in wishing the sram cell zone of subnormal voltage operation, wishing that other zone that high speed transmission of signals and low interconnect power dissipate has low or ultralow interconnection capacitance amount.In addition, it is in cutting raceway groove, bond pad and all introduced mechanically robust IMD under the interconnection line, thereby excellent chip robustness is provided.
Claims (23)
1. interconnection structure, be included in the same plane, in first top of media with a k value, and contact a plurality of conductors that are provided with described first medium, second medium that interval between first subclass of wherein said a plurality of conductors is had the 2nd k value occupies, and the 3rd medium that the interval between second subclass of described a plurality of conductors is had the 3rd k value occupies, wherein said first, second comprises mutually different first with the 3rd medium, the second and the 3rd material, a described k value is 2.0＜k＜4.0, described the 2nd k value be 4＜k＜7 or greater than 7 and described the 3rd k value less than 2.5, between described a plurality of conductors and described first medium, described second medium and the 3rd medium are not set, first subclass of described conductor is the interconnection wiring that is arranged in the sram cell of microelectronic chip, and second subclass of described conductor is arranged in other zone except that described sram cell, and is used for the zones of different on the interconnect die.
2. according to the structure of claim 1, wherein said a plurality of conductors are interconnection wirings, and it comprises conductive barrier lining and the higher packing material of conductivity.
3. according to the structure of claim 1, wherein said first medium is to be selected from following at least a mechanically robust medium: silica, fluorided silica comprises the organic silicic acid salt medium of silicon, carbon, oxygen and hydrogen.
4. according to the structure of claim 1, wherein said second medium is selected from the medium by spin coating or plasma enhanced chemical vapor deposition deposition, and is selected from least a in titanium dioxide, zirconia, hafnium oxide and silicate thereof, barium strontium salt, the barium titanate zirconates.
5. according to the structure of claim 1, wherein said the 3rd medium is selected from least a in the organosilicate of porous or fine and close form and the organic media.
6. according to the structure of claim 5, wherein said organic media comprises at least a in polyimides, poly (arylene ether) and the celelular silica.
7. according to the structure of claim 1, first subclass of wherein said conductor comprises the word line and the power line of sram cell.
8. according to the structure of claim 1, wherein said first medium also is arranged in the cutting raceway groove in the chip and under joint and the testing weld pad.
9. according to the structure of claim 1, wherein said various medium utilizations are selected from following at least a method deposition: spin coating and curing, collosol and gel processing, chemical vapour deposition (CVD), plasma auxiliary chemical vapor deposition, physical vapour deposition (PVD) and ald.
10. according to the structure of claim 2, wherein said conductive barrier lining is selected from: the nitride of tantalum and titanium, tantalum and titanium and silicon nitride and combination thereof.
11. according to the structure of claim 2, the packing material that wherein said conductivity is higher is selected from copper, aluminium, gold, silver and combination thereof.
12. according to the structure of claim 1, wherein said structure is the mechanically robust microelectronic chip, it has high interconnection capacitance amount in the SRAM zone, and has low interconnection capacitance amount in other interconnect area.
13. according to the structure of claim 1, the more high-capacitance in the wherein said sram cell is used to allow higher supply voltage, thereby increases static noise surplus and the leakage that reduces in the sram cell.
14. according to the structure of claim 1, the more high-capacitance in the wherein said sram cell is used to allow higher supply voltage, thereby causes single supply voltage is used for simultaneously the logic and the SRAM zone of microelectronic chip.
15. make the method for mixing interconnection structure, may further comprise the steps for one kind:
On substrate the deposition first medium, and in described first medium patterned trench and via hole;
Utilize the higher packing material of conductive barrier materials and conductivity to fill described groove and via hole, to form the interconnection wiring structure;
In the first area of described substrate, form first and stop the resist figure, with the first group of interconnection that only expose;
Described first medium of etching between the described first group of interconnection wiring described first area, and peel off described photoresist;
Utilize second medium to be filled in etched gap between described first group of interconnection wiring, and to its complanation, to form coplanar structure;
Form second and stop the photoresist figure, its exposure comprises the second area of the substrate of second group of interconnection;
From described first medium of etching between described second group of interconnection, and peel off described photoresist; And
Utilize the 3rd medium to be filled in etched gap between described second group of interconnection, and to its complanation, to form coplanar structure;
Wherein, a described k value is 2.0＜k＜4.0, the k value of described second medium be 4＜k＜7 or greater than 7 and the k value of described the 3rd medium less than 2.5, described first group of interconnection is arranged in the sram cell zone, and described second area comprises the Zone Full except that described sram cell, joint and testing weld pad and cutting raceway groove.
16. according to the method for claim 15, wherein said substrate is a microelectronic chip, comprises logical block, sram cell, joint and testing weld pad and cutting raceway groove at least.
17. according to the method for claim 15, wherein said first medium is selected from following at least a: silica, fluorided silica comprises the organic silicic acid salt medium of silicon, carbon, oxygen and hydrogen.
18. according to the method for claim 15, wherein said second medium is selected from following at least a: titanium dioxide, zirconia, hafnium oxide and silicate thereof, barium strontium salt, barium titanate zirconates.
19. according to the method for claim 15, wherein said the 3rd medium is selected from following at least a: the organosilicate of porous or fine and close form and organic media.
20. according to the method for claim 19, wherein said organic media comprises at least a in polyimides, poly (arylene ether) and the celelular silica.
21. according to the method for claim 15, wherein the described mixing interconnection structure by described method manufacturing is the mechanically robust microelectronic chip, it has high interconnection capacitance amount in the SRAM zone, and has low interconnection capacitance amount in other interconnect area.
22. according to the method for claim 15, it forms a microelectronic chip, has mechanically robust mixing interconnection structure, and can move with the form that higher static noise surplus and the sram cell that reduces leak.
23. according to the method for claim 15, it forms a microelectronic chip, has mechanically robust mixing interconnection structure, and can be with the form operation of the SRAM that single supply voltage is used for simultaneously described chip and logical block.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/988,484 | 2004-11-12 | ||
| US10/988,484 US20060103023A1 (en) | 2004-11-12 | 2004-11-12 | Methods for incorporating high k dielectric materials for enhanced SRAM operation and structures produced thereby |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1776905A CN1776905A (en) | 2006-05-24 |
| CN100539117C true CN100539117C (en) | 2009-09-09 |
Family
ID=36385406
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200510114904.8A Active CN100539117C (en) | 2004-11-12 | 2005-11-11 | Introduce method and structure that the high K medium material is used to strengthen the SRAM operation |
Country Status (2)
| Country | Link |
|---|---|
| US (2) | US20060103023A1 (en) |
| CN (1) | CN100539117C (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7259986B2 (en) * | 2005-03-25 | 2007-08-21 | International Business Machines Corporation | Circuits and methods for providing low voltage, high performance register files |
| US9153538B2 (en) * | 2013-08-22 | 2015-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacture thereof |
| US9773866B2 (en) | 2015-06-18 | 2017-09-26 | Qualcomm Incorporated | Semiconductor integrated circuits (ICs) employing localized low dielectric constant (low-K) material in inter-layer dielectric (ILD) material for improved speed performance |
| US10396042B2 (en) | 2017-11-07 | 2019-08-27 | International Business Machines Corporation | Dielectric crack stop for advanced interconnects |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04120732A (en) * | 1990-09-12 | 1992-04-21 | Hitachi Ltd | Solid element and its manufacture |
| US5548159A (en) * | 1994-05-27 | 1996-08-20 | Texas Instruments Incorporated | Porous insulator for line-to-line capacitance reduction |
| JPH11354652A (en) * | 1998-06-09 | 1999-12-24 | Mitsubishi Electric Corp | Semiconductor device |
| US6777320B1 (en) * | 1998-11-13 | 2004-08-17 | Intel Corporation | In-plane on-chip decoupling capacitors and method for making same |
| US6657302B1 (en) * | 1999-01-12 | 2003-12-02 | Agere Systems Inc. | Integration of low dielectric material in semiconductor circuit structures |
| US6214630B1 (en) * | 1999-12-22 | 2001-04-10 | United Microelectronics Corp. | Wafer level integrated circuit structure and method of manufacturing the same |
| KR100465865B1 (en) * | 2000-06-30 | 2005-01-13 | 주식회사 하이닉스반도체 | Method for forming storage node electrode in MML device |
| US20020005584A1 (en) * | 2000-07-12 | 2002-01-17 | Shinichi Domae | Semiconductor device |
| US6495918B1 (en) * | 2000-09-05 | 2002-12-17 | Infineon Technologies Ag | Chip crack stop design for semiconductor chips |
| JP2002151652A (en) | 2000-11-10 | 2002-05-24 | Hitachi Ltd | Semiconductor integrated circuit device |
| US6525372B2 (en) * | 2000-11-16 | 2003-02-25 | Silicon Wireless Corporation | Vertical power devices having insulated source electrodes in discontinuous deep trenches |
| US6649517B2 (en) * | 2001-05-18 | 2003-11-18 | Chartered Semiconductor Manufacturing Ltd. | Copper metal structure for the reduction of intra-metal capacitance |
| TWI300971B (en) * | 2002-04-12 | 2008-09-11 | Hitachi Ltd | Semiconductor device |
| JP2003332426A (en) * | 2002-05-17 | 2003-11-21 | Renesas Technology Corp | Method for manufacturing semiconductor device and semiconductor device |
| JP2004095865A (en) * | 2002-08-30 | 2004-03-25 | Nec Electronics Corp | Semiconductor device and manufacturing method therefor |
| US7208369B2 (en) * | 2003-09-15 | 2007-04-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual poly layer and method of manufacture |
| US6922370B2 (en) * | 2003-12-11 | 2005-07-26 | Texas Instruments Incorporated | High performance SRAM device and method of powering-down the same |
| US7348280B2 (en) * | 2005-11-03 | 2008-03-25 | International Business Machines Corporation | Method for fabricating and BEOL interconnect structures with simultaneous formation of high-k and low-k dielectric regions |
| JP5326202B2 (en) * | 2006-11-24 | 2013-10-30 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
-
2004
- 2004-11-12 US US10/988,484 patent/US20060103023A1/en not_active Abandoned
-
2005
- 2005-11-11 CN CN200510114904.8A patent/CN100539117C/en active Active
-
2009
- 2009-08-19 US US12/543,999 patent/US7968450B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US20100041227A1 (en) | 2010-02-18 |
| CN1776905A (en) | 2006-05-24 |
| US20060103023A1 (en) | 2006-05-18 |
| US7968450B2 (en) | 2011-06-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI633688B (en) | Integrated memory device with logic device and method of forming same | |
| US7176125B2 (en) | Method of forming a static random access memory with a buried local interconnect | |
| US9691684B2 (en) | Integrated circuit device including through-silicon via structure and decoupling capacitor and method of manufacturing the same | |
| KR100675726B1 (en) | Semiconductor integrated circuit device and process for manufacturing the same | |
| US6544837B1 (en) | SOI stacked DRAM logic | |
| US6590259B2 (en) | Semiconductor device of an embedded DRAM on SOI substrate | |
| JP3657921B2 (en) | Semiconductor device and manufacturing method thereof | |
| US8975729B2 (en) | Integrating through substrate vias into middle-of-line layers of integrated circuits | |
| CN104425453A (en) | 3DIC interconnect apparatus and method | |
| CN100539117C (en) | Introduce method and structure that the high K medium material is used to strengthen the SRAM operation | |
| CN102487087B (en) | Thin-film transistor applied to three-dimensional on-chip integration system and manufacturing method of thin film transistor | |
| JP2809122B2 (en) | Wiring structure of semiconductor integrated circuit and method of manufacturing the same | |
| KR100265763B1 (en) | Static random access memory device and fabriction method thereof | |
| JP3998422B2 (en) | Semiconductor integrated circuit device | |
| US20060102957A1 (en) | SER immune cell structure | |
| US8853760B2 (en) | Integrated circuit with protection from copper extrusion | |
| US6713886B2 (en) | Semiconductor device | |
| Jeong et al. | Highly manufacturable 4 Gb DRAM using using 0.11/spl mu/m DRAM technology | |
| KR102434434B1 (en) | Semiconductor Device | |
| JP2004104136A (en) | Method for manufacturing semiconductor integrated circuit device, and method for generating mask pattern | |
| TWI722546B (en) | Semiconductor device and method of fabricating the same | |
| US20230275018A1 (en) | Metal lines of hybrid heights | |
| KR100368976B1 (en) | Capacitor in semiconductor device and method for manufacturing the same | |
| KR100947564B1 (en) | Method for manufacturing ultra low coupling noise moscap dram cell | |
| JP2004146844A (en) | Method for manufacturing semiconductor integrated circuit device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20171110 Address after: Grand Cayman, Cayman Islands Patentee after: GLOBALFOUNDRIES INC. Address before: American New York Patentee before: Core USA second LLC Effective date of registration: 20171110 Address after: American New York Patentee after: Core USA second LLC Address before: American New York Patentee before: International Business Machines Corp. |