CN100539103C - 包括统一占用面积的半导体管芯封装及其制造方法 - Google Patents
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Abstract
公开了一种半导体管芯封装。它包括具有第一表面和第二表面的半导体管芯和引线框结构。模制材料可围绕管芯的至少一部分和引线框结构的至少一部分形成。可焊层可以位于该模制材料的外表面和半导体管芯的第一表面上。
Description
相关申请的交叉参考
不适用
发明背景
FLMP(引线模制封装中的倒装芯片)是功率MOSFET封装领域中正在开发的一种重要的封装技术。其电和热性能仍然是本行业中最好的。它在引线框(带栅极和源极连接)上使用倒装芯片MOSFET技术。管芯的背面在封装内露出。在某些情况下,露出的管芯背面可用作该封装的漏极端。
虽然FLMP型封装是理想的,但是FLMP型封装内的管芯尺寸可能变化。这导致带有可变占用面积(footprint)的管芯封装。在某些情况下,占用面积由在电路板上安装该封装所需的可焊表面量来确定。如果可生产带有不同管芯尺寸的封装,同时具有“统一的”占用面积而非不同的占用面积,则将是合乎需要的。
本发明的各实施例单独或共同地解决这些和其他问题。
发明概述
本发明的各实施例涉及半导体管芯封装、电气组件及方法。
本发明的一个实施例涉及一种半导体管芯封装,包括:具有第一表面和第二表面的半导体管芯;引线框结构,其中半导体管芯耦合至该引线框结构;围绕该管芯的至少一部分和引线框结构的至少一部分形成并且具有一外表面的模制材料,其中该半导体管芯的第一表面与模制材料的外表面基本平齐;以及在模制材料外表面上的可焊层。
本发明的另一个实施例涉及一种方法,包括:提供具有第一表面和第二表面的半导体管芯;将该半导体管芯附连至引线框结构,其中该半导体管芯与引线框结构相耦合;围绕该管芯的至少一部分和引线框结构的至少一部分形成模制材料,其中形成的模制材料包括一外表面,且其中该半导体管芯的第一表面与模制材料的外表面基本平齐;以及在模制材料外表面上形成可焊层。
其他实施例涉及电气组件。
随后将进一步详细描述这些和其他实施例。
附图简述
图1示出了带有不同的露出管芯表面的不同半导体管芯封装。
图2(A)至2(H)示出了用露出的管芯表面形成半导体管芯封装的工艺步骤。
图3(A)至3(D),图4(A)和4(B)示出了管芯封装的立体底视图。
图4(C)示出了被安装在电路板上的图4(A)和4(B)的管芯封装的侧截面图。
图5(A)和5(B)示出了管芯封装的立体底视图。
图5(C)示出了被安装在印刷电路板上的图5(B)所示的管芯封装的侧截面图。
图6(A)和6(B)示出了管芯封装的立体底视图。
图7(A)和7(B)示出了当被安装在电路板上时图6(A)和6(B)的管芯封装的侧截面图。
图8(A)和8(B)、图9(A)和9(B)以及图10(A)和10(B)示出了管芯封装的立体底视图。
图11示出了带有管芯的露出表面的管芯封装的侧截面图,其中该管芯的露出表面位于管芯封装顶部而非该管芯封装的底部。
图12示出了根据本发明另一实施例的管芯封装的侧截面图。
图13示出了根据本发明另一实施例的其中散热器附连至管芯封装的顶面的管芯封装的侧截面图。
详细描述
本发明的各实施例涉及用于制造半导体管芯封装、管芯封装和电气组件的方法。
根据本发明一个实施例的一个示例性半导体管芯封装可具有包括通过模制材料在该封装中露出的金属化背面的半导体管芯。可焊层在模制材料上形成以增大该管芯封装的可焊面积。通过在管芯封装上形成可焊层,能够建立统一的占用面积(即,与同其他管芯封装相关联的占用面积相对应的占用面积)而不考虑管芯封装内管芯的横向尺寸。
在模制材料被模塑之后,能够在封装内的模制材料上形成可焊层。该可焊层可以覆盖该封装的部分或全部底侧(或顶侧)。它可以与通过模制材料露出的管芯表面相接触,也可以不相接触。它还可以用作在管芯的露出的金属化背面与PCB(印刷电路板)上的导电焊盘之间的互连介质。焊料或导电粘合剂可用于将管芯封装内的可焊层耦合至PCB。顶部可焊层有助于外部散热器的附连。
可焊层可以使用任何合适的工艺来形成。例如,可焊层可通过包括溅射、蒸镀、丝网印刷、焊盘印刷和/或喷镀(例如,化学镀或电镀)的各种工艺来形成。在一个具体示例中,可焊层可以通过在封装内的模制材料上溅射籽晶层而形成。在溅射之后,可在该籽晶层上喷镀金属。诸如溅射或蒸镀等覆盖工艺可以使用掩模在管芯封装的所选区域上沉积导电材料,或者可以使用后沉积去除工艺来从不希望的区域中去除所沉积的导电材料。
可焊层还可以由一个或多个子层构成。例如,可焊层可以包括粘合子层以及在粘合子层顶部的可焊界面子层。各子层可以使用相同和不同的工艺来形成。
可焊层可以包括任何合适的材料。例如,可焊层可以包括导电墨水。导电墨水优选地用于可焊层,因为导电墨水对模制塑料材料具有良好的粘合力。导电墨水通常包括载体介质内的导电微粒。导电微粒可以包括诸如Ag、Au、Pd、Pt等贵金属及其合金,和/或诸如Sn、Cu等过渡金属及其合金。载体介质可以包括诸如环氧树脂等热固树脂。合适的导电墨水可从Dow Corning(例如,Dow Corning PI 2000和PI 2200)或其他导电墨水制造商处购得。这些导电墨水通常被沉积并在随后使用例如回流炉来固化。
虽然导电墨水具有良好的电特性,但是某些导电墨水可能不是直接可焊的。在此情况下,期望用诸如Sn等可焊界面金属来喷镀墨水以形成可焊界面层。在此情况下,可焊层可以包括固化的导电墨水层以及沉积的金属层。诸如镍等阻挡金属可以在沉积并固化的导电墨水子层和可焊界面层之间使用。
可焊层还可以具有任何合适的形式。例如,如在以下示例中示出的,可焊层可以是连续或不连续的。并且在某些实施例中,可焊层的厚度可以小于约100微米。例如,可焊层可以具有范围在约10微米至30微米之间的厚度。
半导体管芯封装内的管芯优选地包括垂直功率晶体管。垂直功率晶体管包括VDMOS晶体管和垂直双极型功率晶体管。VDMOS晶体管是具有经扩散形成的两个或多个半导体区的MOSFET(金属氧化物半导体场效应晶体管)。它具有源极区、漏极区和栅极。该器件是垂直的,这表现在其源极区和漏极区位于该半导体管芯的相对表面处。栅极可以是沟槽栅极结构或者平面栅极结构,并形成于与源极区相同的表面处。沟槽栅极结构是优选的,因为与平面栅极结构相比沟槽栅极结构更窄并占据更少的空间。在工作期间,在VDMOS器件中从源极区流到漏极区的电流基本垂直于管芯表面。在其它实施例中,半导体管芯内的晶体管可以是双极型晶体管,诸如IGBT(绝缘栅双极型晶体管)。在这些实施例中,半导体管芯的一侧可具有发射极区和基极区。该管芯的另一侧可以具有集电极区。
根据本发明各实施例的管芯封装中使用的模制材料可以包括任何合适的材料,并且可以按任何合适形式模塑到管芯封装中。合适的模制材料可以包括诸如环氧树脂等热固树脂。
具体的封装实施例在各附图中示出。
图1示出了带有露出的管芯表面的各种半导体管芯封装的底视平面图。在左侧是四个管芯封装12,分别带有与不同尺寸的管芯相对应的四个不同的露出的管芯表面12(A)。不同的尺寸构成了不同的可焊面积以及由此得到的不同的“占用面积”。使用本发明的各实施例,带有不同尺寸管芯的管芯封装12可用可焊层15涂敷以形成带有相同或基本相同占用面积的管芯封装14。
形成带有统一可焊占用面积的管芯封装具有诸多优点。首先,通过提供代用相同或基本相同占用面积的管芯封装,电子产品制造商能够使用带有统一尺寸导电焊盘的电路板。这样就不再需要适应带有不同可焊占用面积的管芯封装的专用焊盘。第二,使用带不同占用面积的管芯封装在电子产品制造商仅具有一种焊料模板掩模的情况下会导致各种制造问题。模板掩模适用于形成单一尺寸的焊料沉积。如果在电路板的导电连接盘上放置了过多的焊料并且如果该焊料接触到诸如管芯封装内的模制材料之类的不可焊区域,则该焊料可能向可焊的露出的管芯表面流动并将不会浸润该模制材料。这可能会引起部分焊料朝封装引线向外流动,进而增加引线短路的危险并增加了生产出缺陷电子零件的危险。
图2(A)至2(H)示出了可用于制造带有露出的管芯表面的管芯封装的各工艺步骤。示例性的工艺步骤可以在全文合并在此作为参考的美国专利No.6,720,642中找到,该专利被转让给与本申请相同的受让人。
如图2(A)所示,焊料突起的半导体管芯34被安装在引线框结构32的管芯附连区上。引线框结构32可以包括诸如铜等导电金属,并且可以用其他金属来喷镀或者可以不喷镀。
引线框结构32可以包括栅极引线框结构和源极引线框结构。栅极引线框结构和源极引线框结构各自可具有从其中伸出的一根或多根引线。栅极引线框结构和源极引线框结构的部分可以形成引线框结构32的管芯附连区。该管芯附连区是引线框结构32中其中附连管芯的区域。
如图2(A)所示,突起位于管芯34的第二表面34(B)上。管芯34被翻转并在随后被安装在引线框结构32的管芯附连区上。管芯34上的突起可包括Pb或Sn基焊料,并且可以具有焊球、柱等的形式,或者可以是覆盖有可焊材料的引线接合接线柱的形式。引线接合接线柱在2003年3月10日提交的美国专利申请No.10/386,211中有所描述,该申请全文合并在此作为参考。示例性的接线柱包括带有含贵金属的外部抗氧化层的铜。参考图2(A),焊料突起可以连接至管芯34的第二表面34(B)处的源极和栅极区。焊料还可以在将焊料突起的半导体管芯34附连至引线框结构32之前位于引线框结构32的管芯附连区上。
如图2(B)所示,在管芯34被安装到引线框结构32上之后,随后执行焊料回流工艺。焊料回流工艺回流半导体管芯34上的焊料突起以使得半导体管芯34与引线框结构32粘合。该回流工艺可以是其中焊料突起在回流期间不塌陷的“无塌陷”工艺。合适的回流温度和条件是本领域普通技术人员已知的。
图2(C)示出了形成封装的立体底视图,而图2(D)示出了形成封装的顶视图。如图2(C)所示,模制材料36围绕管芯34形成。管芯34的第一表面34(A)通过模制材料36露出。第一表面34(A)可以与管芯34中的MOSFET的漏极区相对应。然而,第一表面34(A)在其它实施例中也可以与任何合适的输入或输出端相对应。
在示例性模制工艺中,可以在管芯34的第一表面34(A)上放置带(未示出)(如图2(B)所示)。有带的管芯可被放置在模制腔内。模制材料可以围绕管芯34形成并且凝固。在模制之后,去除带。形成的管芯封装具有带外表面的模制材料,该外表面与露出的管芯表面34(A)基本平齐。合适的模制条件可由本领域普通技术人员来确定。
参考图2(C),还可进行排除(debar)过程。在排除过程中,多于的模制材料和引线框材料被去除。参见图2(E),随后进行水去飞边毛刺(water deflash)过程。在此步骤中,可使用喷水口从管芯封装中去除多余的模制混合物。
如图2(F)所示,可以进行栅极引线切割、条带测试和激光标记过程。可以切断封装的栅极引线以使得源极引线和栅极引线彼此电绝缘。随后还可对该封装进行测试并在随后用适当的标识信息来标记。
如图2(G)所示,随后可以进行修整、成形和单片化(sigulation)过程。最后,如图2(H)所示,进行带与盘(tape and reel)过程。修整、成形、单片化以及带与盘过程都是本领域内已知的。
图3(A)示出了带有模制材料36的半导体管芯封装50的底视图,其中模制材料36具有与半导体管芯34的第一表面34(A)基本平齐的外底面。第一表面34(A)可以是管芯34的金属化背侧的一部分。在管芯34的第一表面34(A)处的金属可以包含可焊金属。引线38从模制材料36中向外横向伸出。如图所示,第一表面34(A)在此示例中所占面积小于封装50的底面的一半。
图3(B)至3(D)示出了带有可焊层的半导体管芯封装的立体底视图。
图3(B)示出了包括可焊层22(例如,固化的可焊墨水)的管芯封装50(A),其中该可焊层22覆盖模制材料36的外表面,但是未覆盖管芯34的露出的第一表面34(A)或者仅覆盖该第一表面34(A)的一小部分。当将管芯封装50(A)安装至电路板时,焊料(未示出)可以同时接触第一表面34(A)和可焊层22。
图3(C)示出了包括可焊层22的管芯封装50(A),其中该可焊层22同时覆盖管芯34的第一表面34(A)和模制材料36。在此示例中,可焊层22是不连续的,而非连续的。
图3(D)示出了包括可焊层22的管芯封装50(A),其中该可焊层22同时在管芯34的第一表面34(A)和模制材料36上形成。在此示例中,可焊层22是连续层,而非不连续层。
图4(A)示出了带有管芯34的封装50,其中该管芯34具有通过模制材料36露出的第一表面34(A)。在此示例中,管芯34的第一表面34(A)所占面积大于封装50的底面的一半。
图4(B)示出了带有管芯34的管芯封装50(A),其中该管芯34的第一表面34(A)比图4(A)中所示的管芯的第一表面34(A)要小。为了使图4(B)中的管芯封装50(B)的占用面积与图4(A)中的管芯封装50(A)的占用面积相同,如图4(B)所示在管芯封装50内的模制材料36的外表面上形成可焊层22。于是,图4(A)和4(B)中的管芯封装50和50(a)可以具有相同的占用面积,但可以具有不同尺寸的管芯34。
图4(C)示出了被安装在印刷电路板60上的图4(A)和4(B)所示的管芯封装50和50(A)。焊料70被放置在印刷电路板60上的导电连接盘(未示出)上。如图4(C)所示,所使用的焊料70的量对于封装50和50(A)相同,即使封装50和50(A)含有不同尺寸的管芯。根据本发明一个实施例的印刷电路板60和管芯封装可以共同形成电气组件。
图5(A)示出了其上没有可焊层的管芯封装50。管芯封装50包括露出半导体管芯34的第一表面34(A)的模制材料36。引线38从模制材料36中向外横向伸出。
图5(B)示出了包括模制材料36以及在管芯34的第一表面34(A)和模制材料36上的可焊层22的管芯封装50(A)。图5(B)中的管芯34与图5(A)中的管芯34尺寸相同。如图5(C)所示,图5(B)所示的管芯封装50(A)可以被安装在印刷电路板60上。焊料70可以位于印刷电路板60上。
图6(A)和6(B)示出了带有不连续可焊层22的其他封装51(A)和51(B)。在图6(A)中示出的管芯封装51(A)具有比图6(B)中示出的管芯封装51(B)更大的管芯34。在图6(A)和6(B)中,不连续的可焊层22具有图案化矩形的形式。在其它实施例中也可以使用其他图案。
图7(A)示出了如何使用焊料70在印刷电路板60上安装管芯封装51(A)和51(B)。如图所示,用于安装封装51(A)和51(B)的焊料70的量相同,即使使用了不同尺寸的管芯34。图7(B)示出了在安装到印刷电路板上之后的管芯封装51(A)和51(B)。在标号170处,焊料70不浸润模制材料36的底面。
图8(A)示出了包括带有通过模制材料36露出的两个管芯表面134(A)和134(B)的两个管芯的管芯封装50。电绝缘区136可位于两个管芯之间。如图8(B)所示,可焊层22同时覆盖管芯表面134(A)和134(B),以将其电耦合在一起。管芯表面134(A)和134(B)可以与各管芯内的MOSFET的漏极区相对应,并且可焊层22可以构成公用漏极端。
图9(A)示出了带有不可焊聚合物层144的管芯封装59(A)。图9(B)示出了在不可焊聚合物层144上形成可焊层146之后的管芯封装59(B)。可焊层146可以通过喷镀、蒸镀、溅射等来形成。
图10(A)示出了包括溅射籽晶层150以及经由模制材料36露出的管芯背侧152的管芯封装69(A)。图10(B)示出了在籽晶层154上形成可焊界面层154之后的管芯封装69(B)。可焊界面层154可以被喷镀在不可焊层150上。
图11示出了包括围绕管芯234的各侧的模制材料238的半导体管芯封装200。管芯表面234(A)可以构成管芯234内的MOSFET的漏极端,并且可以经由模制材料238露出。表面234(A)可以与模制材料238的顶部外表面基本共面。互连(例如,焊点)236将管芯34234耦合至引线框结构240。引线240从模制材料238中向外横向伸出。
可焊和/或导电层224可以在露出的管芯表面234(A)以及引线240中的一根或多根之间提供外部漏极连接。管芯234的露出的表面234(A)电耦合至引线240中的一根或多根,使得漏极电流可以从管芯表面234(A)流至电路板60。焊料70用于将引线240耦合至电路板60。
另一可焊和/或导电层222可以位于管芯封装200的顶部。如前所述,可焊和/或导电层222可以是连续的或不连续的,并且可以覆盖封装200的上部外表面的部分或基本全部。焊料或热粘合剂(未示出)可被沉积在管芯表面234(A)和可焊和/或导电层222的顶部。随后可以将散热器HS附连至管芯封装顶部的焊料用以冷却管芯封装220。散热器HS可以包括诸如铝或铜等金属,并且可以包括或不包括散热片。
图11中示出的实施例与前述各实施例不同。在图11中,管芯234位于引线框结构顶部而非引线框结构底部。此外,与前述实施例不同,管芯234并不靠近电路板。虽然图11的实施例与前述实施例不同,但显而易见的是图11的实施例可以适用于形成带有统一占用面积的管芯封装,即使该管芯封装内的管芯具有不同尺寸的管芯。
图12和13示出了本发明其他实施例的侧截面图。在图11、12和13中,相同的标号指示相同的元件,并且不再重复对图12和13中的某些元件的描述。
图12示出了安装在电路板60上的管芯封装200。此示例中的管芯封装200具有管芯234,该管芯234带有与模制材料238的外表面238(A)基本共面的表面234(A)。可焊和/或导电层224可至少部分覆盖管芯表面234(A)并且覆盖模制材料238的至少一部分。可焊和/或导电层224能够将引线框结构的一根或多根引线240耦合至管芯234。与图11的实施例不同,可焊和/或导电层224位于封装200的底部,而非顶部。
图13示出了具有管芯234的管芯表面234(A)的管芯封装200,其中该管芯表面234(A)与模制材料238的外表面238(A)基本共面。可焊和/或导电层224可以位于封装200的顶部,并且可以将散热器HS耦合至模制材料238。另一个可焊和/或导电层224可以处于封装200的底部,并且可将管芯表面234(A)(可形成漏极区)耦合至电路板60。与前述图11和12中的实施例不同,图13的实施例具有散热器HS,并且在封装200的底部具有露出的管芯表面234(A)。
已在此使用的术语和表达是用作描述而非限制性的术语,并且使用这些术语和表达并不意味着排除所示和描述的特征的等效特征,应该认识到在所要求保护的本发明的范围内也可以有各种修改。
此外,本发明一个或多个实施例的一个或多个特征可以与本发明其他实施例的一个或多个特征组合而不背离本发明的范围。例如,参考图3至图10描述的任何特征都可并入或与图11中的特征一并使用而不背离本发明的范围。
以上提及的所有专利、专利申请、公开和描述都出于全部目的全文合并在此作为参考。所有这些都不承认是现有技术。
Claims (16)
1.一种半导体管芯封装,包括:
半导体管芯,具有第一表面和第二表面;
引线框结构,其中所述半导体管芯耦合至所述引线框结构;
模制材料,围绕所述半导体管芯的至少一部分和所述引线框结构的至少一部分形成,并且具有一外表面,其中所述半导体管芯的第一表面与所述模制材料的外表面的至少一部分基本平齐;以及
可焊层,在所述模制材料的外表面的至少一部分上。
2.如权利要求1所述的半导体管芯封装,其特征在于,所述可焊层是使用溅射、蒸镀、丝网印刷、焊盘印刷、喷镀或其任意组合而形成的。
3.如权利要求1所述的半导体管芯封装,其特征在于,所述可焊层包括导电墨水层。
4.如权利要求1所述的半导体管芯封装,其特征在于,所述半导体管芯包括垂直功率晶体管。
5.如权利要求1所述的半导体管芯封装,其特征在于,所述半导体管芯包括在所述第一表面处的漏极区以及在所述第二表面处的源极和栅极区。
6.如权利要求1所述的半导体管芯封装,其特征在于,所述引线框结构包括从所述模制材料中向外横向伸出的多根引线。
7.如权利要求1所述的半导体管芯封装,其特征在于,所述可焊层包括金属层。
8.如权利要求1所述的半导体管芯封装,其特征在于,所述可焊层具有小于约100微米的厚度。
9.如权利要求1所述的半导体管芯封装,其特征在于,所述可焊层包括多个导电层。
10.一种电气组件,包括:
如权利要求1所述的半导体管芯封装;以及
电路板,其中所述半导体管芯封装被安装在所述电路板上。
11.如权利要求10所述的电气组件,其特征在于,还包括在所述半导体管芯封装和所述电路板之间的焊料。
12.一种方法,包括:
提供具有第一表面和第二表面的半导体管芯;
将所述半导体管芯附连至引线框结构,其中所述半导体管芯与所述引线框结构相耦合;
围绕所述半导体管芯的至少一部分和所述引线框结构的至少一部分形成模制材料,其中所形成的模制材料包括一外表面,并且其中所述半导体管芯的第一表面与所述模制材料的外表面的至少一部分基本平齐;以及
在所述模制材料的外表面的至少一部分上形成可焊层。
13.如权利要求12所述的方法,其特征在于,形成所述可焊层包括溅射、蒸镀、丝网印刷、焊盘印刷、喷镀或其任意组合。
14.如权利要求12所述的方法,其特征在于,所述半导体管芯包括垂直功率晶体管。
15.如权利要求12所述的方法,其特征在于,所述半导体管芯的第一表面包括漏极区,而所述半导体管芯的第二表面包括源极和栅极区。
16.如权利要求12所述的方法,其特征在于,模制材料包括塑料材料。
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2005
- 2005-01-13 US US11/035,918 patent/US7256479B2/en not_active Expired - Fee Related
- 2005-12-07 WO PCT/US2005/044445 patent/WO2006076101A2/en active Application Filing
- 2005-12-21 TW TW094145547A patent/TW200633149A/zh unknown
- 2005-12-21 WO PCT/US2005/046613 patent/WO2006076143A2/en active Application Filing
- 2005-12-21 DE DE112005003368T patent/DE112005003368T5/de not_active Withdrawn
- 2005-12-21 JP JP2007551276A patent/JP4850184B2/ja not_active Expired - Fee Related
- 2005-12-21 KR KR1020077018333A patent/KR101204107B1/ko not_active IP Right Cessation
- 2005-12-21 CN CNB2005800462033A patent/CN100539103C/zh not_active Expired - Fee Related
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KR20070096013A (ko) | 2007-10-01 |
CN101099238A (zh) | 2008-01-02 |
US7256479B2 (en) | 2007-08-14 |
WO2006076143A3 (en) | 2006-09-14 |
JP4850184B2 (ja) | 2012-01-11 |
US20060151861A1 (en) | 2006-07-13 |
WO2006076143A2 (en) | 2006-07-20 |
KR101204107B1 (ko) | 2012-11-22 |
TW200633149A (en) | 2006-09-16 |
DE112005003368T5 (de) | 2007-12-06 |
WO2006076101A2 (en) | 2006-07-20 |
JP2008527740A (ja) | 2008-07-24 |
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