CN100538882C - A kind of method for designing of synchronous dynamic storage controller - Google Patents
A kind of method for designing of synchronous dynamic storage controller Download PDFInfo
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- CN100538882C CN100538882C CNB2005100616546A CN200510061654A CN100538882C CN 100538882 C CN100538882 C CN 100538882C CN B2005100616546 A CNB2005100616546 A CN B2005100616546A CN 200510061654 A CN200510061654 A CN 200510061654A CN 100538882 C CN100538882 C CN 100538882C
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Abstract
The method for designing of a kind of synchronous dynamic random access memory (SDRAM) controller comprises at video decode being optimized, and can increase substantially the efficient of memory data read-write, is easy to the realization of hardware, (1) address resolution optimization; (2) status register settings and use auto-precharge (Auto Pre-charge) pattern; (3) to activating the optimization of (Active) order transmitting time; (4) time interval of refreshing (Refresh) is dynamically controlled; (5) cache read write order is divided read/write slot, and read write command is concentrated respectively and sent.Its advantage is, by 4 Bank collaborative works among the SDRAM, make full use of the ability to communicate of SDRAM, satisfy the demand of mass data high speed communication, its bandwidth availability ratio carries out reaching when video decode more than 85%, can realize AVS and HD video real-time decoding H.264.The present invention not only is applicable to SDRAM and DDR SDRAM and video decode.
Description
Technical field
The present invention relates to a kind of method for designing of Memory Controller, particularly a kind of method for designing of synchronous dynamic storage controller.
Background technology
AVS is that Chinese first has the digital audio/video encoding and decoding standard of independent intellectual property right, and full name is " an infotech advanced audio/video encoding standard ".H.264 be the video encoding standard that video joint working group (JVT) exploitation that the relevant video coding expert by two ISO (International Standards Organization) of ITU-T and ISO constitutes jointly is formulated, these two kinds of standards as compared with the past video compression standard on code efficiency has all had significant raising, but meanwhile hardware realizes that complexity of decoding also rises thereupon, brings certain challenge to hardware design.
In high definition video decoding computing in real time, there are a large amount of intermediate data to preserve and to read, most data wherein, all pixel values of the image of finishing such as decoding, because data volume is very big, thereby need be saved in the chip external memory, the image of decoding after preparing against is as the reference data or be directly used in demonstration.On the other hand, the bus frequency of system and bandwidth often are subjected to physical condition and cost, the restriction of power consumption, because cost, the fastest SRAM of operating speed is unpractical.High definition video decoding chip mentioned in this article adopts the memory carrier of the outer SDRAM of sheet as decoded data, huge data volume in the intrinsic property of SDRAM and the high definition video decoding, determined to realize that real-time decoding must improve the data access efficiency of SDRAM, this just requires to design a kind of controlling schemes of SDRAM efficiently.
Summary of the invention
Technical matters to be solved by this invention is the method for designing that a kind of synchronous dynamic storage controller of the data access efficiency that can improve SDRAM is provided at above-mentioned prior art present situation.
The present invention solves the problems of the technologies described above the technical scheme that is adopted: the method for designing of a kind of synchronous dynamic random access memory (SDRAM) controller, comprise at video decode and being optimized, can increase substantially the efficient of memory data read-write, be easy to the realization of hardware, it is characterized in that: (1) address resolution optimization; (2) status register settings and use auto-precharge (Auto Pre-charge) pattern; (3) to activating the optimization of (Active) order transmitting time; (4) time interval of refreshing (Refresh) is dynamically controlled; (5) cache read write order is divided read/write slot, and read write command is concentrated respectively and sent.
To the address analytical optimization, data are evenly distributed among each Bank, make that the data of avoiding needing in time to obtain continuously all are stored among the Bank to the visit equalization of each Bank, cause frequent line activating and the wait of precharge time, lower efficiency; The map addresses formula is as follows:
If the SDRAM storer Column address of usefulness is the m position, the Row address is the n position, and the logical address of request read-write is Address[m+n-1:0]
Get X=Address[m-1:0], Y=Address[m+n-1:m], Bottom_field=Y[0]
Then the SDRAM physical address corresponding to logical address Address is:
Bank＝Bottom_field？{!Y[2]，Y[1]}:Y[2:1]
Row＝{Y[n-1:3]，Bottom_field}
Column＝X。
Status register only is set when power-up initializing one time, and uses auto-precharge (Auto Pre-charge) pattern, improve the utilization factor of order pipeline.
To activating the optimization of (Active) order transmitting time, the Active instruction of a Bank is at the Idle of all the other 3 Bank, tRCD, in the tRP time or in the interval time of two read write commands, send, reduce the conflict of order pipeline generation and etc. the time to be activated.
The time interval dynamically control in the preset threshold value scope to refreshing (Refresh) reduces the interference that refreshes in the reading and writing data process.
Read write command is carried out buffer memory, and be divided into the read time sheet and write timeslice when scheduling, read write command is concentrated transmitting time in corresponding timeslice, eliminates read-write and is connected the time waste that causes.Two counters are set, and first counter was counted sheet cycle current time, and another counter is counted the continuous idling cycle of current time sheet, carried out the switching of read/write slot when one of them counter reaches preset threshold value.
Compared with prior art, the invention has the advantages that, by 4 Bank collaborative works among the SDRAM, make full use of the ability to communicate of SDRAM, satisfy the demand of mass data high speed communication, its bandwidth availability ratio carries out reaching when video decode more than 85%, can realize AVS and HD video real-time decoding H.264.The present invention not only is applicable to SDRAM and DDR SDRAM and video decode.
Description of drawings
Fig. 1 is a SDRAM read-write sequence synoptic diagram;
Fig. 2 is the sdram controller logic diagram.
Embodiment
Embodiment describes in further detail the present invention below in conjunction with accompanying drawing.
The present invention's being implemented as follows on SDRAM is described, and realization and SDRAM on DDR SDRAM are similar.
1.SDRAM the technical scheme of controller
As shown in Figure 1,, SDRAM is gone up any data write, must activate earlier and be expert at, read and write then, also need this line precharge to close this delegation after read-write is finished to open it according to the standard of SDRAM.In order to obtain data, must extra additional period tRCD, tRP open and close the row at this data place, and whole process also is subjected to the restriction of tRC and tRAS.
Contain 4 relatively independent Bank among the SDRAM, after finishing initialization operation, except refreshing (Refresh), beyond the order such as replacement register (LMR), each Bank is essentially independent, but their shared same set of interface (order, address and data-interface).Therefore in actual applications, should guarantee the work of 4 Bank fully, guarantee the busy state of data bus as far as possible, can not cause order again, data, the data collision of address interface.
(1) the address resolution optimization of SDRAM
Through statistics, in video decode, system is at random and disperses the visit of data among the SDRAM, particularly internal memory is read maximum reference frame datas that reads, in H.264, account for 80% of total reading of data amount, the total 76-88% of the amount of reading in AVS, and average data length is no more than 3, so the data in the internal memory are evenly distributed in address resolution among 4 Bank, make the visit equalization of each module to internal memory, the data that so just can not exist all to need in time to obtain continuously all are present among the Bank, cause frequent line activating and the wait of precharge time, cause data bus to be in the idle condition of no datat.
If the SDRAM storer Column address of usefulness is the m position, the Row address is the n position, and the logical address of request read-write is Address[m+n-1:0].
Get X=Address[m-1:0], Y=Address[m+n-1:m], Bottom_field=Y[0].
Then the SDRAM physical address corresponding to logical address Address is:
Bank＝Bottom_field？{!Y[2]，Y[1]}:Y[2:1]
Row＝{Y[n-1:3]，Bottom_field}
Column＝X
After mapping is handled like this in the video data each row pixel mean allocation and the operation of each Bank intermeshed come among 4 Bank, improved bandwidth availability ratio.
(2) status register settings and use auto-precharge (Auto Pre-charge) pattern
For the maximum throughput flow of data, instruction is stitched together as far as possible, this moment, command line may produce conflict.In order to solve this point, the present invention has adopted auto-precharge (Auto Pre-charge) pattern, has reduced by an order like this, and for a Bank, the instruction that has reduced 1tCK/tRC takies.According to the difference of system frequency, this changes in the effect on the efficient between 1/8-1/12, and owing to the co-operating of 4 Bank, the increase on the tWR equal time that attracts does not thus reduce the utilization factor of data bus simultaneously.
(3) to activating the optimization of (Active) order transmitting time
Activate (Active) order and often conflict with read write command, it also is subjected to the restriction of tRRD simultaneously.The present invention is the Idle of the active of Bank instruction at all the other 3 Bank, and tRCD in the tRP time or send, guarantees that the data pipe streamline is unimpeded in the interval time of two read write commands.In order to reach this purpose, just judge whether other Bank has read-write requests in the time of must will finishing in the read-write of a Bank, make in advance and judge and the request of other Bank is arbitrated according to rule, also to consider the realization complexity of sequential and actual hardware circuit simultaneously, logic is optimized.
(4) time interval of refreshing (Refresh) is dynamically controlled
SDRAM does not lose in order to keep data wherein, need in 64ms, refresh 4096 or 8192 times, preset a threshold range among the present invention, the suitable flexible time interval of at every turn refreshing of having controlled, SDRAM can be accessed at the appointed time refreshed, and can reduce the interference that refreshes in the reading and writing data process again.
(5) cache read write order is divided read/write slot, and read write command is concentrated respectively and sent
In SDRAM, because the existence of data input register and data output register if 4 Bank are all are read or write and can closely be connected, data form the transmission of pipeline system therein.But, and then read command of write order between same Bank or the different B ank, otherwise cause the conflict of data.The present invention has designed a buffer memory to read write command, and is divided into the read time sheet and writes timeslice when scheduling, and read write command is concentrated transmitting time in corresponding timeslice, eliminates read-write and is connected the time waste that causes.The present invention is provided with two counters, and first counter was counted current cycle period, and another counter is counted continuous idling cycle of current period, reads and writes the switching of period when one of them counter reaches preset threshold value.So just can put together read-write operation respectively, guarantee that simultaneously the request responding time has the predictable upper limit, can not reduce utilization factor again because of long-time not corresponding request in a certain period.
2.SDRAM the design of controller realizes
As shown in Figure 2, sdram controller adopts modular design, has comprised moderator, initialization controller, conduit controller, refresh controller, state controller, command analysis device, response generator, modules such as recording controller.
Moderator: receive the read-write requests to SDRAM, carry out address resolution, buffer memory also carries out optimization sorting, exports to state controller.
Initialization controller: the various parameters of being responsible for configuration SDRAM when system's power-up initializing.
Refresh controller: the dynamic calculation refresh cycle is controlled the refresh cycle of SDRAM, keeps the data integrity of SDRAM.
State controller: the state exchange of 4 Bank of control, processes such as the processing of response signal.
Conduit controller: predict the operating position of pipeline according to the state of 4 Bank, coordinate the equilbrium running of 4 Bank state controllers of control, and guarantee that the command channel can not conflict, as far as possible remain valid state and not conflicting of data channel.
The command analysis device: the order that accepting state controller and initialization controller send also converts the control signal that meets the SDRAM standard to and exports to the SDRAM chip.
Response generator: the response signal of sending the SDRAM read-write requests according to state controller.
Recording controller: the command selection that the accepting state controller sends writes the data of SDRAM, and selects valid data from the data that SDRAM reads.
The present invention obtains practical application on No. two, No. one, high-definition real-time decoding SOC chip phoenix core and phoenix core.Adopt the bandwidth availability ratio of the sdram controller of this method design can reach more than 85%, collaborative work by 4 Bank among the SDRAM, utilized the ability to communicate of SDRAM greatly, satisfy the demand of high speed mass data communication, can realize AVS and HD video real-time decoding H.264.
Claims (3)
1. the method for designing of a synchronous dynamic random access memory (SDRAM) controller comprises at video decode being optimized, and can increase substantially the efficient of memory data read-write, is easy to the realization of hardware, it is characterized in that:
(1) address resolution optimization; Data are evenly distributed among each Bank, make that the data of avoiding needing in time to obtain continuously all are stored among the Bank, cause frequent line activating and the wait of precharge time, lower efficiency to the visit equalization of each Bank; The map addresses formula is as follows:
If the SDRAM storer Column address of usefulness is the m position, the Row address is the n position, and the logical address of request read-write is Address[m+n-1:0]
Get X=Address[m-1:0], Y=Address[m+n-1:m], Bottom_field=Y[0]
Then the SDRAM physical address corresponding to logical address Address is:
Bank＝Bottom_field？{！Y[2]，Y[1]}:Y[2：1]
Row＝{Y[n-1:3]，Bottom_field}
Column＝X；
(2) status register settings and use auto-precharge (Auto Pre-charge) pattern;
(3) to activating the optimization of (Active) order transmitting time; The Active of Bank instruction is at the Idle of all the other 3 Bank, tRCD, in the tRP time or in the interval time of two read write commands, send, reduce the conflict of order pipeline generation and etc. the time to be activated;
(4) time interval of refreshing (Refresh) is dynamically controlled; The time interval dynamically control in the preset threshold value scope to refreshing (Refresh) reduces the interference that refreshes in the reading and writing data process;
(5) cache read write order is divided read/write slot, and read write command is concentrated respectively and sent.
2. the method for designing of synchronous dynamic random access memory as claimed in claim 1 (SDRAM) controller, it is characterized in that: status register only is set when power-up initializing one time, and use auto-precharge (Auto Pre-charge) pattern, improve the utilization factor of order pipeline.
3. the method for designing of synchronous dynamic random access memory as claimed in claim 1 (SDRAM) controller, it is characterized in that: read write command is carried out buffer memory, and when scheduling, be divided into the read time sheet and write timeslice, read write command is concentrated transmitting time in corresponding timeslice, eliminate read-write and be connected the time waste that causes; Two counters are set, and first counter was counted current cycle period, and another counter is counted continuous idling cycle of current period, reads and writes the switching of period when one of them counter reaches preset threshold value.
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Cited By (1)
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| CN102103548A (en) * | 2011-02-22 | 2011-06-22 | 中兴通讯股份有限公司 | Method and device for increasing read-write rate of double data rate synchronous dynamic random access memory |
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| CN102117244B (en) * | 2010-01-05 | 2012-10-17 | 上海硅知识产权交易中心有限公司 | Control structure supporting double data rate (DDR) addressing of audio and video intellectual property (IP) cores |
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| CN105760315A (en) * | 2014-12-15 | 2016-07-13 | 深圳市中兴微电子技术有限公司 | Method and device improving synchronization dynamic RAM access efficiency |
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| WO2020063413A1 (en) * | 2018-09-28 | 2020-04-02 | Changxin Memory Technologies, Inc. | Chip and chip test system |
| CN111639046B (en) * | 2020-05-11 | 2022-07-12 | 中国科学院国家空间科学中心 | System and method for caching and transmitting data of far ultraviolet aurora imager in real time |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102103548A (en) * | 2011-02-22 | 2011-06-22 | 中兴通讯股份有限公司 | Method and device for increasing read-write rate of double data rate synchronous dynamic random access memory |
| CN102103548B (en) * | 2011-02-22 | 2015-06-10 | 中兴通讯股份有限公司 | Method and device for increasing read-write rate of double data rate synchronous dynamic random access memory |
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