CN100517579C - Metal oxide semiconductor device grid preparation method - Google Patents
Metal oxide semiconductor device grid preparation method Download PDFInfo
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- CN100517579C CN100517579C CNB2006101188386A CN200610118838A CN100517579C CN 100517579 C CN100517579 C CN 100517579C CN B2006101188386 A CNB2006101188386 A CN B2006101188386A CN 200610118838 A CN200610118838 A CN 200610118838A CN 100517579 C CN100517579 C CN 100517579C
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Abstract
The invention relates to a method for manufacturing a grid of a semiconductor part with a metal oxide, which comprises the following steps: a heteromorphic silicon layer is formed on a basement of a semiconductor; an overburden layer is formed on the heteromorphic silicon layer; an adulteration and an annealing processes are carried out to the heteromorphic silicon layer; a lithography glue layer is spin-coated on the overburden layer and is graphic to form a grid pattern; the overburden layer and the heteromorphic silicon layer which are not covered by the grid pattern are sculptured. The adulteration to the heteromorphic silicon layer is carried out after the overburden layer is formed through the method of the invention, which can prevent the heteromorphic silicon layer from being damaged when an ion form ashing and wet cleaning processes are carried out.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacture method of metal oxide semiconductor device grid.
Background technology
In the manufacturing process of metal oxide semiconductor device, the manufacturing process of grid is very important, represents the technology level of whole semiconductor fabrication process.Because parameters such as the live width of grid, resistivity directly influence parameters such as the speed of response, power consumption of the device of formation, semiconductor manufacturing and research and development engineer there's no one who doesn't or isn't reduce the live width of grid and resistivity as main task.For example, the patent No. is the United States Patent (USP) of US6875668B2 reduces grid by selective etch a bottom live width; Patent No. application number is that 97126460.0 Chinese patent forms grid by form the metal silicide that mixes on polysilicon, reduce the resistivity of grid, described disclosed patent is to reduce resistivity and the purpose that reduces live width by the manufacturing process of improving grid to reach.Generally speaking, the raising that reduces mainly to depend on photoetching resolution of grid live width, at present, and by means of high-resolution deep ultraviolet light source, mask plate correction technique (OPC), and infiltration type exposure technique, photoetching resolution can be accomplished 65nm, or even 45nm; The method that reduces of resistance rate is generally the polysilicon gate that adopt to mix, metal silicide gate, metal gates etc.Employing is a kind of effective and easy method to the polysilicon gate method of improving resistivity of mixing, even arrived the technology node of 65nm even 45nm, this method still is suitable for.Existing a kind of processing step that forms the doped polycrystalline silicon grid is as follows:
As shown in Figure 1, at first, provide semi-conductive substrate 10, on described Semiconductor substrate 10, form an oxide layer 12, deposition one polysilicon layer 14 on described oxide layer 12.
As shown in Figure 2, spin coating photoresist layer 16 on described polysilicon layer 14, and exposure imaging formation opening 15, doped regions is treated in the subsequent technique in described opening 15 zones.
As shown in Figure 3, the polysilicon layer 14 of described opening 15 bottoms is carried out N type ion doping, the concentration of doping and dosage are according to the electrical parameter decision of device.Doping can improve the resistivity of grid of the nmos device of formation.
After finishing doping, remove described photoresist layer 16, carry out wet-cleaned then by oxygen gas plasma (O2 plasma) ashing to described polysilicon layer 14.
As shown in Figure 4, on described polysilicon layer 14, form one deck amorphous carbon (amorphous carbon) 17, on described agraphitic carbon, form a nitrogen-oxygen-silicon layer (SiON) 18.Spin coating photoresist and the graphical gate patterns that forms on described nitrogen-oxygen-silicon layer 18 are transferred to described gate patterns on the described polysilicon layer 14 by etching then, form grid 14a as shown in Figure 5.
Because being injected into to form in the PMOS grid, N type impurity can cause the problem that the PMOS device creepage increases, thereby polysilicon is carried out need will forming by photoresist layer 16 when the N type mixes the zone covering of PMOS, after finishing described N formation doping, need to remove photoresist layer 16 as PMOS zone polysilicon protection layer by ashing and wet-cleaned, but, in ashing and wet-cleaned process, the cleaning fluid of oxygen gas plasma and wet method can destroy and attenuate through the polysilicon surface of overdoping, the reduced thickness of the grid of the feasible NMOS that forms influences the electrical of device on the one hand; On the other hand, make to form in the process of NMOS grid that damage is caused to the active area substrate of bottom in the place that is etched again and removes at described doped polycrystalline silicon layer thinner thickness in etching.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of manufacture method of metal oxide semiconductor device grid, to cause the destroyed and problem of reduced thickness of polysilicon layer in the manufacturing process that solves existing grid.
For achieving the above object, the manufacture method of a kind of metal oxide semiconductor device grid provided by the invention comprises: form polysilicon layer in the semiconductor substrate; On described polysilicon layer, form cover layer; Described polysilicon layer is mixed and anneals; Spin coating photoresist layer on described cover layer, and graphically form gate pattern; Cover layer and polysilicon layer that etching is not covered by described gate pattern.
Described cover layer is a kind of or its combination in silicon nitride, carborundum, agraphitic carbon, the nitrogen-oxygen-silicon compound.
Form described tectal method and be a kind of in chemical vapour deposition (CVD), the plasma enhanced chemical vapor deposition.
The step that described polysilicon layer is mixed is as follows:
Spin coating photoresist on described cover layer, and by the graphical opening that forms;
See through described opening and described cover layer described polysilicon layer is carried out the ion injection;
Remove described photoresist.
Described polysilicon layer is carried out N type foreign ion to be injected.
Described N type foreign ion is a kind of in phosphorus, arsenic, the antimony.
The dosage that described ion injects is 1 * 10
13To 10
18Cm
-3
The energy that described ion injects is: 10KeV to 100Kev.
The method of removing described photoresist is the oxygen gas plasma ashing.
To the described rapid thermal annealings that carry out 500 to 1500 degree after crystal silicon layer is mixed.
Compared with prior art, the present invention has the following advantages:
In the inventive method, seeing through described cover layer after finishing sedimentary cover mixes to described polysilicon layer, and the photoresist layer of formation when polysilicon layer mixes by oxygen gas plasma ashing (ash) and wet-cleaned removal, owing on described polysilicon layer, be formed with cover layer, when described photoresist layer is carried out oxygen gas plasma ashing and wet-cleaned, described oxygen gas plasma can not directly act on the polysilicon layer, wet-cleaned can not corroded described polysilicon layer yet, thereby eliminate or reduced damage described polysilicon layer, help to form the grid that thickness reaches target call, described oxygen gas plasma ashing and wet-cleaned can not cause described polysilicon layer thickness to reduce, thereby when etching forms grid, can not cause damage yet, improve the reliability of the device that forms the substrate of the source and drain areas of grid both sides.
In addition, inject owing to carry out ion again behind first sedimentary cover on the described polysilicon, described cover layer has also reduced damage and the destruction of described ion injection to described polysilicon layer as resilient coating, in subsequent annealing technology, can reduce heat budget.
Description of drawings
Fig. 1 to Fig. 5 is existing a kind of generalized section that forms each step corresponding construction of technology of doped polycrystalline silicon grid;
Fig. 6 is the flow chart of the manufacture method embodiment of metal oxide semiconductor device grid of the present invention;
Fig. 7 to Figure 16 is the generalized section of each step corresponding construction of manufacture method embodiment of metal oxide semiconductor device grid of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Fig. 6 is the flow chart of the manufacture method embodiment of metal oxide semiconductor device grid of the present invention.As shown in Figure 6, at first, provide the semiconductor substrate, the described semiconductor-based end is a kind of during silicon on polysilicon, monocrystalline silicon, amorphous silicon, the insulating barrier, SiGe composition, arsenicization are sowed.In the described semiconductor-based end, mix N type impurity or p type impurity to form the conducting channel of device.Described semiconductor-based basal surface has a thin oxide layer, and described thickness of oxide layer is 1 to 100nm, and the formation method of described oxide layer is high-temperature thermal oxidation or deposition.This oxide layer is the grid oxygen of the grid of follow-up formation.On described oxide layer, form a polysilicon layer (S100).The formation method of described polysilicon layer is a kind of in physical vapour deposition (PVD), the chemical vapour deposition (CVD), and its thickness is 800 to 3000A.
On described polysilicon layer, form cover layer (S200).Described cover layer is a kind of in silicon nitride, carborundum, agraphitic carbon, nitrogen-oxygen-silicon compound, carbon oxygen silicon compound, the carbon nitrogen silicon compound or its combination, forms described tectal method and be a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD), plasma enhanced chemical vapor deposition, the ald.Cover layer of the present invention is the stack architecture of agraphitic carbon and nitrogen-oxygen-silicon compound.The step of its formation is as follows, and at first, deposition one deck agraphitic carbon on described polysilicon layer, the thickness of described agraphitic carbon are 200 to 1000A; On described agraphitic carbon, deposit a nitrogen-oxygen-silicon compound layer then, the thickness of described nitrogen-oxygen-silicon compound layer is 100 to 800A, need be on described nitrogen-oxygen-silicon compound in the subsequent technique spin coating photoresist layer and graphical, described nitrogen-oxygen-silicon compound layer can be used as antireflecting inorganic layer and reduces that reverberation helps to form sidewall profile preferably to the influence of the profile of patterned photoresist figure in photoetching process.
Finish behind sedimentary cover on the described polysilicon layer, see through described cover layer described polysilicon layer mix (S300).Polysilicon layer mixed can change its resistivity, improves the speed of response of the grid that described polysilicon layer forms behind chemical wet etching, and reduces power consumption.Thereby, adopt the grid of polysilicon to improve its resistivity by the doping of N type.For CMOS, adopting the PMOS of N type doped polycrystalline silicon grid is buried channel road metal oxide semiconductor device, thereby can cause the problem that leakage current is excessive.Thereby, need carry out the P type to PMOS and mix to improve its resistivity.As seen, to the grid doping of cmos device the time, need optionally and carry out, promptly NMOS is carried out the N type when mixing, need block the PMOS zone, PMOS is carried out the P type when mixing, also need the nmos area territory to be blocked by photoresist by photoresist.The grid that only relates in the present embodiment NMOS carries out the doping of N type.Its step is as follows: spin coating photoresist layer on described cover layer, and by the graphical opening that forms, described open area is for forming the zone of NMOS; See through described opening and described cover layer described polysilicon layer is carried out the ion injection; After finishing described ion injection, remove described photoresist layer by ashing and wet-cleaned.In the present embodiment described polysilicon is carried out N type foreign ion and inject, described N type foreign ion is a kind of in phosphorus, arsenic, the antimony.The dosage that described ion injects is 1 * 10
13To 10
18Cm
-3, the injection energy is 10KeV to 100Kev.The method of removing described photoresist layer is oxygen gas plasma ashing and wet-cleaned, after finishing the described cover layer of deposition, described polysilicon layer is mixed in the present embodiment, and the photoresist layer of formation when described polysilicon layer is mixed by oxygen gas plasma ashing and wet-cleaned removal, owing on described polysilicon layer, be formed with cover layer, when described photoresist layer is carried out oxygen gas plasma ashing and wet-cleaned, described oxygen gas plasma can not directly act on the described polysilicon layer, wet-cleaned can not corroded described polysilicon layer yet, eliminate or reduce damage described polysilicon layer, help to form the grid that thickness reaches target call, described oxygen gas plasma ashing and wet-cleaned can not cause described polysilicon layer thickness to reduce, thereby when etching forms grid, can not cause damage yet, improve the reliability of the device that forms the substrate of the source and drain areas of grid both sides.In addition, inject owing to carry out ion again behind first sedimentary cover on the described polysilicon, described cover layer has also reduced damage and the destruction of described ion injection to described polysilicon layer as resilient coating, in subsequent annealing technology, can reduce heat budget.
Finish described polysilicon layer is carried out annealing (S400) through doped polycrystalline silicon layer to described after ion injects, the method for annealing described in the present embodiment is rapid thermal annealing (RTA).Because in ion implantation process, the ion of high energy can cause the destruction of lattice in the described polysilicon layer when being injected in the described polysilicon layer and form defective, and the foreign ion that injects also may be free in the interstitial void position of described polysilicon layer, needs could activate by high-temperature annealing step.Described doped polycrystalline silicon layer is carried out rapid thermal annealing,, can repair the lattice structure of in ion implantation process, destroying on the one hand by the high temperature of 500 to 1500 degree; Also can make the foreign ion of injection move to lattice position on the other hand and be activated.Described rapid thermal annealing generally carries out in nitrogen or other inert gas environment, can not be subjected to the pollution of oxidation or other external environment condition to protect the whole semiconductor-based end.
Described polysilicon layer is carried out being cooled to after the rapid thermal annealing room temperature, spin coating one photoresist layer on described cover layer then, and form gate pattern (S500) by exposure imaging.
By cover layer and the polysilicon layer that etching is not protected by described gate pattern, in described polysilicon layer, form grid (S600).Further form side wall protective layer in described grid both sides, and in described grid substrate on two sides, mix formation source electrode and drain electrode, metal oxide semiconductor transistor promptly formed.Among the embodiment of the inventive method; by at first forming cover layer at described polysilicon layer; and then described polysilicon layer mixed; protect described polysilicon layer not to be subjected to the influence of oxygen gas plasma ashing and wet-cleaned, helped forming the metal oxide semiconductor device of reliability height, good stability.
The joint profile is described in detail the embodiment of metal oxide semiconductor device grid manufacture method of the present invention below.Fig. 7 to Figure 16 is the generalized section of each step corresponding construction of the embodiment of the manufacture method of metal oxide semiconductor device grid of the present invention.
As shown in Figure 7, at first, provide semiconductor substrate 20, a kind of for during silicon, SiGe composition, arsenicization are sowed on polysilicon, monocrystalline silicon, amorphous silicon, the insulating barrier of the described semiconductor-based end 20.In the described semiconductor-based end 20, mix N type impurity or p type impurity to form the conducting channel of device.Surface, the described semiconductor-based ends 20 has a thin oxide layer 22, and the thickness of described oxide layer 22 is 1 to 100nm, and the formation method of described oxide layer 22 is high-temperature thermal oxidation or deposition.This oxide layer 22 is the grid oxygen of the grid of follow-up formation.
As shown in Figure 8, on described oxide layer 22, form a polysilicon layer 24.The formation method of described polysilicon layer 24 is a kind of in physical vapour deposition (PVD), the chemical vapour deposition (CVD), and its thickness is 800 to 3000A.
As shown in Figure 9, on described polysilicon layer 24, form cover layer.Described cover layer is a kind of in silicon nitride, carborundum, agraphitic carbon, nitrogen-oxygen-silicon compound, carbon oxygen silicon compound, the carbon nitrogen silicon compound or its combination, forms described tectal method and be a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD), plasma enhanced chemical vapor deposition, the ald.Cover layer of the present invention is the stack architecture of agraphitic carbon 28 and nitrogen-oxygen-silicon compound layer 30.The step of its formation is as follows, and at first, deposition one deck agraphitic carbon 28 on described polysilicon layer 24, the thickness of described agraphitic carbon 28 are 200 to 1000A; On described agraphitic carbon 28, deposit a nitrogen-oxygen-silicon compound layer 30 then, the thickness of described nitrogen-oxygen-silicon compound layer 30 is 100 to 800A, need be on described nitrogen-oxygen-silicon compound layer 30 in the subsequent technique spin coating photoresist layer and graphical, described nitrogen-oxygen-silicon compound layer 30 can be used as antireflecting inorganic layer, reduce that reverberation helps to form sidewall profile preferably to the influence of the profile of patterned photoresist figure in photoetching process.
After finishing sedimentary cover on described polysilicon layer 24 (being agraphitic carbon 28 and nitrogen-oxygen-silicon compound 30 stack architectures in the present embodiment), see through described cover layer described polysilicon layer 24 is mixed.Polysilicon layer 24 mixed can change its resistivity, improves the speed of response of the grid that described polysilicon layer 24 forms behind chemical wet etching, and reduces power consumption.Thereby, adopt the grid of polysilicon layer to improve its resistivity by the doping of N type.For CMOS, adopting the PMOS of N type doped polycrystalline silicon grid is buried channel road metal oxide semiconductor device, can cause the problem that leakage current is excessive.Thereby, need carry out the P type to PMOS and mix to improve its resistivity.As seen, to the grid doping of cmos device the time, need optionally and carry out, promptly NMOS is carried out the N type when mixing, need block the PMOS zone, PMOS is carried out the P type when mixing, also need the nmos area territory to be blocked by photoresist by photoresist.The grid that only relates in the present embodiment NMOS carries out the doping of N type.Its step is as follows: go up spin coating photoresist layer 32 as shown in figure 10 at described cover layer (being agraphitic carbon 28 and nitrogen-oxygen-silicon compound 30 stack architectures in the present embodiment), and by the graphical opening 33 that forms, described opening 33 zones are for forming the zone of NMOS; Then, as shown in figure 11, see through described opening 33, nitrogen-oxygen- silicon compound layer 30 and 28 pairs of described polysilicon layers 24 of agraphitic carbon and carry out the ion injection; After finishing described ion injection, as shown in figure 12, remove described photoresist layer 32 by ashing and wet-cleaned.In the present embodiment described polysilicon layer 24 is carried out N type foreign ion and inject, described N type foreign ion is a kind of in phosphorus, arsenic, the antimony.The dosage that described ion injects is 1 * 10
13To 10
18Cm
-3, the injection energy is 10KeV to 100Kev.The method of removing described photoresist layer 32 is oxygen gas plasma ashing and wet-cleaned, in the present embodiment behind the cover layer of finishing deposition described agraphitic carbon 28 and nitrogen-oxygen-silicon compound layer 30 stack architectures, described polysilicon layer 24 is mixed, and the photoresist layer 32 of formation when described polysilicon layer 24 is mixed by oxygen gas plasma ashing and wet-cleaned removal, owing on described polysilicon layer 24, be formed with cover layer (being agraphitic carbon 28 and nitrogen-oxygen-silicon compound 30 stack architectures in the present embodiment), when described photoresist 32 is carried out oxygen gas plasma ashing and wet-cleaned, described oxygen gas plasma can not directly act on the described polysilicon layer 24, wet-cleaned can not corroded described polysilicon layer 24 yet, eliminate or reduce damage, help to form the grid that thickness reaches target call described polysilicon layer 24; On the other hand, described oxygen gas plasma ashing and wet-cleaned can not cause described polysilicon layer 24 thickness to reduce, thereby when etching forms grid, can not cause damage to the substrate of the source and drain areas of grid both sides yet, have improved the reliability of the device that forms.
Finish described polysilicon layer is carried out annealing (S400) through doped polycrystalline silicon layer 24 to described after ion injects, the method for annealing described in the present embodiment is rapid thermal annealing (RTA).Because in ion implantation process, the ion of high energy can cause the destruction of lattice in the described polysilicon layer 24 when being injected in the described polysilicon layer 24 and form defective, and the foreign ion that injects also may be free in the interstitial void position of described polysilicon layer 24, needs could activate by high-temperature annealing step.Described doped polycrystalline silicon layer 24 is carried out rapid thermal annealing,, can repair the crystal silicon structure of in ion implantation process, destroying on the one hand by the high temperature of 500 to 1500 degree; Also can make the foreign ion of injection move to lattice position on the other hand and be activated.Described rapid thermal annealing generally carries out in nitrogen or other inert gas environment, can not be subjected to the pollution of oxidation or other external environment condition to protect the whole semiconductor-based end.
As shown in figure 13, described polysilicon layer 24 is carried out being cooled to after the rapid thermal annealing room temperature, spin coating one photoresist layer 34 on described cover layer then, and form as shown in figure 14 gate patterns 34a by exposure imaging.
As shown in figure 15, etching forms grid 24a not by the cover layer (being agraphitic carbon 28 and nitrogen-oxygen-silicon compound 30 stack architectures in the present embodiment) and the polysilicon layer 24 of described gate pattern 34a protection in described polysilicon layer 24.Further form side wall protective layer (side wall protective layer described in the present embodiment is the N-O structure of silicon nitride layer 36 and oxide layer 38) as shown in figure 16 in described grid 24a both sides; and in described grid 24a substrate on two sides, mix formation source electrode and drain electrode, promptly formed metal oxide semiconductor transistor.Among the embodiment of the inventive method; by at first on described polysilicon layer 24, forming cover layer (being agraphitic carbon 28 and nitrogen-oxygen-silicon compound 30 stack architectures in the present embodiment); and then described polysilicon layer 24 mixed; protect described polysilicon layer 24 not to be subjected to the influence of oxygen gas plasma ashing and wet-cleaned, helped forming the metal oxide semiconductor device of reliability height, good stability.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (9)
1, a kind of manufacture method of metal oxide semiconductor device grid comprises:
In the semiconductor substrate, form polysilicon layer;
On described polysilicon layer, form cover layer;
Described polysilicon layer is mixed and anneals;
Spin coating photoresist layer on described cover layer, and graphically form gate pattern;
Cover layer and polysilicon layer that etching is not covered by described gate pattern; Wherein, the step that described polysilicon layer is mixed is as follows:
Spin coating photoresist on described cover layer, and by the graphical opening that forms;
See through described opening and described cover layer described polysilicon layer is carried out the ion injection;
Remove described photoresist.
2, the manufacture method of metal oxide semiconductor device grid as claimed in claim 1 is characterized in that: described cover layer is a kind of or its combination in silicon nitride, carborundum, agraphitic carbon, the nitrogen-oxygen-silicon compound.
3, the manufacture method of metal oxide semiconductor device grid as claimed in claim 2 is characterized in that: form described tectal method and be a kind of in chemical vapour deposition (CVD), the plasma enhanced chemical vapor deposition.
4, the manufacture method of metal oxide semiconductor device grid as claimed in claim 1 is characterized in that: described polysilicon layer is carried out N type foreign ion inject.
5, the manufacture method of metal oxide semiconductor device grid as claimed in claim 4 is characterized in that: described N type foreign ion is a kind of in phosphorus, arsenic, the antimony.
6, the manufacture method of metal oxide semiconductor device grid as claimed in claim 1 is characterized in that: the dosage that described ion injects is 1 * 10
13To 10
18Cm
-3
7, the manufacture method of metal oxide semiconductor device grid as claimed in claim 1 is characterized in that: the energy that described ion injects is: 10KeV to 100Kev.
8, the manufacture method of metal oxide semiconductor device grid as claimed in claim 1 is characterized in that: the method for removing described photoresist is the oxygen gas plasma ashing.
9, the manufacture method of metal oxide semiconductor device grid as claimed in claim 1 is characterized in that: to the described rapid thermal annealings that carry out 500 to 1500 degree after crystal silicon layer is mixed.
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| CNB2006101188386A CN100517579C (en) | 2006-11-28 | 2006-11-28 | Metal oxide semiconductor device grid preparation method |
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Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101783298B (en) * | 2009-01-21 | 2012-11-14 | 中国科学院微电子研究所 | Method for inhibiting growth of high-k gate dielectric/metal gate structure interface layer |
| CN102376552B (en) * | 2010-08-24 | 2014-03-12 | 中芯国际集成电路制造(北京)有限公司 | Method for preventing grid electrode from damage in ion implantation process |
| CN102956461B (en) * | 2011-08-30 | 2015-03-11 | 中芯国际集成电路制造(上海)有限公司 | Forming method of grid electrode |
| CN102354669B (en) * | 2011-10-25 | 2013-02-27 | 上海华力微电子有限公司 | Production method of silicon nano-wire device |
| CN103377901A (en) * | 2012-04-28 | 2013-10-30 | 无锡华润上华科技有限公司 | Polysilicon grid forming method |
| CN103390559B (en) * | 2012-05-09 | 2016-08-31 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of semiconductor device |
| CN104425239B (en) * | 2013-09-09 | 2017-10-17 | 中芯国际集成电路制造(上海)有限公司 | The preparation method of semiconductor devices |
| CN103668081A (en) * | 2013-12-09 | 2014-03-26 | 京东方科技集团股份有限公司 | Crystal oscillation sheet cleaning equipment |
| CN106952807B (en) * | 2016-01-06 | 2020-08-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US11362117B2 (en) | 2019-12-23 | 2022-06-14 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Manufacturing method of array substrate, array substrate, and display device |
| CN110993564A (en) * | 2019-12-23 | 2020-04-10 | 深圳市华星光电半导体显示技术有限公司 | Manufacturing method of array substrate, array substrate and display device |
| CN113113291A (en) * | 2021-04-06 | 2021-07-13 | 武汉新芯集成电路制造有限公司 | Substrate cleaning method |
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