CN100483678C - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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CN100483678C
CN100483678C CNB2007100970205A CN200710097020A CN100483678C CN 100483678 C CN100483678 C CN 100483678C CN B2007100970205 A CNB2007100970205 A CN B2007100970205A CN 200710097020 A CN200710097020 A CN 200710097020A CN 100483678 C CN100483678 C CN 100483678C
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interlevel dielectric
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考什克·A·库玛尔
凯文·S.·佩特拉卡
斯特凡·格鲁诺夫
劳伦斯·A·克莱文格
维德赫亚·拉马昌德拉
泽奥多鲁斯·E.·斯坦达耶尔特
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    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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Abstract

一种半导体结构，包括多条形成于层间电介质(ILD)层内的导线，和一个形成于ILD层和导线上面的非平面帽层，其中该帽层在导线之间的位置处相对于导线抬高。

Description

半导体结构及其形成方法
技术领域
本发明大体上涉及半导体器件处理技术，更特别地，涉及一种用于降低半导体横向边缘电容(lateral fringe capacitance)的结构及其形成方法。
背景技术
半导体工业中在给定的面积内形成越来越多电路器件，这一持续不断的趋势使得单个集成电路以及采用集成电路的电子器件的性能显著提高。在典型的集成电路中，单个集成电路元件或元件群一般通过金属化处理彼此电连接，在金属化处理中，沉积金属层并进行构图从而形成按照设计完成电路的金属线。在经过构图的金属层内形成的各个金属线通过称作层间电介质的层彼此隔离。这些层间电介质隔离金属线与其它金属线(不论位于相同的还是不同的金属层内)及其它电路元件之间发生不良的电接触。
典型的双镶嵌结构的制造过程如下：通过沉积电介质材料，经光刻和刻蚀限定线路和通道(via)，然后金属化以便填充该经过构图的线路和通道，对过多的金属进行抛光完成线路。在化学机械抛光(CMP)之后，表面接***面，载流线路与相邻的线路隔离，从而完成电路。在这里，典型地对铜金属层进行盖顶，随后沉积电介质层。
然而，上述集成电路密度增加的一个不良副效应是给定金属层内相邻金属线之间存在寄生横向电容。这一不必要的电容会使电路性能变慢，因为会产生太多不需要的电荷，从而使必要电路元件处电荷的建立变慢。
图1图解了部分形成的传统集成电路器件100的剖面图。在层间电介质(ILD)层(例如二氧化硅)102中具有多个导电金属线104形成于其中。利用平面化步骤将金属填充材料104抛光直到ILD层102的顶部之后，在其上面形成一个电介质帽层106，例如NBLoK(氮掺杂碳化硅)。当ILD层102的介电常数的量级是大约2.5-3.0，NBLoK帽层的介电常数为大约6.0。
结构100相邻金属线104之间的横向电容(C)受到数个因素的影响，其中的两个是：(1)由于线路102之间ILD材料102导致的电容，和(2)由于所覆盖的NBLoK层106导致的边缘电容。尽管由于ILD材料102产生的电容能够通过用k更低的电介质代替二氧化硅加以降低，但是如果仅仅简单地替换NBLoK帽层则要困难得多，因为这个层行使大量的功能，使得难以用一种材料加以替换。
因此，如果能够使用某种方式，在保留使用介电常数较高的帽层的优点的条件下，降低金属线路内横向电容的边际贡献则是令人期待的。
发明内容
前面讨论的先前技术的缺点和缺陷可以通过一种用于形成半导体结构的方法加以克服或减轻。在一个示例性实施例中，该方法包括：在上面形成有硬掩模的层间电介质(ILD)层内限定多条导线，并使导线的填充材料凹陷到低于ILD层顶部的程度。在凹陷的填充材料的顶部形成一个保护性绝缘层，并在硬掩模层内限定一个穹形图形，借此除去保护性绝缘层。除去硬掩模层，从而将穹形图形转移到ILD层的顶部，并在ILD层和导线上面形成一个帽层，其中该帽层采用穹形图案的形式。
在另一个实施例中，半导体结构包括多条形成于层间电介质(ILD)层内的导线，和一个形成于ILD层和导线上面的非平面帽层，其中在导线之间的位置处，该帽层相对于导线抬高。
附图说明
参考示例图，其中在一些图中相似的元件用相似的数字标注：
图1是部分形成的传统集成电路器件的剖面图；
图2是图解用于降低半导体器件中横向边缘电容的方法的处理流程图；和
图3(a)-3(g)是根据图2所述方法用于降低横向边缘电容的半导体结构的剖面图。
具体实施方式
本文公开的是一种用于降低半导体器件的金属导线之间横向电容边缘分量的方法和结构。简而言之，形成一个穹形帽结构，从而在线路之间的位置处从金属线路的顶部物理地拱起一个k较高的帽层，借此降低器件的总体横向电容。
现在同时参考图2的流程图200和图3(a)-3(g)的处理程序，图解了制造穹形电容结构的方法。从图2的框202和图3(a)开始，通过CMP操作制造双(或单)镶嵌结构。特别地，ILD层302上面形成有硬掩模层303，随后构图线路304，线路304被导电材料(例如铜)填充。可以对用于使铜填充物平面化的特殊CMP处理进行改变或者不进行改变，以便保留硬掩模层303。
然后，如图2的框204和图3(b)所示，使铜填充材料凹陷经过硬掩模层303的底部，直到其最终的高度低于ILD层302的顶部。该凹陷步骤可以通过一种或多种不同的方法(例如湿法刻蚀、干法刻蚀、CMP等)加以实现。在此阶段，非共形或共形地沉积保护性绝缘材料306(例如SiO2)，如图2的框206和图3(c)所示。然后在绝缘材料306上执行平面化步骤，直到硬掩模层303的顶部，如图2的框208和图3(d)所示。结果，绝缘材料306的U形部分提供一个在随后的处理步骤期间保护铜线304的机构。
接着参考图2的框210和图3(e)，执行各向同性(非定向)刻蚀，从而除去牺牲绝缘材料部分306，并将硬掩模层303的角成形为圆形、穹形图形308。然后通过各向异性(定向)刻蚀将这些穹形图形308转移到ILD层302内，如图2的框212和图3(f)所示。尽管各向异性转移刻蚀在附图中被描绘成一个分离的步骤，但是各向同性圆化刻蚀和各向异性转移刻蚀能够在单一的步骤中加以执行。
最后，如图2的框214和图3(g)所示，在非平面结构上共形沉积一个帽层310(例如NBLoK)，这样保留了穹形图形308。与图1的传统平面结构100相比，线304之间帽层310的部分沿着向上的方向拱起，借此使高k层与导线物理地相离。进而，由于穹形的高度，使得线的总横向电容降低了大约5％。
在制造单和双镶嵌结构期间进行刻蚀处理以提供尖锐的角是令人期望的。随后在圆化结构上的金属化将趋向于引起增加的短路(shorts)，因为负担在CMP时将衬垫残余清除到器件人工公差范围。通过以上述方式制造该结构，使Cu-Cu间隔保持在设计原则规范内，同时能够实现穹形绝缘体间隔的制造。
尽管本发明是参考优选的实施例加以说明的，但是本领域的技术人员能够理解，在不背离本发明范围的前提下，可以有各种改变，并且能够用等价物替换其元件。此外，在不背离本发明基本范围的前提下，可以进行许多修改以适应本发明教授内容的特殊条件或材料。因此，我们期望，本发明并不仅限于作为用于执行本发明的最佳模式所公开的特殊实施例，而是本发明包括处于附属权利要求范围内的全部实施例。

Claims (11)

1.一种用于形成半导体结构的方法，该方法包括：
在上面形成有硬掩模层的层间电介质层内限定多条导线；
将导线的填充材料凹陷到低于所述层间电介质层的顶部的水平；
在所述凹陷的填充材料的顶部形成保护性绝缘层；
在所述硬掩模层内限定穹形图形，借此除去所述保护性绝缘层；
除去所述硬掩模层，以便将所述穹形图形转移到所述层间电介质层的顶部；和
在所述层间电介质层和所述导线上方形成帽层，其中所述帽层采取所述穹形图形的形式。
2.根据权利要求1的方法，其中所述穹形图形位于所述导线之间。
3.根据权利要求1的方法，其中所述在所述硬掩模层内限定穹形图形，借此除去所述保护性绝缘层的步骤包括各向同性地刻蚀所述硬掩模层和所述保护性绝缘层。
4.根据权利要求3的方法，其中所述除去所述硬掩模层，以便将所述穹形图形转移到所述层间电介质层的顶部的步骤进一步包括各向异性刻蚀所述硬掩模层。
5.根据权利要求1的方法，其中所述帽层具有比所述层间电介质层更大的介电常数。
6.根据权利要求5的方法，其中所述层间电介质层包括二氧化硅，而所述帽层包括氮掺杂碳化硅。
7.根据权利要求1的方法，其中所述在所述凹陷的填充材料的顶部形成保护性绝缘层的步骤进一步包括沉积牺牲绝缘材料，将该绝缘材料平面化到所述硬掩模层，从而在所述导线上形成所述绝缘材料的U形部分。
8.根据权利要求7的方法，其中所述绝缘材料包括二氧化硅。
9.一种半导体结构，包括：
多条导线，其形成于层间电介质层内；和
非平面帽层，其形成于所述层间电介质层和所述导线的上方，其中所述帽层在所述导线之间的位置处相对于所述导线抬高。
10.根据权利要求9的半导体结构，其中所述帽层在所述导线之间的所述位置处具有穹形形状。
11.根据权利要求9的半导体结构，其中所述层间电介质层包括二氧化硅，而所述帽层包括氮掺杂的碳化硅。
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CN1624897A (zh) * 2003-12-03 2005-06-08 三星电子株式会社 采用牺牲金属氧化物层形成双镶嵌金属互连的方法

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