CN100452412C

CN100452412C - Pixel structure and manufacture method and photoelectronic device with the pixel structure and manufacture method

Info

Publication number: CN100452412C
Application number: CNB2007101058635A
Authority: CN
Inventors: 俞善仁; 彭中宏
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2007-05-31
Filing date: 2007-05-31
Publication date: 2009-01-14
Anticipated expiration: 2027-05-31
Also published as: CN101060127A

Abstract

The disclosed pixel structure comprises at least: one grid line, one data bus, one TFT formed on the grid line to couple the grid line and data bus, and one pixel electrode coupling with the TFT, wherein both the grid line and data bus are formed on the substrate alternatively.

Description

Dot structure and manufacture method and contain the electrooptical device and the manufacture method of dot structure

Technical field

The invention relates to a kind of display, particularly relevant for a kind of dot structure and manufacture method thereof in the display.

Background technology

Because flat-panel screens now, as LCD (LCD), plasma scope (PDP) and organic light emitting diode display (OLED display) etc., no matter on characteristics such as resolution, weight, thickness, reaction speed and power consumption, all be better than traditional cathode ray tube (Cathode Ray Tube, CRT) display is so flat-panel screens replaces traditional cathode-ray tube display gradually.Add, the technological progress of flat-panel screens is in recent years advanced by leaps and bounds, and along with the continuous expansion of electronic product purposes, so the application of flat-panel screens also more and more is extensive.

Known flat-panel screens comprises a plurality of dot structures, and each dot structure such as Fig. 1 and shown in Figure 2, wherein Fig. 1 is arranged on the public electrode for storage capacitors, and Fig. 2 is arranged on the gate line for storage capacitors.See also Figure 1A and Fig. 2 B, it is a known pixel structure schematic top plan view.As shown in the figure, known pixel structure 100 comprises a gate line 120, a data wire 130, a thin-film transistor 140, a pixel electrode 160 and a common wire 170, gate line 120, data wire 130, thin-film transistor 140, pixel electrode 160 and common wire 170, and be arranged on one first substrate (figure does not show).Wherein, gate line 120 is interlaced with data wire 130.Thin-film transistor 140 comprises a grid (figure does not show), one source pole 144, one drain electrode 146 and semi-conductor layer 148, the grid of thin-film transistor 140 is constituted by part of grid pole line 120, and the semiconductor layer 148 of thin-film transistor 140 is corresponding to the grid of thin-film transistor 140, be provided with an insulating barrier (figure does not show) between the grid of semiconductor layer 148 and thin-film transistor 140, the source electrode 144 of thin-film transistor 140 and drain electrode 146 are arranged at the both sides of semiconductor layer 148 respectively, and extend to gate line 120 both sides respectively, and couple data wire 130 and pixel electrode 160 respectively, and pixel electrode 160 couples drain electrode 146 via a through hole 149.Common wire 170 is set in parallel on first substrate with

gate line

120, and 170 of pixel electrode 160 and common wires form a storage capacitors 162.

Accept above-mentionedly, because pixel electrode 160 be the electrically conducting transparent material, so the zone of pixel electrode 160 is transmission region, yet common wire 170 can obstruct part transmission regions.Now in order to prevent the situation of pixel generation light leak, first substrate or can around corresponding to pixel electrode 160, a black matrix" 190 be set with respect to one second substrate of first substrate (figure does not show), shown in Figure 1B, spill around transmission region to intercept light, so pixel electrode 160 is not subjected to black matrix" 190 zone that covers and the zone that not intercepted by common wire 170, is viewing area 180.Because the drain electrode 146 and/or the source electrode 144 whole transmission regions that are arranged in pixel electrode 160 places of dot structure 100 commonly used, moreover drain 146 with the material of source electrode 144 be light tight material, so drain 146 with source electrode 144 also stopped part light, so can reduce the viewing area 180 of dot structure 100, also promptly cause the aperture opening ratio (aperture ratio) of dot structure 100 to reduce, and also can cause light transmittance to reduce.

See also Fig. 2 A and Fig. 2 B, it is the schematic top plan view of the known pixel structure of tool etch-stop type thin-film transistor.As shown in the figure, the difference of Figure 1A and Fig. 2 A is that the thin-film transistor 240 of the dot structure 200 of Fig. 2 A is an etch-stop type thin-film transistor, and be arranged at a side of gate line 220, etch-stop type thin-film transistor 240 has an etching stopping layer 241, it is corresponding to the grid 242 of thin-film transistor 240, and be arranged on the semiconductor layer (figure does not show) of thin-film transistor 240, the source electrode 244 of thin-film transistor 240 and drain electrode 246 are arranged at the both sides of etching stopping layer 241 respectively.Wherein, source electrode 244 is coupled to data wire 230, and pixel electrode 260 couples drain electrode 246 via through hole 249.In addition, the pixel electrode 260 of the dot structure 200 of Fig. 2 A also extends and is arranged on the next stage gate line 220, and forms a storage capacitors 262.Because the thin-film transistor 240 of the dot structure 200 of Fig. 2 A is arranged at a side of gate line 220, therefore shown in Fig. 2 B, black matrix" 290 can be because cover film transistor 240 and cover the side regions of gate line 220 on every side, and the aperture opening ratio that the viewing area 280 of reduction dot structure 200 causes dot structure 200 because of the position of thin-film transistor 240 dwindles reduces, and also can cause light transmittance to reduce.

Summary of the invention

Main purpose of the present invention is the electrooptical device and the manufacture method thereof that a kind of dot structure and manufacture method thereof are provided and comprise this dot structure, and it increases the viewing area of dot structure, to increase the aperture opening ratio of dot structure.

Secondary objective of the present invention is the electrooptical device and the manufacture method thereof that a kind of dot structure and manufacture method thereof are provided and comprise this dot structure, and it is arranged at gate line for utilizing thin-film transistor, to increase the aperture opening ratio of dot structure.

The present invention is about a kind of dot structure, it comprises a substrate, interlaced in fact at least one gate line and at least one data wire, at least one thin-film transistor and at least one pixel electrode are set on it, wherein thin-film transistor is positioned at gate line, and thin-film transistor couples gate line and data wire and pixel electrode.

The present invention is about a kind of one pixel structure process method, it provides a substrate earlier, and form at least one gate line, at least one data wire, at least one thin-film transistor and at least one pixel electrode on substrate, wherein gate line and data wire are interlaced in fact, thin-film transistor is formed at gate line and is relative with gate line, and couples gate line, data wire and pixel electrode.

The present invention is about a kind of electrooptical device, and it has dot structure of the present invention.

The present invention is about a kind of manufacture method of electrooptical device, and it has the formation method of dot structure of the present invention.

The present invention is above-mentioned to be become apparent with other purpose, feature and advantage in order to allow, and preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.

Description of drawings

Figure 1A is a known pixel structure schematic top plan view;

Figure 1B is the schematic top plan view of viewing area of the dot structure of Figure 1A;

Fig. 2 A is known schematic top plan view with dot structure of etch-stop type thin-film transistor;

Fig. 2 B is the schematic top plan view of viewing area of the dot structure of Fig. 2 A;

Fig. 3 A is the schematic top plan view of an embodiment of dot structure of the present invention;

Fig. 3 B is the schematic top plan view of viewing area of the dot structure of Fig. 3 A;

Fig. 4 is the cutaway view of the embodiment of Fig. 3 A;

Fig. 5 is the cutaway view of another embodiment of Fig. 3 A;

Fig. 6 is the cutaway view of another embodiment of Fig. 3 A;

Fig. 7 is the cutaway view of another embodiment of dot structure of the present invention;

Fig. 8 is the schematic top plan view of another embodiment of dot structure of the present invention;

Fig. 9 is the cutaway view of the embodiment of Fig. 8;

Figure 10 A is the schematic top plan view of another embodiment of dot structure of the present invention;

Figure 10 B is the schematic top plan view of viewing area of the dot structure of Figure 10 A;

Figure 11 is the cutaway view of the embodiment of Figure 10 A;

Figure 12 A is the schematic top plan view of another embodiment of dot structure of the present invention;

Figure 12 B is the schematic top plan view of viewing area of the dot structure of Figure 12 A;

Figure 13 is the cutaway view of the embodiment of Figure 12 A;

Figure 14 is the cutaway view of another embodiment of Figure 12 A;

Figure 15 is the cutaway view of another embodiment of Figure 12 A;

Figure 16 is the schematic top plan view of another embodiment of dot structure of the present invention;

Figure 17 is the cutaway view of the embodiment of Figure 16; And

Figure 18 is the schematic top plan view of an embodiment of electrooptical device of the present invention.

Wherein, Reference numeral:

100 dot structures, 314 insulating barriers, 120 gate lines

130 data wires, 320 gate lines, 412 dummy pattern

140 thin-film transistors, 322 insulating barriers, 420 gate lines

144 source electrodes, 330 data wires, 422 insulating barriers

146 drain electrodes, 332 doping semiconductor layers 424 are stretched portion

148 semiconductor layers, 334 doping semiconductor layers, 430 data wires

149 through holes, 340 thin-film transistors, 432 doping semiconductor layers

160 pixel electrodes, 344 source electrodes, 434 doping semiconductor layers

162 storage capacitors, 346 drain electrodes, 440 thin-film transistors

170 common wires, 348 semiconductor layers, 444 source electrodes

349 through holes, 446 drain electrodes of 180 viewing areas

190 black matrix"s, 352 protective layers, 448 semiconductor layers

200 dot structures, 360 pixel electrodes, 449 through holes

Layer 452 protective layer of 220 gate lines, 362 tool dielectric coefficients

230 data wires, 364 insulating barriers, 454 through holes

240 thin-film transistors, 366 electrodes, 460 pixel electrodes

The layer of 244 source electrodes, 370 common wires, 462 tool dielectric coefficients

246 drain electrodes, 372 storage capacitors, 470 common wires

249 through holes, 380 black matrix"s, 472 storage capacitors

260 pixel electrodes, 381 resilient coatings, 480 black matrix"s

262 storage capacitors, 382 viewing areas, 481 resilient coatings

280 viewing areas, 384 color filter layers, 484 color filter layers

300 dot structures, 386 flatness layers, 486 flatness layers

310 first substrates, 388 public electrodes, 488 public electrodes

312 dummy pattern, 390 second substrates, 490 second substrates

512 dummy pattern, 400 dot structures, 500 dot structures

520 gate lines, 410 first substrates, 510 first substrates

530 data wires, 630 data wires, 730 data wires

532 doping semiconductor layers, 632 doping semiconductor layers, 732 doping semiconductor layers

534 doping semiconductor layers, 634 doping semiconductor layers, 734 doping semiconductor layers

540 thin-film transistors, 640 thin-film transistors, 740 thin-film transistors

544 source electrodes, 644 source electrodes, 744 source electrodes

546 drain electrodes, 646 drain electrodes, 746 drain electrodes

548 semiconductor layers, 648 semiconductor layers, 748 semiconductor layers

549 through holes, 649 through holes, 749 through holes

552 protective layers, 650 etch stop layers, 750 etch stop layers

560 pixel electrodes, 652 protective layers, 752 protective layers

Layer 660 pixel electrode 754 through holes of 562 tool dielectric coefficients

570 common wires, 662 storage capacitors, 760 pixel electrodes

Layer 762 storage capacitors of 572 storage capacitors, 664 tool dielectric coefficients

The layer of 580 black matrix"s, 666 insulating barriers, 764 tool dielectric coefficients

581 resilient coatings, 670 black matrix"s, 770 black matrix"s

582 viewing areas, 671 resilient coatings, 771 resilient coatings

584 color filter layers, 672 viewing areas, 774 color filter layers

586 flatness layers, 674 color filter layers, 776 flatness layers

588 public electrodes, 676 flatness layers, 778 public electrodes

590 second substrates, 678 public electrodes, 780 second substrates

600 dot structures, 680 second substrates, 800 display units

610 first substrates, 700 dot structures, 802 dot structures

612 insulating barriers, 710 first substrates, 810 electrooptical devices

620 gate lines, 720 gate lines, 724 extensions

622 insulating barriers, 722 insulating barriers

Embodiment

See also Fig. 3 A, it is the schematic top plan view of first embodiment of dot structure of the present invention.As shown in the figure, dot structure 300 of the present invention comprises one first substrate 310 (as shown in Figure 4), at least one gate line 320, at least one data wire 330, at least one thin-film transistor 340 and at least one pixel electrode 360, and wherein gate line 320, data wire 330, thin-film transistor 340 are arranged on first substrate 310 with pixel electrode 360.Gate line 320 is interlaced in fact with data wire 330, and the thin-film transistor 340 of this embodiment is positioned on the gate line 320 and relative with gate line 320, and thin-film transistor 340 is coupled to gate line 320, data wire 330 and pixel electrode 360.Wherein, with respect to the part of grid pole line 320 of thin-film transistor 340 with a grid as thin-film transistor 340, and the semi-conductor layer 348 of thin-film transistor 340 is arranged at the grid top, also be that semiconductor layer 348 is positioned at the zone top of gate line 320 with respect to thin-film transistor 340, the one source pole 344 of thin-film transistor 340 and a drain electrode 346 are arranged on the semiconductor layer 348, and all be positioned on the gate line 320, wherein source electrode 344 is coupled to data wire 330.(Through Hole TH) 349 is coupled to drain electrode 346 to pixel electrode 360 via the through hole with respect to gate line 320.

Accept above-mentioned, one common wire 370 more is set on first substrate 310, and common wire 370 is parallel in fact with gate line 320, so common wire 370 is also interlaced in fact with data wire 330, and forms a storage capacitors 372 between common wire 370 and the pixel electrode 360.In the present embodiment, pixel electrode 360 is the electrically conducting transparent material, so the zone of pixel electrode 360 is the transmission region of dot structure 300, but common wire 370 is nontransparent conductive material, so common wire 370 has intercepted dot structure 300 part transmission regions.

In addition, shown in Fig. 3 B, first substrate 310 of dot structure 300 or can around with respect to pixel electrode 360, a black matrix" 380 be set with respect to one second substrate 390 (as shown in Figure 4) of first substrate 310, with this gate line 320 of cover part, this data wire 330 of part, this thin-film transistor 340 and this pixel electrode 360 of part, to prevent the situation of pixel generation light leak.Because the light by pixel electrode 360 can be subjected to covering of black matrix" 380 and be subjected to common wire 370 obstructs, so pixel electrode 360 is not covered and the zone that not intercepted by common wire 370 by black matrix" 380, is viewing area 382.Because thin-film transistor 340 of the present invention is positioned on the gate line 320, therefore also can cover film transistor 340 black matrix" 380 covering gate polar curves 320 time, so relatively can obviously learn by Figure 1B and Fig. 3 B, the aperture opening ratio of the aperture opening ratio of the dot structure 300 of embodiment of the invention dot structure 100 commonly used is big, and it mainly is because the drain electrode 146 and/or the source electrode 144 whole transmission regions that are arranged in pixel electrode 160 places of dot structure 100 commonly used.Moreover drain 146 with the material of source electrode 144 be light tight material, so drain 146 and/or source electrode 144 stopped part light, reduce and make aperture opening ratio increase, the viewing area 382 that is to say dot structure 300 of the present invention is in fact greater than the viewing area 180 of using dot structure 100 always, comparatively speaking, the aperture opening ratio of dot structure 300 of the present invention also improves relatively.

In addition, another embodiment of dot structure 300 of the present invention, can not need on first substrate 310, common wire 370 to be set, and pixel electrode 360 is extended the subregion that covers to next gate line 320, form storage capacitors with subregion at next gate line 320, so viewing area 382 is not influenced by common wire 370 promptly can and reduce, and therefore can increase viewing area 382 areas and the aperture opening ratio of dot structure 300.In addition, in order to detect the defective of dot structure 300, therefore on first substrate 310 at least one dummy pattern (dummy pattern) 312 is set more, with the defective that detects dot structure 300 (as: residue contacts the short circuit that produced etc. with dot structure 300 interior arbitrary layer of conductor layer and/or semiconductor layer), on first substrate 310 a plurality of dummy pattern 312 are set in this embodiment, it is positioned at four corners of dot structure 300, this does not only limit to the set position of dummy pattern 312 for one embodiment of the invention, also optionally be arranged at the arbitrary position in the dot structure 300, for example: around this viewing area, be arranged at easy generation residue part, parallel gate polar curve 320, data wire 330, wherein at least one setting of common wire 370, or other set-up mode.The dummy pattern 312 of the embodiment of the invention is to be example with the through hole that exposes first substrate 310, but is not limited thereto, and also optionally is that groove, slit or above-mentioned mixing are used.Certainly, if dot structure 300 does not need to detect, then dummy pattern 312 can not be provided with yet.Again, dot structure 300 of the present invention preferably, more comprises at least one light shield layer (figure do not show), and it is arranged on this first substrate 310, and parallel with at least one of this data wire 330 and this gate line 320, but is not limited thereto, and also can not comprise light shield layer.

See also Fig. 4, it is the cutaway view of the AA ' direction of Fig. 3 A.As shown in the figure, the gate line 320 and the common wire 370 of dot structure 300 of the present invention are arranged on first substrate 310, the thin-film transistor 340 of this embodiment is positioned on the gate line 320, wherein with respect to the part of grid pole line 320 of thin-film transistor 340 with grid as thin-film transistor 340.One insulating barrier 322 is arranged on first substrate 310, part of grid pole line 320 and the common wire 370.Semiconductor layer 348 is arranged on the insulating barrier 322, and semiconductor layer 348 is positioned at the position of the part of grid pole line 320 of relative thin film transistor 340.Source electrode 344 and drain electrode 346 are arranged at two ends of semiconductor layer 348.Moreover embodiments of the invention preferably, are provided with doping semiconductor layer 332,334 on semiconductor layer 348, and lay respectively at source electrode 344 and drain and 346 contact part, to reduce resistance value.Source electrode 344, drain electrode 346 and on source electrode 344 and the semiconductor layer 348 between 346 of draining a protective layer 352 is set, protective layer 352 also is arranged on the insulating barrier 322 of relative part first substrate 310 and common wire 370.Pixel electrode 360 is arranged on first substrate 310, and is positioned on the protective layer 352, and pixel electrode 360 via through holes 349 couple drain electrode 346, and forms storage capacitors 372 between pixel electrode 360 and the common wire 370.

Accept above-mentionedly, dot structure 300 more includes one second substrate 390, and it is provided with respect to first substrate 310, and second substrate 390 has black matrix" 380, a color filter layer 384 and public electrode 388.Wherein black matrix" 380 is arranged at part second substrate 390, and corresponding to gate line 320, thin-film transistor 340 and data wire (figure does not show), and color filter layer 384 is arranged on second substrate 390 of respective pixel electrode 360.Public electrode 388 is arranged on the color filter layer 384 and couples a common voltage, the data-signal that itself and data wire are sent to pixel electrode 360 produces pressure reduction to be changed, thereby the layer 362 that orders about the tool dielectric coefficient that pixel electrode 360 and public electrode 388 contacted changes the corresponding GTG brightness of demonstration according to voltage difference.Wherein, the layer 362 of tool dielectric coefficient is a liquid crystal layer, a luminescent layer (as: organic material, inorganic material or above-mentioned combination) or above-mentioned combination, to show corresponding GTG brightness.In other words, the layer 362 of tool dielectric coefficient is to be arranged between first substrate 310 and second substrate 390.In addition, for the phenomenon of peeling off that can reduce color filter layer 384 produces, in the present embodiment, preferably, comprising a resilient coating 381 is arranged on the black matrix" 380 and second substrate 390, but be not limited thereto, also can not form resilient coating 381 or be formed under the color filter layer 384 and/or on the part black matrix" 380.Certainly, if solve the drop problem of color filter layer 384, in the present embodiment, preferably, comprise a flatness layer 386 and be arranged on black matrix" 380 and the color filter layer 384, but be not limited thereto, also flatness layer 386 can be set.

See also Fig. 5, it is the cutaway view of another embodiment of Fig. 3 A.Fig. 5 analyses and observe the AA ' direction that direction is all Fig. 3 A.(color filter layer 384 of the dot structure of this kind pattern is positioned at first base stage 310, and is positioned on the thin-film transistor 340 for Color filter On Array, the COA) dot structure of pattern on array applicable to colour filter in the present invention.As shown in the figure, the dot structure 300 of this embodiment has first substrate 310, gate line 320, thin-film transistor 340, pixel electrode 360 and storage capacitors 372 equally, and gate line 320, thin-film transistor 340, pixel electrode 360 and storage capacitors 372 are arranged on first substrate 310.Part of grid pole line 320 corresponding to thin-film transistor 340 as the grid of thin-film transistor 340.Thin-film transistor 340 includes insulating barrier 322 and is arranged on gate line 320, part first substrate 310 and the common wire 370; Semiconductor layer 348 is arranged on the partial insulative layer 322 and corresponding to the grid of thin-film transistor 340; Source electrode 344 and drain electrode 346 are arranged at two ends of semiconductor layer 348 respectively.Moreover embodiments of the invention preferably, are provided with doping semiconductor layer 332,334 on semiconductor layer 348, and respectively with source electrode 344 and drain and 346 contact, to reduce resistance value.Protective layer 352 is arranged on source electrode 344, drain electrode 346 and the part semiconductor layer 348.Pixel electrode 360 is arranged on the partial protection layer 352, and pixel electrode 360 couples drain electrode 346 via through hole 349, and pixel electrode 360 more forms storage capacitors 372 corresponding to common wire 370 in addition.

Accept above-mentioned, dot structure 300 preferably, more comprises another insulating barrier 364, it is arranged on thin-film transistor 340 and the pixel electrode 360, black matrix" 380 is arranged on the insulating barrier 364, because black matrix" 380 is with respect to gate line 320, and thin-film transistor 340 is positioned on the gate line 320, therefore black matrix" 380 is equally with respect to thin-film transistor 340, color filter layer 384 is arranged on the insulating barrier 364, but is not limited thereto, and also another insulating barrier 364 can be set.Color filter layer 384 is provided with flatness layer 386 with the black matrix" 380 of part, but is not limited thereto, and also flatness layer 386 can be set.Just, the color filter layer 384 pre-structure profile of complying with forms and has multistage structure.In addition, for the phenomenon of peeling off that can reduce color filter layer 384 produces, in the present embodiment, preferably, comprising resilient coating 381 is arranged on partial insulative layer 364 and the black matrix" 380, but be not limited thereto, also can not form resilient coating 381 or be formed under the color filter layer 384 and/or on the part black matrix" 380.Moreover second substrate 390 that dot structure 300 is comprised is provided with public electrode 388, the second substrates 390 with respect to first substrate 310.

In addition, also be provided with the layer 362 and between flatness layer 386 and public electrode 388 of tool dielectric coefficient between first substrate 310 and second substrate 390, the layer 362 of tool dielectric coefficient is a liquid crystal layer among this embodiment, but be not limited thereto, also can be a luminescent layer (as: organic material, inorganic material or above-mentioned combination) or above-mentioned combination.Because the present invention can be used in the dot structure of colour filter pattern on array, just the colour filter thin-film transistor 340 that is positioned at the dot structure 300 of pattern on the thin film transistor (TFT) array is positioned at gate line 320, therefore the present invention can allow the dot structure of colour filter pattern on array increase the viewing area, shows usefulness to promote.

See also Fig. 6, it is the cutaway view of another embodiment of Fig. 3 A.Fig. 6 analyses and observe the AA ' direction that direction is all Fig. 3 A.The present invention is applicable to that also (color filter layer 384 of the dot structure of this kind pattern is positioned at first substrate 310 to array, and thin-film transistor 340 is positioned on the color filter layer 384 for Array On Color filter, dot structure AOC) on colour filter.As shown in the figure, the dot structure 300 of this embodiment also has first substrate 310, and first substrate 310 is provided with black matrix" 380, color filter layer 384 and flatness layer 386.Color filter layer 384 is provided with flatness layer 386 with the black matrix" 380 of part, but is not limited thereto, and also flatness layer 386 can be set.In addition, for the phenomenon of peeling off that can reduce color filter layer 384 produces, in the present embodiment, preferably, comprise that resilient coating 381 is arranged on part first substrate 310 and black matrix" 380 on, but be not limited thereto, also can not form resilient coating 381 or be formed under the color filter layer 384 and/or on the part black matrix" 380.Moreover, in order to improve the adsorptivity of gate line 320 and flatness layer 386, preferably, an insulating barrier 314 more is set on flatness layer 386.The gate line 320 of this embodiment, thin-film transistor 340, pixel electrode 360 is arranged on the insulating barrier 314 with storage capacitors 372, and thin-film transistor 340 is electrically connected with storage capacitors 372, but is not limited thereto, and also another insulating barrier 314 can be set.The thin-film transistor 340 of this embodiment is positioned on the gate line 320; corresponding to the part of grid pole line 320 of thin-film transistor 340 grid as thin-film transistor 340, and thin-film transistor 340 comprises insulating barrier 322, semiconductor layer 348, source electrode 344, drain electrode 346 and protective layer 352 equally.Source electrode 344 and drain electrode 346 are arranged at two ends of semiconductor layer 348 respectively.Moreover embodiments of the invention preferably, are provided with doping semiconductor layer 332,334 on semiconductor layer 348, and contact source electrode 344 and drain electrode 346 respectively, to reduce resistance value.Pixel electrode 360 is set on the partial protection layer 352, and pixel electrode 360 couples drain electrode 346 via through hole 349, and corresponding to the common wire 370 that is arranged on insulating barrier 314, to be formed at storage capacitors 372.

In addition, dot structure 300 still comprises second substrate 390, and it is provided with respect to first substrate 310, and is provided with public electrode 388.Be provided with the layer 362 of tool dielectric coefficient between the pixel electrode 360 of the public electrode 388 and first substrate 310, wherein, the layer 362 of tool dielectric coefficient is a liquid crystal layer, a luminescent layer (as: organic material, inorganic material or above-mentioned combination) or above-mentioned combination, to show corresponding GTG brightness.Because the dot structure of array pattern on colour filter can use the present invention, and makes thin-film transistor 340 be positioned at gate line 320, therefore can promote the viewing area of array dot structure of pattern on colour filter, show usefulness to promote.

Fig. 3 A another embodiment of dot structure 300 be the dot structure of organic light emission pattern, its cutaway view as shown in Figure 7, the dot structure of this kind pattern need not be provided with through hole 349 and couple the drain electrode 346 of thin-film transistor 340 with pixel electrode 360.As shown in the figure, the dot structure 300 of this embodiment includes first substrate 310, gate line 320, data wire (figure does not show), thin-film transistor 340 and pixel electrode 360, and the layer 362 of tool dielectric coefficient, and the layer 362 of the tool dielectric coefficient of this embodiment is an organic luminous layer.Gate line 320 is interlaced in fact with data wire; and the thin-film transistor 340 of this embodiment is positioned on the gate line 320; wherein relative with thin-film transistor 340 part of grid pole line is the grid of thin-film transistor 340, and thin-film transistor 340 also comprises insulating barrier 322, semiconductor layer 348, source electrode 344, drain electrode 346 and protective layer 352.Insulating barrier 322 is arranged on part first substrate 310 and the gate line 320, and semiconductor layer 348 is arranged on the partial insulative layer 322, and is positioned at the position of the part of grid pole line 320 of relative thin film transistor 340.Source electrode 344 and drain electrode 346 are arranged at two ends of semiconductor layer 348 respectively.Moreover present embodiment preferably, is provided with doping semiconductor layer 332,334 on the semiconductor layer 348, and it contacts source electrode 344 and drain electrode 346 respectively, to reduce resistance value.Wherein source electrode 344 couples data wire.Pixel electrode 360 is arranged on the partial insulative layer 322, and couples drain electrode 346.In an embodiment of the present invention, be that to present level in fact with the intersection of pixel electrode 360 serve as to implement example to drain 346, but be not limited thereto, also alternative be partial pixel electrode 360 in drain on 346 or under.

Accept above-mentionedly, the layer 362 of tool dielectric coefficient is set on the partial pixel electrode 360, and the layer of tool dielectric coefficient is provided with an electrode 366 on 362.And on source electrode 344, drain electrode 346, part semiconductor layer 348 and the electrode 366 protective layer 352 is set.The present invention allows dot structure 300 increase the area of viewing area, thereby promotes the demonstration usefulness of the dot structure of organic light emission pattern.

See also Fig. 8, it is the schematic top plan view of the dot structure of another embodiment of the present invention.As shown in the figure, dot structure 400 of the present invention comprises first substrate 410 (as shown in Figure 9), gate line 420, data wire 430, thin-film transistor 440, pixel electrode 460 and storage capacitors 472, and gate line 420, data wire 430, thin-film transistor 440, pixel electrode 460 and storage capacitors 472 are arranged on first substrate 410, wherein, gate line 420 is interlaced in fact with data wire 430.The thin-film transistor 440 of this embodiment is positioned on the gate line 420, and thin-film transistor 440 is coupled to gate line 420, data wire 430 and pixel electrode 460, and thin-film transistor 440 is electrically connected with storage capacitors 472.Dot structure 400 more comprises a through hole 454, and it is positioned on the gate line 420, and the position of through hole 454 is corresponding to thin-film transistor 440, and gate line 420 extends an extension 424 to through hole 454, with the grid as thin-film transistor 440.The semiconductor layer 448 of thin-film transistor 440 is with respect to the grid of thin-film transistor 440, and the source electrode 444 of thin-film transistor 440 is positioned on the semiconductor layer 448 with drain electrode 446, and all is positioned on the gate line 420, and wherein source electrode 444 is coupled to data wire 430.Pixel electrode 460 is via being coupled to drain electrode 446 corresponding to drain electrode 446 through hole 449, and partial pixel electrode 460 with respect to the common wire 470 that is arranged on first substrate 410 to form storage capacitors 472.

In addition, another embodiment of dot structure 400 of the present invention need not be provided with common wire 470 on first substrate 410, and extends the subregion of pixel electrode 460 to next stage gate line 420, to form storage capacitors at next stage gate line 420.In addition, in order to detect the defective of dot structure 400, therefore on first substrate 410 at least one dummy pattern 412 is set more, with the defective that detects dot structure 400 (as: residue contacts the short circuit that produced etc. with dot structure 400 interior arbitrary layer of conductor layer and/or semiconductor layer), it is positioned at four corners of dot structure 400, this does not only limit to the set position of dummy pattern 412 for one embodiment of the invention, also optionally be arranged at the arbitrary position in the dot structure 400, for example: around this viewing area, be arranged at easy generation residue part, parallel gate polar curve 420, data wire 430, wherein at least one setting of common wire 470, or other set-up mode.The dummy pattern 412 of the embodiment of the invention is to be example with the through hole that exposes first substrate 410, but is not limited thereto, and also optionally is that groove, slit or above-mentioned mixing are used.Certainly, if dot structure 400 does not need to detect, then dummy pattern 412 can not be provided with yet.Again, dot structure 400 of the present invention more comprises at least one light shield layer (figure do not show), and it is arranged on first substrate 410, and parallel with at least one of data wire 430 and gate line 420, but is not limited thereto, and also can not comprise light shield layer.

See also Fig. 9, it is the cutaway view of the embodiment of Fig. 8.The direction of analysing and observe of Fig. 9 is the BB ' direction of Fig. 8.As shown in the figure, the gate line 420 and the common wire 470 of dot structure 400 of the present invention are arranged on first substrate 410, wherein on the gate line 420 through hole 454 is set, and through hole 454 is corresponding to thin-film transistor 440, can extend to thin-film transistor 440 times and as the grid of thin-film transistor 440 via through hole 454 corresponding to the extension that part of grid pole line 420 extended 424 of thin-film transistor 440.Present embodiment, preferably, the extension 424 of part of grid pole line 420 is to extend from one side of through hole 454 but the gate line 420 that is not attached to the another side of this through hole 454 is an example, that is to say that extension 424 extends in the through hole 454 for part of grid pole line 420 but do not run through through hole 454, but also can be connected to the another side of through hole 454, that is to say that part of grid pole line 420 also may extend in the through hole 454 and runs through through hole 454.Thin-film transistor 440 comprises insulating barrier 422, semiconductor layer 448, source electrode 444, drain electrode 446 and protective layer 452.Insulating barrier 422 is arranged on the gate line 420, on part first substrate 410 and the common wire 470.Semiconductor layer 448 is arranged on the partial insulative layer 422 of corresponding thin-film transistor 440.Source electrode 444 and drain electrode 446 are provided with two ends of semiconductor layer 448 respectively.Moreover embodiments of the invention preferably, are provided with doping semiconductor layer 432,434 on the semiconductor layer 448, and contact source electrode 444 and drain electrode 446 respectively, to reduce resistance value.Source electrode 444 couples data wire 430 (as shown in Figure 8).Protective layer 452 is arranged on source electrode 444, drain electrode 446 and the part semiconductor layer 448, protective layer 452 also be arranged at part first substrate 410 and common wire 470 both on the relative partial insulative layer 422.In addition, pixel electrode 460 is arranged at partial protection layer 452, and via through holes 449 couples drain electrode 446, and partial pixel electrode 460 forms storage capacitors 472 with respect to common wire 470.

In addition, dot structure 400 more comprises second substrate 490, and it is with respect to first substrate 410, and part second substrate 490 is provided with black matrix" 480, color filter layer 484 and public electrode 488.Wherein black matrix" 480 is arranged at part second substrate 490, and corresponding to gate line 420 and thin-film transistor 440, and color filter layer 484 is arranged on second substrate 490 of respective pixel electrode 460.Public electrode 488 is arranged on the color filter layer 484 and couples a common voltage, the data-signal that itself and data wire 430 are sent to pixel electrode 460 produces pressure reduction to be changed, thereby the layer 462 that orders about the tool dielectric coefficient that pixel electrode 460 and public electrode 488 contacted changes the corresponding GTG brightness of demonstration according to voltage difference.Wherein, the layer 462 of tool dielectric coefficient is a liquid crystal layer, a luminescent layer (as: organic material, inorganic material or above-mentioned combination) or above-mentioned combination, to show corresponding GTG brightness.In other words, the layer 462 of tool dielectric coefficient is to be arranged between first substrate 410 and second substrate 490.In addition, for the phenomenon of peeling off that can reduce color filter layer 484 produces, in the present embodiment, preferably, comprising a resilient coating 481 is arranged on the black matrix" 480 and second substrate 490, but be not limited thereto, also can not form resilient coating 481 or be formed under the color filter layer 484 and/or on the part black matrix" 480.Certainly, if solve the drop problem of color filter layer 484, in the present embodiment, preferably, comprise a flatness layer 486 and be arranged on black matrix" 480 and the color filter layer 484, but be not limited thereto, also flatness layer 486 can be set.Again, the through hole 454 of dot structure 400 extends for the extension 424 of gate lines 420 and as the design of the grid of thin-film transistor 440, also can apply to as Fig. 5 and dot structure pattern shown in Figure 6, and be applied to colour filter in the dot structure of pattern on the array or the dot structure of array pattern on colour filter.

See also Figure 10 A, it is the schematic top plan view of the dot structure of another embodiment of the present invention.As shown in the figure, dot structure 500 of the present invention is similar to the dot structure 300 of Fig. 3 A, and the two is and is symmetrical arranged.Dot structure 500 also is to comprise first substrate 510 (as shown in figure 11), gate line 520, data wire 530, thin-film transistor 540 and pixel electrode 560, wherein gate line 520 is arranged on first substrate 510 with data wire 530, and gate line 520 is interlaced in fact with data wire 530.The thin-film transistor 540 of this embodiment is positioned on the gate line 520, wherein thin-film transistor 540 relative gate line 520 in contrast to the thin-film transistor 540 of Fig. 3 A relative gate line 520, that is to say that the set position opposite of the thin-film transistor of this embodiment 540 is in the set position of the thin-film transistor 540 of Fig. 3 A.This embodiment is equally with respect to the part of grid pole line 520 of thin-film transistor 540 grid as thin-film transistor 540, and the semiconductor layer 548 of thin-film transistor 540 is positioned on the gate line 520, and corresponding to the grid of thin-film transistor 540.The source electrode 544 of thin-film transistor 540 is positioned on the semiconductor layer 548 with drain electrode 546, and source electrode 544 also is positioned on the gate line 520 with drain electrode 546, and wherein source electrode 544 is coupled to data wire 530.Pixel electrode 560 is coupled to drain electrode 546 via through hole 549, and wherein pixel electrode 560 couples drain electrode 546 position up and down in contrast to the pixel electrode 560 of Fig. 3 A.

In addition, pixel electrode 560 is also with respect to the common wire 570 that is arranged at first substrate 510, to form storage capacitors 572.In addition, in order to detect the defective of dot structure 500, therefore on first substrate 510 at least one dummy pattern (dummy pattern) 512 is set more, with the defective that detects dot structure 500 (as: residue contacts the short circuit that produced etc. with dot structure 500 interior arbitrary layer of conductor layer and/or semiconductor layer), a plurality of dummy pattern 512 are set on first substrate 510 in this embodiment, it is positioned at four corners of dot structure 500, this does not only limit to the set position of dummy pattern 512 for one embodiment of the invention, also optionally be arranged at the arbitrary position in the dot structure 500, for example: around this viewing area, be arranged at easy generation residue part, parallel gate polar curve 520, data wire 530, wherein at least one setting of common wire 570, or other set-up mode.The dummy pattern 512 of the embodiment of the invention is to be example with the through hole that exposes first substrate 510, but is not limited thereto, and also optionally is that groove, slit or above-mentioned mixing are used.Certainly, if dot structure does not need to detect, then dummy pattern can not be provided with yet.Again, dot structure 500 of the present invention more comprises at least one light shield layer (figure do not show), and it is arranged on first substrate 510, and parallel with at least one of data wire 530 and gate line 520, but is not limited thereto, and also can not comprise light shield layer.In addition, another embodiment of dot structure 500 of the present invention, on first substrate 510 common wire 570 can not need be set, and directly extend pixel electrode 560, to form storage capacitors in the subregion of a last gate line 520 to the subregion that covers a last gate line 520.

In addition, shown in Figure 10 B, the black matrix" 580 of dot structure 500 is with respect to around the pixel electrode 560 and be positioned at first substrate 510 or with respect to second substrate 590 (as shown in figure 11) of first substrate 510, with this gate line 520 of cover part, this data wire 530 of part, this thin-film transistor 540.Pass through because black matrix" 580 can intercept light with common wire 570, the zone of relative pixel electrode 560 is viewing area 582 so not intercepted with common wire 570 by black matrix" 580.

See also Figure 11, it is the cutaway view of the embodiment of Figure 10 A.The direction of analysing and observe of Figure 11 is the CC ' direction of Figure 10 A.As shown in the figure, the gate line 520 and the common wire 570 of dot structure 500 of the present invention are arranged on first substrate 510, and the thin-film transistor 540 of this embodiment is positioned on the gate line 520.Thin-film transistor 540 comprises insulating barrier 522, semiconductor layer 548 and protective layer 552.Corresponding to the part of grid pole line 520 of thin-film transistor 540 with grid as thin-film transistor 540.Insulating barrier 522 is arranged on part first substrate 510, gate line 520 and the common wire 570.On the partial insulative layer 522 corresponding to thin-film transistor 540 semiconductor layer 548 is set.Source electrode 544 and drain electrode 546 are arranged at two ends of semiconductor layer 548.Moreover embodiments of the invention preferably, are provided with doping semiconductor layer 532,534 on semiconductor layer 548, and contact source electrode 544 and drain electrode 546 respectively, to reduce resistance value.Source electrode 544, drain electrode 546 and on source electrode 544 and the semiconductor layer 548 between 546 of draining a protective layer 552 is set, protective layer 552 also is arranged on the insulating barrier 522 of relative part first substrate 510 and common wire 570.

Accept above-mentionedly, pixel electrode 560 is arranged on first substrate 510, and is positioned at partial protection layer 552, and pixel electrode 560 via through holes 549 couple drain electrode 546, and partial pixel electrode 560 corresponding to common wire 570 to form storage capacitors 572.In addition, dot structure 500 more is provided with second substrate 590, and it has black matrix" 580, a color filter layer 584 and public electrode 588 with respect to first substrate, 510, the second substrates 590.Wherein black matrix" 580 is arranged at part second substrate 590, and corresponding to gate line 520 and thin-film transistor 540, and color filter layer 584 is arranged on second substrate 590 of respective pixel electrode 560.Public electrode 588 is arranged on the color filter layer 584 and couples a common voltage, the data-signal that itself and data wire (figure does not show) are sent to pixel electrode 560 produces pressure reduction to be changed, thereby the layer 562 that orders about the tool dielectric coefficient that pixel electrode 560 and public electrode 588 contacted changes the corresponding GTG brightness of demonstration according to voltage difference.Wherein, the layer 562 of tool dielectric coefficient is a liquid crystal layer, a luminescent layer (as: organic material, inorganic material or above-mentioned combination) or above-mentioned combination, to show corresponding GTG brightness.In other words, the layer 562 of tool dielectric coefficient is to be arranged between first substrate 510 and second substrate 590.In addition, for the phenomenon of peeling off that can reduce color filter layer 584 produces, in the present embodiment, preferably, comprise a resilient coating 581 and be arranged on the black matrix" 580 and second substrate 590, but be not limited thereto, also can not form resilient coating 581 or be formed under the color filter layer 584 and/or on the part black matrix" 580.Certainly, if solve the drop problem of color filter layer 584, in the present embodiment, preferably, comprise a flatness layer 586 and be arranged on black matrix" 580 and the color filter layer 584, but be not limited thereto, also flatness layer 586 can be set.In addition, the dot structure 500 of Figure 10 A can be the dot structure of colour filter pattern on colour filter in pattern on the array or array, and it is as Fig. 5 and dot structure pattern shown in Figure 6.

See also Figure 12 A, it is the schematic top plan view of the dot structure of another embodiment of the present invention.As shown in the figure, dot structure 600 of the present invention comprises first substrate 610 (as shown in figure 13), gate line 620, data wire 630, thin-film transistor 640 and pixel electrode 660.Gate line 620 is interlaced in fact with data wire 630, the thin-film transistor 640 of this embodiment is an etch-stop type thin-film transistor, and be positioned on the gate line 620, part of grid pole line 620 corresponding to thin-film transistor 640 as the grid of thin-film transistor 640.The thin-film transistor 640 of etch-stop type has an etch stop layer 650, it is arranged on the semiconductor layer 648 (as shown in figure 13) of thin-film transistor 640, and grid corresponding to thin-film transistor 640, the source electrode 644 of thin-film transistor 640 lays respectively at etch stop layer 650 both sides with drain electrode 646, wherein, source electrode 644 couples data wire 630, and pixel electrode 660 via through holes 649 couple drain electrode 646, and pixel electrode 660 extends to another gate line 620 and forms storage capacitors 662.Therefore, the etch stop layer 650 of present embodiment, it is arranged on the semiconductor layer 648 (as shown in figure 13) of thin-film transistor 640, and etch stop layer 650 2 ends have source electrode 644 respectively and drain 646.Moreover embodiments of the invention preferably, are provided with doping semiconductor layer 632,634 and contact part in source electrode 644, drain electrode 646 with semiconductor layer 648, with the reduction resistance value.

In addition, shown in Figure 12 B, with respect to being provided with black matrix" 670 around the pixel electrode 660, it is positioned at first substrate 610 or with respect to second substrate 680 (as shown in figure 13) of first substrate 610, with this gate line 620 of cover part, this data wire 630 of part, this thin-film transistor 640.Pass through because black matrix" 670 can intercept light, the zone of pixel electrode 660 is not viewing area 672 relatively so intercepted by black matrix" 670.

In addition, another embodiment of dot structure 600 of the present invention, be pixel electrode 660 not to be extended to next gate line 620, and a common wire (figure do not show) more is set on first substrate 610, and partial pixel electrode 660 corresponding common wires, between pixel electrode 660 and common wire, to form storage capacitors.In addition, in order to detect the defective of dot structure 600, therefore on first substrate 610 at least one dummy pattern (dummy pattern can be set more, figure does not show), with the defective that detects dot structure 600 (as: residue contacts the short circuit that produced etc. with dot structure 600 interior arbitrary layer of conductor layer and/or semiconductor layer), an execution mode wherein, dummy pattern can be positioned at four corners of dot structure 600, this does not only limit to the set position of dummy pattern for one embodiment of the invention, also optionally be arranged at the arbitrary position in the dot structure 600, for example: around this viewing area, be arranged at easy generation residue part, parallel gate polar curve 620, wherein at least one setting of data wire 630, or other set-up mode.The present invention can be with the through hole that exposes first substrate 610 being example as dummy pattern, but be not limited thereto, and also optionally is that groove, slit or above-mentioned mixing are used.Certainly, if dot structure 600 does not need to detect, then dummy pattern can not be provided with yet.Again, dot structure 600 of the present invention more comprises at least one light shield layer (figure do not show), and it is arranged on first substrate 610, and parallel with at least one of data wire 630 and gate line 620, but is not limited thereto, and also can not comprise light shield layer.

See also Figure 13, it is the cutaway view of the embodiment of Figure 12 A.The direction of analysing and observe of Figure 13 is the DD ' direction of Figure 12 A.As shown in the figure, the gate line 620 of dot structure 600 of the present invention is arranged on first substrate 610, the thin-film transistor 640 of this embodiment is an etch-stop type thin-film transistor, and be positioned on the gate line 620, wherein be used for grid as thin-film transistor 640 with respect to the part of grid pole line 620 of thin-film transistor 640.Insulating barrier 622 is positioned on part first substrate 610 and the gate line 620, and semiconductor layer 648 is arranged on the partial insulative layer 622 of corresponding thin-film transistor 640.Source electrode 644 and drain electrode 646 are arranged at respectively on etch stop layer 650 and the semiconductor layer 648.Moreover, embodiments of the invention, preferably, semiconductor layer 648 is provided with doping semiconductor layer 632,634, and contacts source electrode 644 and drain electrode 646 respectively, to reduce resistance value.Therefore, etch stop layer 650 is arranged on the semiconductor layer 648, and doping semiconductor layer 632 and 634, source electrode 644 and draining 646 is positioned on two ends of etch stop layer 650.Wherein the source electrode 644 of thin-film transistor 640 couples data wire 630.Protective layer 652 is arranged on partial insulative layer 622, source electrode 644, drain electrode 646 and the etch stop layer 650.Pixel electrode 660 is arranged on the partial protection layer 652, and via through holes 649 couples the drain electrode 646 of thin-film transistor 640, and pixel electrode 660 forms storage capacitors 662 corresponding to next gate line 620.

In addition, dot structure 600 still comprises second substrate 680, and it is relative with first substrate 610.Part second substrate 680 is provided with black matrix" 670, a color filter layer 674 and public electrode 678.Wherein black matrix" 670 is arranged at part second substrate 680, and black matrix" 670 is with respect to part of grid pole line 620, thin-film transistor 640 and/or data wire (figure does not show).Color filter layer 674 is arranged on second substrate 680 of respective pixel electrode 660.Public electrode 678 is arranged on the color filter layer 674 and couples a common voltage, the data-signal that itself and data wire 630 are sent to pixel electrode 660 produces pressure reduction to be changed, thereby the layer 664 that orders about the tool dielectric coefficient that pixel electrode 660 and public electrode 678 contacted changes the corresponding GTG brightness of demonstration according to voltage difference.Wherein, the layer 664 of tool dielectric coefficient is a liquid crystal layer, a luminescent layer (as: organic material, inorganic material or above-mentioned combination) or above-mentioned combination, to show corresponding GTG brightness.In other words, the layer 664 of tool dielectric coefficient is to be arranged between first substrate 610 and second substrate 680.In addition, for the phenomenon of peeling off that can reduce color filter layer 674 produces, in the present embodiment, preferably, comprise a resilient coating 671 and be arranged on the black matrix" 670 and second substrate 680, but be not limited thereto, also can not form resilient coating 671 or be formed under the color filter layer 674 and/or on the part black matrix" 670.Certainly, if solve the drop problem of color filter layer 674, in the present embodiment, preferably, comprise a flatness layer 676 and be arranged on black matrix" 670 and the color filter layer 674, but be not limited thereto, also flatness layer 676 can be set.

See also Figure 14, it is the cutaway view of another embodiment of Figure 12 A.Figure 14 analyses and observe the DD ' direction that direction is all Figure 12 A.As shown in the figure, the present invention is also applicable to colour filter (Color filter On Array, COA) dot structure of pattern on array of tool etch-stop type thin-film transistor.As shown in the figure, the dot structure 600 of this embodiment also comprises first substrate 610, gate line 620, thin-film transistor 640, pixel electrode 660 and storage capacitors 662, and gate line 620, thin-film transistor 640, pixel electrode 660 and storage capacitors 662 are arranged on first substrate 610.Be the grid of thin-film transistor 640 with respect to the part of grid pole line 620 of thin-film transistor 640.The thin-film transistor 640 of this embodiment comprises insulating barrier 622, semiconductor layer 648, etch stop layer 650, source electrode 644, drain electrode 646 and protective layer 652 equally.

Accept above-mentioned, insulating barrier 622 is arranged on gate line 620 and part first substrate 610, semiconductor layer 648 is arranged on the partial insulative layer 622 and corresponding to the gate line 620 of thin-film transistor 640, etch stop layer 650 is arranged on the semiconductor layer 648, and source electrode 644 is arranged at respectively on etch stop layer 650 and the semiconductor layer 648 with drain electrode 646.Moreover embodiments of the invention preferably, are provided with doping semiconductor layer 632,634, to reduce resistance value.So etch stop layer 650 is arranged on the semiconductor layer 648, and on two ends of etch stop layer 650, be provided with doping semiconductor layer 632 and 634, source electrode 644 and drain electrode 646.Protective layer 652 is arranged on source electrode 644, drain electrode 646 and the etch stop layer 650, and protective layer 652 also is arranged on the partial insulative layer 622.Pixel electrode 660 is arranged on the partial protection layer 652, and couples drain electrode 646 via through hole 649, and pixel electrode 660 more forms storage capacitors 662 with respect to the subregion of another gate line 620 in addition.In addition, dot structure 600 more comprises another insulating barrier 666, it is arranged on thin-film transistor 640 and the pixel electrode 660, and black matrix" 670 is arranged on the insulating barrier 666, and wherein the position of black matrix" 670 is with respect to thin-film transistor 640, gate line 620 and/or data wire (not icon).Color filter layer 674 is positioned on the insulating barrier 666 and reaches on the part black matrix" 670, but is not limited thereto, and also another insulating barrier 666 can be set.

In addition, for the peeling phenomenon that can reduce color filter layer 674 produces, in the present embodiment, preferably, comprise a resilient coating 671 and be arranged on the black matrix" 670 and second substrate 680, but be not limited thereto, also can not form resilient coating 671 or be formed under the color filter layer 674 and/or on the part black matrix" 670.Certainly, if solve the drop problem of color filter layer 674, in the present embodiment, preferably, comprise a flatness layer 676 and be arranged on black matrix" 670 and the color filter layer 674, but be not limited thereto, also flatness layer 676 can be set.

In addition, second substrate 680 of dot structure 600 is provided with public electrode 678, second substrate 680 is with respect to a basic Broad-rice-noodles 610, and be provided with the layer 664 of tool dielectric coefficient between the two, wherein, the layer 664 of tool dielectric coefficient is a liquid crystal layer, a luminescent layer (as: organic material, inorganic material or above-mentioned combination) or above-mentioned combination, to show corresponding GTG brightness.Because the present invention can be used in the dot structure of colour filter pattern on array of tool etch-stop type thin-film transistor, just colour filter is positioned on the gate line 620 in the thin-film transistor 640 of the dot structure 600 of pattern on the array, therefore the present invention can increase the viewing area of colour filter dot structure of pattern on array of tool etch-stop type thin-film transistor, shows usefulness to promote.

See also Figure 15, it is the cutaway view of another embodiment of Figure 12 A.Figure 15 analyses and observe the DD ' direction that direction is all Figure 12 A.The present invention also is applicable to array (Array On Color filter, AOC) dot structure of pattern on colour filter of tool etch-stop type thin-film transistor.As shown in the figure, the dot structure 600 of this embodiment also comprises first substrate 610, and black matrix" 670 is arranged on first substrate 610 with color filter layer 674, and color filter layer 674 is provided with flatness layer 676 with black matrix" 670 partly, but be not limited thereto, also flatness layer 676 can be set.In addition, in order to reduce the peeling phenomenon of color filter layer 674, in the present embodiment, preferably, comprise resilient coating 671, its be arranged on part first substrate 610 and black matrix" 670 on, but be not limited thereto, also can not form resilient coating 671 or be formed under the color filter layer 674 and/or on the part black matrix" 670.In order to improve the tack of gate line 620 and flatness layer 676, in the present embodiment, preferably, another insulating barrier 612 is set more on the flatness layer 676.The gate line 620 of this embodiment, thin-film transistor 640, pixel electrode 660 are arranged on the insulating barrier 612 with storage capacitors 662, and thin-film transistor 640 is electrically connected with storage capacitors 662, but are not limited thereto, and also another insulating barrier 612 can be set.The part of grid pole line 620 that wherein corresponds to thin-film transistor 640 is the grid of thin-film transistor 640, and the thin-film transistor 640 of this embodiment comprises insulating barrier 622, semiconductor layer 648, source electrode 644, drain electrode 646, etch stop 650 and protective layer 652 equally.

Accept above-mentioned, insulating barrier 622 is arranged on gate line 620 and part first substrate 610, semiconductor layer 648 is arranged on the partial insulative layer 622, and gate line 620 corresponding to thin-film transistor 640, etch stop layer 650 is arranged on the semiconductor layer 648, and source electrode 644 is arranged at respectively on etch stop layer 650 and the semiconductor layer 648 with drain electrode 646.Moreover embodiments of the invention preferably, are provided with doping semiconductor layer 632,634, to reduce resistance value.So, on the semiconductor layer 648 and two ends of etch stop layer 650, be provided with

doping semiconductor layer

632 and 634, source electrode 644 and drain electrode 646.Protective layer 652 is arranged on source electrode 644, drain electrode 646 and the etch stop layer 650, and protective layer 652 also is arranged on the insulating barrier 622 of part with respect to first substrate 610.Pixel electrode 660 is arranged on the partial protection layer 652, and pixel electrode 660 couples drain electrode 646 via through hole 649, and extends to the subregion of next stage gate line 620, to be formed at storage capacitors 662.

In addition, dot structure 600 still comprises second substrate 680, and it is provided with respect to first substrate 610, and is provided with public electrode 678.Public electrode 678 and the pixel electrode 660 that is positioned at first substrate 610 are provided with the layer 664 of tool dielectric coefficient between the two, wherein, the layer 664 of tool dielectric coefficient is a liquid crystal layer, a luminescent layer (as: organic material, inorganic material or above-mentioned combination) or above-mentioned combination, to show corresponding GTG brightness.

Because the present invention also can be used in the dot structure of array pattern on colour filter of tool etch-stop type thin-film transistor, just array is positioned on the gate line 620 in the thin-film transistor 640 of the dot structure 600 of pattern on the colour filter, therefore the present invention also allows the dot structure of array pattern on colour filter of tool etch-stop type thin-film transistor increase the viewing area, shows usefulness to promote.See also Figure 16, it is the schematic top plan view of the dot structure of another embodiment of the present invention.As shown in the figure, dot structure 700 of the present invention comprises first substrate 710 (as shown in figure 17), gate line 720, data wire 730, thin-film transistor 740, pixel electrode 760 and storage capacitors 762, and gate line 720, data wire 730, thin-film transistor 740, pixel electrode 760 and storage capacitors 762 are arranged on first substrate 710, wherein, gate line 720 is interlaced in fact with data wire 730, and thin-film transistor 740 is electrically connected with storage capacitors 762.The thin-film transistor 740 of this embodiment is positioned on the gate line 720, and dot structure 700 more comprises a through hole 754, it is positioned on the gate line 720 equally, and through hole 754 is with respect to thin-film transistor 740, and the extension 724 of gate line 720 extends to through hole 754, with the grid as thin-film transistor 740.The thin-film transistor 740 of this embodiment is the thin-film transistor of an etch-stop type, the etch stop layer 750 that it comprised is with respect to the grid of thin-film transistor 740, and be positioned on the semiconductor layer (figure does not show) of thin-film transistor, the source electrode 744 of thin-film transistor 740 is positioned on etch stop layer 750 two ends with drain electrode 746, and all be positioned on the gate line 720, wherein source electrode 744 is coupled to data wire 730.Pixel electrode 760 is coupled to drain electrode 746 via through hole 749, and partial pixel electrode 760 extends to the subregion corresponding to next stage gate line 720, to form storage capacitors 762.

In addition, another embodiment of dot structure 700 of the present invention, pixel electrode 760 is not extended to the subregion of next stage gate line 720, and common wire (figure does not show) is set on first substrate 710, between pixel electrode 760 and common wire, to form storage capacitors.In addition, at least one dummy pattern (figure does not show) more can be set on first substrate 710, with the defective that detects dot structure 700 (as: residue contacts the short circuit that produced etc. with dot structure 700 interior arbitrary layer of conductor layer and/or semiconductor layer), an execution mode wherein, dummy pattern can be positioned at four corners of dot structure 700, this does not only limit to the set position of dummy pattern for one embodiment of the invention, also optionally be arranged at the arbitrary position in the dot structure 700, for example: around this viewing area, be arranged at easy generation residue part, parallel gate polar curve 720, wherein at least one setting of data wire 730, or other set-up mode.The present invention can be with the through hole that exposes first substrate 710 being example as dummy pattern, but be not limited thereto, and also optionally is that groove, slit or above-mentioned mixing are used.Certainly, if dot structure 700 does not need to detect, then dummy pattern can not be provided with yet.Again, dot structure 700 of the present invention more comprises at least one light shield layer (figure do not show), and it is arranged on first substrate 710, and parallel with at least one of data wire 730 and gate line 720, but is not limited thereto, and dot structure 700 of the present invention also can not comprise light shield layer.

See also Figure 17, it is the cutaway view of the embodiment of Figure 16.The direction of analysing and observe of Figure 17 is the EE ' direction of Figure 16.As shown in the figure, the gate line 720 of dot structure 700 of the present invention is arranged on first substrate 710, and thin-film transistor 740 is positioned on the gate line 720, wherein on the gate line 720 through hole 754 is set, and through hole 754 is corresponding to thin-film transistor 740, can extension 724 be extended to thin-film transistor 740 times and as the grid of thin-film transistor 740 via through hole 754 corresponding to the part of grid pole line 720 of thin-film transistor 740.Present embodiment, preferably, the extension 724 of part of grid pole line 720 is to extend from one side of through hole 754 but the another side that is not attached to this through hole 754 is an example, that is to say that extension 724 extends in the through hole 754 for part of grid pole line 720 but do not run through through hole 754, but also can be connected to the another side of through hole 754, that is to say that part of grid pole line 720 extends in the through hole 754 and runs through through hole 754.The thin-film transistor 740 of this embodiment comprises insulating barrier 722, semiconductor layer 748, source electrode 744, drain electrode 746, etch stop layer 750 and protective layer 752.

Accept above-mentioned, insulating barrier 722 be arranged on the gate line 720 with part first substrate 710 on.Semiconductor layer 748 is arranged on the partial insulative layer 722 of corresponding thin-film transistor 740.Etch stop layer 750 is arranged on the semiconductor layer 748, and source electrode 744 is arranged at respectively on the semiconductor layer 748 with drain electrode 746 and reaches on etch stop layer 750 two ends.Moreover, embodiments of the invention, preferably, semiconductor layer 748 is provided with doping semiconductor layer 732,734, and contacts source electrode 744 and drain electrode 746 respectively, to reduce resistance value.So etch stop layer 750 is arranged on the semiconductor layer 748, and

doping semiconductor layer

732 and 734, source electrode 744 and drain electrode 746 are arranged at two ends of etch stop layer 750.Protective layer 752 is arranged on source electrode 744, drain electrode 746 and the etch stop layer 750, protective layer 752 also be arranged at part first substrate 710 on the relative partial insulative layer 722.In addition, pixel electrode 760 is arranged on the partial protection layer 752, and via through holes 749 couples drain electrode 746, and pixel electrode 760 extends to next stage gate line 720, to form storage capacitors 762.

In addition, dot structure 700 more comprises second substrate 780, and it is with respect to first substrate 710, and part second substrate 780 is provided with black matrix" 770, color filter layer 774 and public electrode 778.Wherein black matrix" 770 is arranged at part second substrate 780, and corresponding to gate line 720 and thin-film transistor 740 and/or data wire (figure does not show), and color filter layer 774 is arranged on second substrate 780 of respective pixel electrode 760.Public electrode 778 is arranged on the color filter layer 774 and couples a common voltage, the data-signal that itself and data wire are sent to pixel electrode 760 produces pressure reduction to be changed, thereby the layer 764 that orders about the tool dielectric coefficient that pixel electrode 760 and public electrode 778 contacted changes the corresponding GTG brightness of demonstration according to voltage difference.Wherein, the layer 764 of tool dielectric coefficient is a liquid crystal layer, a luminescent layer (as: organic material, inorganic material or above-mentioned combination) or above-mentioned combination, to show corresponding GTG brightness.In other words, the layer 764 of tool dielectric coefficient is to be arranged between first substrate 710 and second substrate 780.

In addition, for the phenomenon of peeling off that can reduce color filter layer 774 produces, in the present embodiment, preferably, comprise a resilient coating 771 and be arranged on the black matrix" 770 and second substrate 780, but be not limited thereto, also can not form resilient coating 771 or be formed under the color filter layer 774 and/or on the part black matrix" 770.Certainly, if solve the drop problem of color filter layer 774, in the present embodiment, preferably, comprise a flatness layer 776 and be arranged on black matrix" 770 and the color filter layer 774, but be not limited thereto, dot structure 700 also can not be provided with flatness layer 776.Again, the extension 724 of gate line 720 extends in the through hole 754 of dot structure 700 and as the grid of thin-film transistor 740, present embodiment also can apply to as Figure 14 and dot structure pattern shown in Figure 15, and is applied to colour filter in the dot structure of pattern on the array or the dot structure of array pattern on colour filter.

Moreover, wherein at least one the material of described first substrate 310,410,510,610 of the various embodiments described above of the present invention and 710 and second substrate 390,490,590,680 and 780 comprises transparent material (as glass, quartz or other material), transparent materials (as pottery, silicon chip or other material) and flexible materials (as Merlon, polyvinyl chloride or other material).Again, in the various embodiments described above, wherein at least one the material of resilient coating, protective layer, insulating barrier and flatness layer comprises inorganic (as: Si oxide, silicon nitride, silicon nitrogen oxide, carborundum, hafnium oxide or other material or above-mentioned combination), organic material (as: photoresist, poly-propionyl ether (polyarylene ether; PAE), polyamides class, polyesters, polyalcohols, polyalkenes, benzocyclobutene (benzocyclclobutene; BCB), HSQ (hydrogen silsesquioxane), MSQ (methyl silesquioxane), silica hydrocarbons (SiOC-H) or other material or above-mentioned combination) or above-mentioned combination.

In the various embodiments described above, be that resilient coating, insulating barrier and the protective layer with the flatness layer of organic material and inorganic serves as to implement example.If the material of resilient coating is an organic material, in order to solve the absorption affinity problem between the original resilient coating and second substrate, preferably, comprise the insulating barrier (not shown) of an inorganic or have an inorganic and the multilayer dielectric layer of an organic material is formed on second substrate, and its material as mentioned above.Again, in the various embodiments described above of the present invention, described pixel electrode serves as to implement example with transparent material (as: indium tin oxide, aluminium zinc oxide, cadmium tin-oxide, indium-zinc oxide, aluminium tin-oxide or other material or above-mentioned combination) all, but being not limited thereto, also optionally is reflection material (as: aluminium (Al), gold (Au), silver (Ag), chromium (Cr), molybdenum (Mo), niobium (Nb), titanium, tantalum, tungsten, neodymium or above-mentioned alloy or other material or above-mentioned combination) or above-mentioned transparent material and the combination of reflecting material.

Again, the various embodiments described above of the present invention are embodiment to have black matrix" all, but are not limited thereto, also black matrix" can be set, wherein at least one is used as black matrix" and uses with data wire, gate line, thin-film transistor, common wire, light shield layer, color filter layer storehouse.And the set black matrix" of the various embodiments described above is embodiment with conductive material (as: aluminium (Al), gold (Au), silver (Ag), chromium (Cr), molybdenum (Mo), niobium (Nb), titanium, tantalum, tungsten, neodymium or above-mentioned alloy or other material or above-mentioned combination) all, but being not limited thereto, also optionally is organic material (as: coloured dye coating, coloured photoresist or at least two coloured photoresist storehouse or other materials) or other material or above-mentioned combination.Again, the arrangement mode of described semiconductor layer of the various embodiments described above of the present invention and doping semiconductor layer is a vertical arrangement, also optionally be horizontally, and its material comprise siliceous amorphous material, siliceous polycrystalline material, siliceous crystallite material, siliceous monocrystalline material or germanic material or other material or above-mentioned combination.In addition, semiconductor layer of the present invention is that the semiconductor layer (as intrinsic semiconductor layer) with non-doping is embodiment, also optionally be doped with the son that mixes, and its concentration is lower than the concentration of doping semiconductor layer.And if only when semiconductor layer is arranged, its also can in presumptive area form non-doped region, first doped region and second doped region wherein at least the two, and its arrangement mode can be vertical arrangement or horizontally.

In addition; interlayer in the storage capacitors of the various embodiments described above of the present invention all with insulating barrier and protective layer wherein at least one is an example, also optionally more the folder establish etch stop layer, semiconductor layer and doping semiconductor layer wherein at least one in its storage capacitors.

As shown in figure 18, a display unit 800 of the present invention comprises a plurality of dot structures 802, wherein these a plurality of dot structures 802 dot structure that is the various embodiments described above wherein one, increase the viewing area of these a plurality of dot structures 802 thus, show usefulness and allow display unit 800 promote.Display unit 800 can apply to an electrooptical device 810, and electrooptical device 810, have more at least one electronic building brick (figure does not show), as: control assembly, operating assembly, processing components, input module, memory element, driven unit or other functional unit or above-mentioned combination.And the type of electrooptical device 810 comprises portable type product (as mobile phone, video camera, camera, mobile computer, game machine, wrist-watch, music player, electronic mail transceiver, digital photo frame, map navigator or similar products like), video and audio product (as audio-visual projector or similar products like), screen, TV, indoor or outdoors billboard etc.Again, thin-film transistor in the dot structure 802 of present embodiment is except can be the bottom gate type among above-described each embodiment, as: outside etch-stop type, the back of the body channel etch type, also can be the thin-film transistor of other type and be positioned at grid online, top gate type for example is in addition with corresponding to the part of grid pole line of the thin-film transistor grid as thin-film transistor.

But the above person, it only is a preferred embodiment of the present invention, be not to be used for limiting scope of the invention process, the equalization done of the described shape of with good grounds claims of the present invention, structure, feature and spirit change and modify, all should be included in the claim scope of the present invention.

Claims

1, a kind of dot structure, it comprises:

One first substrate;

At least one gate line is arranged on this first substrate;

At least one data wire is arranged on this first substrate, and this data wire and this gate line are interlaced;

At least one thin-film transistor is arranged on this first substrate, and is positioned on this gate line, and this thin-film transistor is respectively coupled to this gate line and this data wire; And

At least one pixel electrode is arranged on this first substrate, and couples the drain electrode of this thin-film transistor.

2, dot structure according to claim 1 is characterized in that, the type of this thin-film transistor comprises bottom gate type or top gate type.

3, dot structure according to claim 1 is characterized in that, this pixel electrode couples this drain electrode via a through hole, and this through hole is positioned at this gate line top.

4, dot structure according to claim 1 is characterized in that, in this gate line corresponding to the part of this thin-film transistor a grid as this thin-film transistor.

5, dot structure according to claim 1 is characterized in that, the position corresponding to this thin-film transistor in this gate line has a through hole, and this gate line has an extension and extends in this through hole, with the grid as this thin-film transistor.

6, dot structure according to claim 1 is characterized in that, more comprises:

One second substrate, corresponding to this first substrate setting, this second substrate has a public electrode.

7, dot structure according to claim 6 is characterized in that, more comprises:

One color filter layer is arranged at wherein on of this first substrate and this second substrate.

8, dot structure according to claim 7 is characterized in that, more comprises:

At least one insulating barrier is arranged at least one of this first substrate and this second substrate.

9, dot structure according to claim 7 is characterized in that, more comprises:

One resilient coating is arranged under this color filter layer.

10, dot structure according to claim 7 is characterized in that, more comprises:

One flatness layer, it is arranged on this color filter layer.

11, dot structure according to claim 6 is characterized in that, more comprises:

One black matrix" is arranged at wherein on of this first substrate and this second substrate.

12, dot structure according to claim 11 is characterized in that, this black matrix" correspondence is covered in this pixel electrode of part, this gate line of part and this data wire of part.

13, dot structure according to claim 1 is characterized in that, more comprises:

One common wire is set in parallel on this first substrate with this gate line.

14, according to claim 1,11 or 13 described dot structures, it is characterized in that, more comprise:

At least one light shield layer is set in parallel on this first substrate with at least one of this data wire and this gate line.

15, dot structure according to claim 1 is characterized in that, more comprises:

At least one dummy pattern is arranged on this first substrate.

16, dot structure according to claim 1 is characterized in that, the layer of a tool dielectric coefficient more is set on this pixel electrode.

17, dot structure according to claim 16 is characterized in that, the layer of this tool dielectric coefficient comprises liquid crystal material, luminescent layer or above-mentioned combination.

18, dot structure according to claim 1 is characterized in that, more comprises:

At least one storage capacitors, it is electrically connected at this thin-film transistor.

19, a kind of electrooptical device comprises dot structure as claimed in claim 1.

20, a kind of one pixel structure process method, it comprises:

One first substrate is provided;

Form at least one gate line on this first substrate;

Form at least one data wire on this first substrate, and this data wire and this gate line are interlaced;

Form at least one thin-film transistor on this first substrate, and this thin-film transistor is positioned on this gate line, and is respectively coupled to this gate line and this data wire; And

Form at least one pixel electrode on this first substrate, and this pixel electrode couples this thin-film transistor.

21, method according to claim 20 is characterized in that, more comprises:

One second substrate is provided, and with respect to this first substrate, this second substrate has a public electrode.

22, method according to claim 21 is characterized in that, more comprises:

Form a color filter layer in wherein on of this first substrate and this second substrate.

23, method according to claim 22 is characterized in that, more comprises:

Form at least one insulating barrier at least one of this first substrate and this second substrate.

24, method according to claim 22 is characterized in that, more comprises:

Form a resilient coating under this color filter layer.

25, method according to claim 22 is characterized in that, more comprises:

Form a flatness layer on this color filter layer.

26, method according to claim 21 is characterized in that, more comprises:

Form a black matrix" in wherein on of this first substrate and this second substrate.

27, method according to claim 26 is characterized in that, this black matrix" correspondence is covered in this pixel electrode of part, this gate line of part and this data wire of part.

28, method according to claim 20 is characterized in that, more comprises:

Form a common wire on this first substrate, and be parallel to this gate line.

29, according to claim 20,26 or 28 described methods, it is characterized in that, more comprise:

Form at least one light shield layer on this first substrate, and be parallel to this data wire and this gate line at least one.

30, method according to claim 20 is characterized in that, more comprises:

Form at least one dummy pattern on this first substrate.

31, method according to claim 20 is characterized in that, more comprises:

The layer that forms a tool dielectric coefficient is on this pixel electrode.

32, method according to claim 31 is characterized in that, the layer of this tool dielectric coefficient comprises liquid crystal material, luminescent layer or above-mentioned combination.

33, method according to claim 20 is characterized in that, more comprises:

Form at least one storage capacitors, and be electrically connected with this thin-film transistor.

34, method according to claim 20 is characterized in that, in this gate line corresponding to the part of this thin-film transistor a grid as this thin-film transistor.

35, method according to claim 20 is characterized in that, more comprises:

Form a through hole in this gate line, this through hole is corresponding to this thin-film transistor, and this gate line has an extension and extends in this through hole, with the grid as this thin-film transistor.

36, a kind of manufacture method of electrooptical device comprises manufacture method as claimed in claim 20.