CN100437676C - Differential ab class amplifier circuit and drive circuit using the same - Google Patents
Differential ab class amplifier circuit and drive circuit using the same Download PDFInfo
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- CN100437676C CN100437676C CNB2004100119943A CN200410011994A CN100437676C CN 100437676 C CN100437676 C CN 100437676C CN B2004100119943 A CNB2004100119943 A CN B2004100119943A CN 200410011994 A CN200410011994 A CN 200410011994A CN 100437676 C CN100437676 C CN 100437676C
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/4521—Complementary long tailed pairs having parallel inputs and being supplied in parallel
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
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Abstract
A drive circuit includes a plurality of differential AB class amplifier circuits and a common bias circuit. The plurality of differential AB class amplifier circuits are connected in a voltage follower, input a plurality of analog signals in parallel and drive a plurality of data lines in parallel based on the plurality of analog signals. The common bias circuit generates the first bias signal set and the second bias signal set which is different the first bias signal set. Each of the plurality of differential AB class amplifier circuits includes an N-channel differential amplifier circuit, a P-channel differential amplifier circuit and an output stage circuit. The N-channel differential amplifier circuit is provided between a power supply terminal and a ground terminal, inputs a differential signal and outputs a first output signal onto a first output line based on the first bias signal set. The P-channel differential amplifier circuit is provided between the power supply terminal and the ground terminal in parallel to the N-channel differential amplifier circuit to operate independently from the N-channel differential amplifier circuit, inputs the differential signal and outputs a second output signal onto a second output line based on the first bias signal set. The output stage circuit generates an output signal from the first and second output signals based on the second bias signal set and outputs the output signal onto an output terminal.
Description
Technical field
The present invention relates to driving circuit and treatment circuit, more exactly, relate to the driving circuit of forming by a plurality of differential AB class amplifier circuits, and the treatment circuit that uses this driving circuit.
Background technology
Under the existing situation, such driving circuit or treatment circuit are made up of a plurality of differential AB class amplifier circuits, so that drive the analog data line of a plurality of parallel connections or amplify the simulating signal of a plurality of parallel connections with lower power consumption.
The capacity loads such as data line in parallel that are used for existing driving circuit driven such as the LCD panel of display unit are with the simulating signal of output corresponding to video data.For this purpose, in connecting, used by voltage follower a plurality of difference class ab ammplifiers that on the gamut of the supply voltage between power lead and the ground wire, have the so-called full amplitude of oscillation (Rail-To-Rail) I/O function.
For example, Fig. 1 is a block diagram, shows the circuit structure and the existing driving circuit that is used for display unit of display panel.With reference to figure 1, the existing driving circuit that is used for display unit drives display panel 8, and is made up of control circuit 4, branch level power supply 5, scan line drive circuit 6 and data line drive circuit 7.
Display panel 8 is the active matrix drive-type color liquid crystal panel, uses Thin Film MOS transistor (TFT) as on-off element.Pixel distribution is in going to sweep trace and being listed as on each point of crossing that sweep trace intersects with predetermined space.At each pixel place, the TFT that links to each other with sweep trace as liquid crystal capacitance and its grid of capacity load is series between data line and the common electrode line.
Scanning impulse is produced according to horizontal-drive signal and vertical synchronizing signal by scan line drive circuit 7, and is applied to each horizontal scanning line of display panel 8.Data line drive circuit 7 has generated analog data signal according to digital displaying data for each color, and the common electrode line is being imposed under the state of common potential Vcom, with this signal application to each column data line of display panel 8.Like this, writings and image just is presented on the display panel 8 with full color.
Next tell about data line drive circuit 7.This data line drive circuit 7 is made up of D/A change-over circuit 71 and output circuit 72.D/A change-over circuit 71 is by selecting one in the tapping voltage to come each row video data is carried out the D/A conversion.Output circuit 72 is carried out impedance transformation, drives each column data line and output simulation display data signal.The composition of output circuit 72 comprises a plurality of differential AB class amplifier circuits 1, wherein can carry out full amplitude of oscillation I/O, and it is arranged in the voltage follower connection; And common bias circuit 2, for a plurality of differential AB class amplifier circuits 1 provide shared bias voltage.The output circuit 72 of available data line drive circuit 7 uses power consumption differential AB class amplifier circuits 1 still less, and by they and shared biasing circuit 2 are combined, can circuit scale be increased under the limited situation, a plurality of data lines of driving in parallel.Therefore, reduce circuit area, realized low-power consumption.
Fig. 2 shows the first existing example of disclosed differential AB class amplifier circuits 1 in the unsettled publication application of Japan (JP-A-Showa 61-35004).This differential AB class amplifier circuits 1 is made up of differential amplifier 17 and AB class output circuit 18.Used the general differential amplifier 17 that wherein can use full amplitude of oscillation I/O to be used as the driver of AB class output circuit.Differential amplifier 17 is made up of N raceway groove differential amplifier mirror image output 171 and P raceway groove differential amplifier part 172.
Differential amplifier mirror image output 171 by a pair of N raceway groove difference MOS transistor 112 and 113, a pair of P raceway groove load mos transistor 114 and 115, a pair of P raceway groove mirror image output mos transistor 117 and 118 and constant current source 116 form.N raceway groove difference MOS transistor 112 links to each other with reversed input pin Vin (-) with noninverting input pin Vin (+) with 113 grid.P raceway groove load mos transistor 114 and 115 is connected, as the load of N raceway groove difference MOS transistor 112 and 113.P raceway groove mirror image output mos transistor 117 and 118 is with the image current I4 of the difference current of P raceway groove load mos transistor 114 and 115 and the N raceway groove load mos transistor 124 and 125 that I5 outputs to differential amplifier part 172.Constant current source 116 offers continuous current I1 the source electrode of N raceway groove difference MOS transistor 112 and 113.
In addition, differential amplifier part 172 by a pair of P raceway groove difference MOS transistor 122 and 123, a pair of N raceway groove load mos transistor 124 and 125 and constant current source 126 form.P raceway groove difference MOS transistor 122 links to each other with noninverting input pin Vin (+) with reversed input pin Vin (-) with 123 grid.N raceway groove load mos transistor 124 and 125 is connected, as the current mirror type load of P raceway groove difference MOS transistor 122 and 123.Constant current source 126 offers continuous current I2 the source electrode of P raceway groove difference MOS transistor 122 and 123.Signal outputs to the grid of the N raceway groove output stage MOS transistor 132 of AB class output circuit 18 from the drain electrode of P raceway groove difference MOS transistor 123.
AB class output circuit 18 by a pair of N raceway groove and P raceway groove output stage MOS transistor 131 and 132, a pair of constant current source 137 and 138, a pair of N raceway groove and P raceway groove displacement MOS transistor 135 and 136 and a pair of constant pressure source 139 and 140 form.P raceway groove and N raceway groove output stage MOS transistor 131 and 132 are connected between output pin and the power pins and between output pin and grounding pin.Constant current source 137 and 138 is connected between the grid of P raceway groove output stage MOS transistor 131 and the power pins and between the grid and grounding pin of N raceway groove output stage MOS transistor 132.P raceway groove and N raceway groove displacement MOS transistor 135 and 136 play the effect of level regulator, and are connected in parallel between constant current source 137 and 138.Constant pressure source 139 is connected P raceway groove and transistorized two threshold voltages of N-channel MOS with 140 by the diode that couples together with the series connection form, and the voltage that is lower than power pins and grounding pin is provided.
When it is pointed out that the biasing partial common when a plurality of differential AB class amplifier circuits 1 that make this existing example, the constant current source 116,126,137 of differential AB class amplifier circuits and 138 is formed the current mirror circuit structures.The continuous current MOS transistor and the mirror image input mos transistor that are used for mirror image output separate.Common bias circuit 2 is made up of mirror image input mos transistor and constant pressure source 139 and 140.The mirror image input mos transistor provides bias voltage for the grid of the continuous current MOS transistor of differential AB class amplifier circuits 1.
In this existing differential AB class amplifier circuits, two constant current sources 116 of differential amplifier 17 and 126 generally are made up of the current mirror circuit of N raceway groove and P channel MOS transistor respectively.The P channel MOS transistor of constant current source 126 can operate as normal input voltage range be equal to or greater than VSS, and be equal to or less than VDD-[Vgs+Vds (sat)].In input voltage range greater than VDD-[Vgs+Vds (sat)] time, the transistorized current mirror circuit of the N-channel MOS of constant current source 116 is working properly.By the P channel MOS transistor 114 and 117 of current mirror circuit, and 115 and 118 these two groups, superimposed and be provided for N raceway groove load mos transistor 124 and 125 based on the image current I4 of the difference current of bias current I1 and I5.Therefore, differential amplifier partly works in the input voltage range from the grounding pin to the power pins, and can carry out full amplitude of oscillation input.Therefore, realized the full amplitude of oscillation I/O function of differential AB class amplifier circuits.
Fig. 3 is a circuit diagram, shows the second existing example of disclosed above-mentioned differential AB class amplifier circuits in the unsettled publication application of Japan (JP-P2001-177352A).Should existing differential AB class amplifier circuits 1 form, and realized full amplitude of oscillation I/O function by N raceway groove differential amplifier 11, P raceway groove differential amplifier 12 and AB class output circuit 13.
AB class output circuit 13 by a pair of P raceway groove and N raceway groove output stage MOS transistor 131 and 132, a pair of P raceway groove and N raceway groove continuous current MOS transistor 133 and 134 and a pair of P raceway groove and N raceway groove displacement MOS transistor 135 and 136 form.P raceway groove and N raceway groove output stage MOS transistor 131 and 132 are connected between output pin and the power pins, and between output pin and the grounding pin.MOS transistor 131 and 132 grid link to each other with 12 output line with differential amplifier 11 respectively.P raceway groove and N raceway groove continuous current MOS transistor 133 and 134 are connected between the output line and power pins of differential amplifier 11, and between the output line and grounding pin of differential amplifier 12.MOS transistor 133 links to each other with BN with N raceway groove continuous current bias voltage BP with the P raceway groove with 134 grid.P raceway groove and N raceway groove displacement MOS transistor 135 and 136 are connected in parallel between the output line of differential amplifier 11 and 12, to play the effect of level regulator.In addition, AB class output circuit 13 by a pair of P raceway groove and N raceway groove mirror image output mos transistor 141 and 142 and a pair of P raceway groove and N raceway groove mirror image output mos transistor 143 and 144 form.P raceway groove and N raceway groove mirror image output mos transistor 141 and 142 are connected between the grid and power pins of N raceway groove displacement MOS transistor 136, and between the grid and grounding pin of P raceway groove displacement MOS transistor 135.MOS transistor 141 links to each other with BN with bias voltage BP respectively with 142 grid.P raceway groove and N raceway groove mirror image output mos transistor 143 and 144 are connected between P raceway groove displacement MOS transistor 135 and the power pins, and between the grid and grounding pin of N raceway groove displacement MOS transistor 136.P raceway groove and N raceway groove mirror image output mos transistor 143 and 144 are delivered to output stage MOS transistor 131 and 132 with P raceway groove and N raceway groove image current I7 and I6.And in the AB of this existing example class output circuit, a pair of mirror capacity 145 and 146 that is used for phase compensation is connected between each grid and output pin Vout of P raceway groove and N raceway groove output stage MOS transistor 131 and 132.Differential AB class amplifier circuits has frequency response preferably.It is pointed out that common bias circuit 2 is made up of P raceway groove in the current mirror circuit and N raceway groove mirror image input mos transistor, bias voltage BP and BN are offered a plurality of differential AB class amplifier circuits of this existing example.
In this existing differential AB class amplifier circuits 1, bias voltage BN and BP are applied to the grid of N raceway groove and P raceway groove mirror image output mos transistor 142 and 141, are used for current mirror control.In addition, P raceway groove and N raceway groove mirror image output mos transistor 143 and 144 are used as current mirror and are controlled, and are similar to P raceway groove and N raceway groove output stage MOS transistor 131 and 132.Node between MOS transistor 143 and 142 and 141 and 144 and P raceway groove and N raceway groove displacement MOS transistor 135 link to each other with 136 grid.Therefore, the grid voltage of P raceway groove and N raceway groove displacement MOS transistor 135 and 136 is not constant, and these are different with the first existing example.Its grid voltage dynamically changes along with the output state of differential AB class amplifier circuits 1, to be set to the current mirror duty with one in P raceway groove and N raceway groove output stage MOS transistor 131 and 132.Therefore, idle current is restricted to very little value, thereby has reduced cross distortion.
In addition, in a plurality of differential AB class amplifier circuits and common bias circuit as shown in Figures 2 and 3, although the MOS transistor of constant current source or continuous current MOS transistor and the controlled disconnection in test pattern of displacement MOS transistor are not shown.Also have, P raceway groove and N raceway groove test MOS transistor are connected between the P raceway groove output stage MOS transistor of power pins and AB class output circuit 13, and between grounding pin and the N raceway groove output stage MOS transistor, so that they are switched in test pattern.In test pattern, P raceway groove and N raceway groove output stage MOS transistor are to being disconnected, idle current is made as zero.Like this, in test pattern, all circuital current paths are disconnected, so that chip leakage current that can the measurement data line drive circuit.
But, in the differential AB class amplifier circuits of existing driving circuit, there are some problems.
In the differential AB class amplifier circuits of as shown in Figure 2 the first existing example, although can carry out full amplitude of oscillation I/O, be necessary according to input voltage range VDD-[Vgs+Vds (sat)] in bias current I1 come the image current I4 and the I5 of superimposed difference current.Just because of this, the component number that is used for superimposed mirror image circuit has increased, and has been increased by image current I4 and I5 institute consumed current.This is unfavorable for highly integrated and realizes low-power consumption.
In the differential AB class amplifier circuits of as shown in Figure 3 the second existing example, when using a plurality of differential AB class amplifier circuits as the output circuit of data line drive circuit, the grid voltage of P raceway groove and N raceway groove displacement MOS transistor 135 and 136 changes along with the output state of differential AB class amplifier circuits 1.Therefore, can't carry out shared the connection with 136 grid to the P raceway groove of a plurality of differential AB class amplifier circuits 1 and N-channel MOS transistor 135.Just because of this for each differential AB class amplifier circuits, needs four mirror image output mos transistors 141 to 144.This is unfavorable for highly integrated.
In addition, the idle current of the output stage MOS transistor of differential AB class amplifier circuits is subjected to the control of current mirror.Therefore, current mirror electric current I 6 and the I7 institute consumed current by as shown in Figure 3 four mirror image output mos transistors 141 to 144 increased.
In addition, when using these differential AB class amplifier circuits 1 as the output circuit 72 of data line drive circuit 7, in order to break all circuital current paths at test pattern, between the grid and power pins of P raceway groove output stage MOS transistor, and between the grid and grounding pin of P raceway groove output stage MOS transistor, P raceway groove and N raceway groove test MOS transistor have been added.In addition, the grid voltage of P raceway groove and N raceway groove output stage MOS transistor is fixed to bias voltage.In the driving circuit of display unit, used 300 to 500 differential AB class amplifier circuits 1 on each chip, therefore need 600 to 1000 P raceway grooves or N raceway groove test MOS transistor.This is unfavorable for highly integrated.
In conjunction with above tell about, a kind of MOSFET power amplifier is disclosed in the Japanese unsettled publication application (JP-A-Heisei 7-142940).In this existing example, the power output stage of push-pull type MOSFET power amplifier has the CMOS structure.Front at power output stage provides compensated stage, and provides amplifier stage with amplification input signal in the front of compensated stage.The gate bias voltage of the MOSFET of power output stage is set by compensated stage.
In addition, in the Japanese unsettled publication application (JP-A-Heisei 9-232883) a kind of operational amplification circuit is disclosed.In this existing example, the operational amplification circuit that proposes has first and second differential amplifier circuits, first and second output circuits that it has first input pin and second input pin, first and second level adjustment circuits, first and second current sources, be made up of transistor etc. a whole set of.First input pin of first differential amplifier circuit links to each other with first input pin of second differential amplifier circuit, and second input pin of first differential amplifier circuit links to each other with second input pin of second differential amplifier circuit.The output of first differential amplifier circuit links to each other with the input of described first level adjustment circuit.The output of described first level adjustment circuit links to each other with the grid of the first transistor of first current source and output circuit.The output of second differential amplifier circuit links to each other with the input of second level adjustment circuit, and the output of second level adjustment circuit links to each other with the grid of current source with the transistor seconds of second output circuit.
Summary of the invention
Therefore, target of the present invention is to realize highly integrated and low-power consumption in the treatment circuit of driving circuit that includes a plurality of differential AB class amplifier circuits and use driving circuit.
According to an aspect of the present invention, driving circuit comprises a plurality of differential AB class amplifier circuits and common bias circuit.In voltage follower, be connected with a plurality of differential AB class amplifier circuits, a plurality of simulating signals of they inputs in parallel, and according to a plurality of data lines of a plurality of simulating signals driving in parallel.Common bias circuit generates first bias signal set and is different from second bias signal set of first bias signal set.Each of a plurality of differential AB class amplifier circuits comprises N raceway groove differential amplifier circuit, P raceway groove differential amplifier circuit and output-stage circuit.N raceway groove differential amplifier circuit between power pins and grounding pin, its input differential signal and first output signal is outputed on first output line according to first bias signal set.P raceway groove differential amplifier circuit is between power pins and grounding pin, be in parallel with N raceway groove differential amplifier circuit, with the separate work of N raceway groove differential amplifier circuit, input differential signal and second output signal is outputed on second output line according to first bias signal set.Output-stage circuit comes to generate output signal from first and second output signals according to second bias signal set, and output signal is outputed to output pin.
Here, N raceway groove differential amplifier circuit can comprise the N channel current source MOS transistor of controlling according to first offset signal of first bias signal set, and P raceway groove differential amplifier circuit can comprise the P channel current source MOS transistor of controlling according to second offset signal of first bias signal set.In this case, common bias circuit in test pattern respectively first and second offset signals be set to ground voltage level and mains voltage level.
In addition, output-stage circuit can comprise a pair of P raceway groove and N raceway groove output stage MOS transistor, a pair of P raceway groove and N raceway groove continuous current MOS transistor and P raceway groove and N raceway groove displacement MOS transistor.P raceway groove output stage MOS transistor is connected between power pins and the output pin, and for its grid provides first output signal, and N raceway groove output stage MOS transistor is connected between grounding pin and the output pin, and provides second output signal for its grid.P raceway groove continuous current MOS transistor is connected between the power pins and first output line, and provide the 3rd offset signal of second bias signal set for its grid, and, N raceway groove continuous current MOS transistor is connected between the grounding pin and second output line, and provides as the 4th offset signal one of in the offset signal of second bias signal set for its grid.P raceway groove and N raceway groove displacement MOS transistor are connected in parallel between first and second output lines, play the effect of level regulator.For the grid of P raceway groove displacement MOS transistor provides the 5th offset signal of second bias signal set, and provide the 6th offset signal of second bias signal set for the grid of N raceway groove displacement MOS transistor.In this case, common bias circuit can be set to ground voltage level, mains voltage level, mains voltage level and ground voltage level respectively with the 3rd to the 6th offset signal in test pattern.
In addition, common bias circuit can comprise constant current source, a pair of P raceway groove and N channel current mirror image circuit, a pair of P raceway groove and N-channel MOS transistor.Constant current source is between power pins and grounding pin.Each exports a plurality of image current signals according to the circuital current of constant current source from a plurality of current mirror output pins to P raceway groove and N channel current mirror image circuit.First pair P channel MOS transistor is connected between one of a plurality of current mirror output pins of N channel current mirror image circuit and the power pins, and its grid and drain electrode are coupled together by shared, and, first pair N-channel MOS transistor is connected between one of a plurality of current mirror output pins of P channel current mirror image circuit and the grounding pin, and its grid is coupled together by shared with drain electrode.First and second offset signals of first bias signal set can be respectively exported out from P raceway groove and the transistorized grid of N-channel MOS as the first couples of first and second nodes.
As an alternative, common bias circuit can comprise constant current source and a pair of P raceway groove and N channel current mirror image circuit.Constant current source is between power pins and grounding pin.Each exports a plurality of image current signals according to the circuital current of constant current source from a plurality of current mirror output pins to P raceway groove and N channel current mirror image circuit.First and second offset signals of first bias signal set can be respectively from exporting out at first node between constant current source and the P channel current mirror image circuit and the Section Point between P raceway groove and N channel current mirror image circuit.
In this case, common bias circuit may further include series circuit and two transistorized series circuits of N-channel MOS of second pair of P raceway groove and N-channel MOS transistor, two P channel MOS transistors.The series circuit of two P channel MOS transistors is connected in series between one of a plurality of current mirror output pins of N channel current mirror image circuit and the power pins.The grid of each of two P channel MOS transistors and shared the coupling together of drain electrode.Two transistorized series circuits of N-channel MOS are connected in series between one of a plurality of current mirror output pins of P channel current mirror image circuit and the grounding pin.Transistorized each grid and shared the coupling together of drain electrode of two N-channel MOSs.Second pair P channel MOS transistor is connected between one of a plurality of current mirror output pins of N channel current mirror image circuit and the power pins, and its grid and shared the coupling together of drain electrode.Second pair N-channel MOS transistor is connected between one of a plurality of current mirror output pins of P channel current mirror image circuit and the grounding pin, and its grid and shared the coupling together of drain electrode.Third and fourth offset signal of second bias signal set is respectively from exporting out as second pair P raceway groove and third and fourth node of N-channel MOS transistor gate.The 5th offset signal is exported out from the 5th node as the grid of one of two P channel MOS transistors of the series circuit that is positioned at N channel current mirror image circuit one side, and the 6th offset signal is exported out from the 6th node as the grid of one of two N-channel MOS transistors of the series circuit that is positioned at P channel current mirror image circuit one side.
In addition, common bias circuit may further include first switch, is connected in series with constant current source; Second switch, and the P channel current mirror image circuit between power pins and constant current source is connected in parallel; The 3rd switch, and the N channel current mirror image circuit between the node between grounding pin and P raceway groove and the N channel current mirror image circuit is connected in parallel; The 4th switch is connected between this grid and power pins to the P channel MOS transistor; And the 5th switch, be connected in this between transistorized grid of N-channel MOS and the grounding pin.In this case, first switch is opened in test pattern, and second to the 5th switch is closed in test pattern.
In addition, common bias circuit may further include first switch, is connected in series with constant current source; Second switch, and the P channel current mirror image circuit between power pins and constant current source is connected in parallel; And the 3rd switch, and the N channel current mirror image circuit between the node between grounding pin and P raceway groove and the N channel current mirror image circuit is connected in parallel.In this case, first switch is opened in test pattern, and the second and the 3rd switch is closed in test pattern.
In addition, common bias circuit may further include the 6th switch, is connected between the grid of the 3rd node and second pair of P channel MOS transistor; Minion is closed, and is connected between the 4th node and the second pair of transistorized grid of N-channel MOS; Octavo is closed, and is connected between the 3rd node and the grounding pin; The 9th switch is connected between the 4th node and the power pins; The tenth switch is connected between the 5th node and the power pins; And the 11 switch, be connected between the 6th node and the grounding pin.In this case, the 6th and minion close and in test pattern, to be opened, and the 8th to the 11 switch is closed in test pattern.
Description of drawings
Fig. 1 is a block diagram, shows the display unit and the display panel that use existing driving circuit;
Fig. 2 is a circuit diagram, shows the first existing example of differential AB class amplifier circuits;
Fig. 3 is a circuit diagram, shows the second existing example of differential AB class amplifier circuits;
Fig. 4 is a circuit diagram, shows the circuit structure according to the differential AB class amplifier circuits of the driving circuit of first embodiment of the invention;
Fig. 5 is a circuit diagram, shows the circuit structure according to the common bias circuit of the driving circuit of first embodiment of the invention;
Fig. 6 shows the mode of operation of the differential AB class amplifier circuits as shown in Fig. 5 and Fig. 6;
Fig. 7 shows the switch control of the common bias circuit as shown in Fig. 5 and Fig. 6;
Fig. 8 is a circuit diagram, shows the correction form of common bias circuit as shown in Figure 6; And
Fig. 9 is a block diagram, shows driving circuit of the present invention.
Embodiment
Come to tell about in detail the treatment circuit of driving circuit of the present invention and this driving circuit of use below with reference to the accompanying drawings.With reference to figure 9, driving circuit of the present invention is by differential amplifier 11, differential amplifier 12, and AB class output circuit 13 and common bias circuit 2 are formed.Differential amplifier 11 and differential amplifier 12 are separate.Common bias circuit 2 provides various biasing voltage signals to differential amplifier 11, differential amplifier 12 and AB class output circuit 13.In driving circuit of the present invention, circuit area and power consumption obtain reducing, and do not damage the full amplitude of oscillation I/O characteristic of differential AB class amplifier circuits.Will tell about display unit driving circuit below it is pointed out that as driving circuit and treatment circuit representative instance.
Driving circuit of the present invention is made up of a plurality of differential AB class amplifier circuits 1 and common bias circuit 2, the output circuit 72 in the data line drive circuit 7 of the existing display unit driving circuit shown in similar Fig. 1.Differential AB class amplifier circuits 1 can realize full amplitude of oscillation I/O, and the circuit structure of differential AB class amplifier circuits 1 and common bias circuit 2 is different with those circuit structures in the existing driving circuit.In the following embodiments, the structure and the work of differential AB class amplifier circuits 1 and common bias circuit 2 will be told about with reference to the accompanying drawings.
Fig. 4 is a circuit diagram, shows according to the differential AB class amplifier circuits 1 of the driving circuit of first embodiment of the invention and the circuit structure of common bias circuit 2.Fig. 4 shows differential AB class amplifier circuits 1, and Fig. 5 shows common bias circuit 2.
With reference to figure 4, the differential AB class amplifier circuits 1 of driving circuit in the present embodiment is made up of differential amplifier 11, differential amplifier 12 and AB class output circuit 13.
AB class output circuit 13 by a pair of P raceway groove and N raceway groove output stage MOS transistor 131 and 132, a pair of P raceway groove and N raceway groove continuous current MOS transistor 133 and 134 and a pair of P raceway groove and N raceway groove displacement MOS transistor 135 and 136 form.P raceway groove and N raceway groove output stage MOS transistor 131 and 132 are connected between output pin and the power pins and between output pin and the grounding pin.P raceway groove and N raceway groove output stage MOS transistor 131 and 132 grid and P raceway groove and N raceway groove differential amplifier 11 link to each other with 12 output line.P raceway groove and N raceway groove constant current source mos transistor 133 and 134 are connected between the output line of differential amplifier 11 and the power pins and between the output line and grounding pin of differential amplifier 12. MOS transistor 133 and 134 grid are provided to a pair of P raceway groove and N raceway groove continuous current bias voltage BP2 and BN2 respectively.P raceway groove and N raceway groove displacement MOS transistor 135 and 136 is connected between the grid of the output line of differential amplifier 11 and 12 and MOS transistor 135 and 136, and accept a pair of P raceway groove and N raceway groove continuous current bias voltage BP3 and BN3, to play the effect of level regulator.
In the AB of this embodiment class output circuit 13, similar with existing example, the a pair of mirror capacity 145 and 146 that is used for phase compensation is connected between the grid and output pin Vout of P raceway groove and N raceway groove output stage MOS transistor 131 and 132, so that differential AB class amplifier circuits 1 has frequency response preferably.
Next, with reference to figure 5, the common bias circuit 2 of driving circuit of the present invention by constant current source 21, switch 22, a pair of P raceway groove and N channel current mirror image circuit 23 and 24 and pair of switches 25 and 26 form.Switch 22 breaks at test pattern.For each raceway groove, P raceway groove and N channel current mirror image circuit 23 and 24 are exported a plurality of image currents according to the circuital current of the series circuit of constant current source 21 and 22 from a plurality of output pins.For each raceway groove, switch 25 and 26 is connected between the input pin of P channel current mirror image circuit 23 and the power pins and between the input pin and grounding pin of N channel current mirror image circuit 24. Switch 25 and 26 is connected in test pattern.
In addition, common bias circuit 2 further by a pair of P raceway groove and N- channel MOS transistor 31 and 32, pair of switches 33 and 34 and pair of switches 35 and 36 form.For each raceway groove, P raceway groove and N- channel MOS transistor 31 and 32 are connected between the output pin and power pins of N channel current mirror image circuit 24, and between the output pin and grounding pin of P channel current mirror image circuit 23.The drain and gate of P channel MOS transistor 31 is by shared connection, and the drain and gate of N-channel MOS transistor 32 is by shared connection.Switch 33 links to each other with 32 grid with MOS transistor 31 respectively with 34, and breaks at test pattern.Switch 35 is connected between switch 33 and the grounding pin, and switch 36 is connected between switch 34 and the power pins.Play the effect of the output node of P raceway groove and N raceway groove continuous current bias voltage BP2 and BN2 at the node between switch 33 and 35 and the node between switch 34 and 36. Switch 35 and 36 breaks at test pattern.In test pattern, the P raceway groove of earth level and power level and N raceway groove continuous current bias voltage BP2 and BN2 are output.
In addition, common bias circuit 2 further is made up of by two P channel MOS transistors 37 and 38 series circuits of forming with by two N- channel MOS transistors 39 and 40 series circuits of forming and pair of switches 41 and 42 a pair of.In by two P channel MOS transistors 37 and 38 series circuits of forming, grid in each MOS transistor and drain electrode are coupled together by shared.In by two N- channel MOS transistors 39 and 40 series circuits of forming, grid in each MOS transistor and drain electrode are coupled together by shared.For each raceway groove, two P channel MOS transistors 37 and 38 series circuits of forming are connected between the output pin and power pins of N channel current mirror image circuit 24, and for each raceway groove, two N- channel MOS transistors 40 and 39 series circuits of forming are connected between the output pin and power pins of P channel current mirror image circuit 23. Switch 41 and 42 is in parallel with these series circuits respectively.The grid of the grid of MOS transistor 38 and transistor 40 plays the effect of the output node of P raceway groove and N raceway groove displacement bias voltage BP3 and BN3.Switch 41 and 42 breaks at test pattern.In test pattern, the P raceway groove of power level and earth level and N raceway groove displacement bias voltage BP3 and BN3 are output.It is pointed out that each switch in common bias circuit 2 is made up of P raceway groove and N-channel MOS transistor.
Next tell about the work of the differential AB class amplifier circuits 1 of driving circuit in this embodiment.The work of driving circuit switch as shown in Figure 7.In the differential amplifier circuit 11 of differential AB class amplifier circuits 1 in this embodiment, the constant current source of differential levels is made up of N raceway groove continuous current MOS transistor 111.Therefore, the input signal in the voltage range from power pins VDD to [Vgs1+Vds1 (sat)] is exaggerated and is transferred to AB class output circuit 13.In this case, Vds1 (sat) be N raceway groove continuous current MOS transistor 111 in saturation operation region source electrode and the drain electrode between voltage, and Vgs1 is for when flowing through N raceway groove difference MOS transistor 112 and 113 as bias current I1, N raceway groove difference MOS transistor 112 and 113 source electrode and the voltage between the grid.
In addition, in differential amplifier 12, the constant current source of differential levels is made up of P raceway groove continuous current MOS transistor 121.Therefore, in voltage range from VDD-[Vgs2+Vds2 (sat)] input signal to ground potential VSS is exaggerated and transfers to AB class output circuit 13.In this case, between the source electrode of the P raceway groove continuous current MOS transistor 121 of voltage Vds2 (sat) in the saturation region and the drain electrode, and when bias current I2 flowed through P raceway groove difference MOS transistor 122 or 123, voltage Vgs2 was between the former utmost point and grid of P raceway groove difference MOS transistor 122 or 123.
Fig. 6 shows the mode of operation of the differential AB class amplifier circuits 1 of this embodiment.And the input signal Vin (+) of differential AB class amplifier circuits 1 and the input voltage range of Vin (-) are shown in vertical direction among the figure.
According to the input voltage range of input signal Vin (+) and Vin (-), the differential AB class amplifier circuits 1 of this embodiment has the three kinds of mode of operations in (1)～(3).
Mode of operation (1) is corresponding to the input voltage range of input signal Vin (+) and Vin (-), and it is higher than VDD-[Vgs2+Vds2 (sat)], and be lower than VDD.In this input voltage range, can't carry out the operate as normal of the P raceway groove continuous current MOS transistor 121 of differential amplifier 12, because this voltage range is allowing outside the input voltage range.But this moment, allow within the input voltage range, so signal is delivered to AB class output circuit 13 from differential amplifier 11, and plays the normal effect of differential AB class amplifier circuits because the N raceway groove continuous current transistor 111 of differential amplifier 11 works in.
Mode of operation (2) is corresponding to the input voltage range of input signal Vin (+) and Vin (-), and it is higher than [Vgs1+Vds1 (sat)], and is lower than VDD-[Vgs2+Vds2 (sat)].In this input voltage range, differential amplifier 11 and 12 and P raceway groove and N raceway groove continuous current MOS transistor 111 and 121 be positioned at and allow input voltage range.Therefore, differential amplifier 11 and 12 can both operate as normal.Signal is delivered to AB class output circuit 13 from differential amplifier 11 and 12, and this circuit just can normally play the effect of differential AB class amplifier circuits like this.
Mode of operation (3) is corresponding to the input voltage range of input signal Vin (+) and Vin (-), and it is equal to or higher than ground voltage VSS, and is equal to or less than [Vgs1+Vds1 (sat)].In this input voltage range, the N raceway groove continuous current MOS transistor 111 of differential amplifier 11 is allowing outside the input voltage range, and it can't carry out operate as normal like this.But this moment, the P raceway groove continuous current MOS transistor 121 of differential amplifier 12 is in allowing input voltage range.Therefore, input signal is delivered to AB class output circuit 13 by differential amplifier 12, and this circuit just can normally play the effect of differential AB class amplifier circuits like this.
Like this, in the differential AB class amplifier circuits of this embodiment, even this input signal is allowing outside the input voltage range, so that one of differential amplifier 11 and 12 cisco unity malfunction, but other differential amplifiers are working properly.Therefore, any voltage range,, signal can be passed to AB class output circuit 13 as existing embodiment from power pins VDD to grounding pin VSS.That is to say, can carry out full amplitude of oscillation input.
In addition, in the first existing embodiment as shown in Figure 2, in the difference amplifier section of differential AB class amplifier circuits, generally need superimposed mirror image circuit.In the second existing example as shown in Figure 3, need four mirror image output mos transistors and control a pair of P raceway groove of AB class output circuit of differential AB class amplifier circuits and the grid voltage of N raceway groove displacement MOS transistor.But, do not need these circuit among the present invention.As a result, reduce the element number in the differential AB class amplifier circuits, and do not used the current path of the electric current I 4 to I7 as shown in Fig. 2 and 3.Therefore, reduce circuit area, and can realize the integrated and low-power consumption of height of driving circuit.Particularly, the circuit area and the low-power consumption of the driving circuit of display unit reduce greatly, because in the data line drive circuit of display unit driving circuit, each chip has used 300 to 500 differential AB class amplifier circuits.
Next, tell about the work of the common bias circuit 2 of driving circuit among this embodiment.The common bias circuit 2 of driving circuit is carried out switch control among this embodiment, and wherein P raceway groove and N raceway groove differential bias voltage, P raceway groove and N raceway groove continuous current bias voltage and P raceway groove and N raceway groove displacement bias voltage is set to power level or earth level in test pattern.
Fig. 3 shows the switch control that the common bias circuit 2 of driving circuit among this embodiment is carried out, and the ON/OFF state of switch has been shown in test pattern and normal mode of operation.The ON/OFF state that it is pointed out that each switch in the common bias circuit 2 as shown in Figure 5 shows the ON/OFF state in the normal mode of operation.
In common bias circuit 2 as shown in Figure 5, three switches 22,33 and 34 are switched on.Other switches are closed.P raceway groove and N channel current mirror image circuit 23 and 24 are exported a plurality of image currents from a plurality of output pins, corresponding to continuous current 21.P raceway groove and N-channel MOS transistor 27 and 28 P raceway groove and N raceway groove continuous current MOS transistor 121 and 111 with differential amplifier 12 and 11 are formed mirror image circuit, are used for each raceway groove.P raceway groove and N- channel MOS transistor 27 and 28 generate P raceway groove and N raceway groove differential bias voltage BP1 and BN1 as threshold voltage, are used for the level that diode connects MOS transistor, and output to P raceway groove and N raceway groove continuous current MOS transistor 121 and 111.P raceway groove and N raceway groove continuous current MOS transistor 121 and 111 flow through bias current I2 and I1.
P raceway groove and N-channel MOS transistor 31 and 32 P raceway groove and N raceway groove continuous current MOS transistor 133 and 134 with AB class output circuit 13 are formed current mirror circuit, are used for each raceway groove.P raceway groove and N- channel MOS transistor 31 and 32 generate P raceway groove and N raceway groove continuous current bias voltage BP2 and BN2 as threshold voltage, are used for the level that diode connects MOS transistor, and output to P raceway groove and N raceway groove continuous current MOS transistor 133 and 134.P raceway groove and N raceway groove continuous current the MOS transistor 133 and 134 bias current I3 that flows through.
Two P channel MOS transistors 37 and 38 and two N- channel MOS transistors 39 and 40 generate P raceway grooves and N raceway groove displacement bias voltage BP3 and BN3 as threshold voltage, be used for the two-stage that diode connects MOS transistor, and output to the P raceway groove and the N raceway groove displacement MOS transistor 135 and 136 of AB class output circuit 13.These P raceway grooves and N raceway groove displacement MOS transistor 135 and 136 play the effect of level regulator.
In addition, in common bias circuit 2 as shown in Figure 5, in test pattern, three switches 22,33 and 34 disconnect, and other switch connections.Like this, all the circuital current paths in the common bias circuit 2 get clogged.And N raceway groove and P raceway groove differential bias voltage BN1 and BP1 get to earth level and power level by switch respectively, and P raceway groove and N raceway groove continuous current bias voltage BP2 and BN2 are got to earth level and power level by switch respectively.In addition, P raceway groove and N raceway groove displacement bias voltage BP3 and BN3 are got to power level and earth level by switch respectively.Therefore, in differential AB class amplifier circuits 1, P raceway groove and N raceway groove continuous current MOS transistor 12 and 11 are disconnected.In addition, the P raceway groove of AB class output circuit 13 and N raceway groove continuous current MOS transistor 133 and 134 are switched on.The P raceway groove of AB class output circuit 13 and N raceway groove displacement MOS transistor 135 and 136 are disconnected.The grid of P raceway groove and N raceway groove output stage MOS transistor 131 and 132 is fixed on power level and earth level, disconnects P raceway groove and N raceway groove output stage MOS transistor 131 and 132 fully, and all circuital current paths of differential AB class amplifier circuits 1 are disconnected like this.Like this, in test pattern, the circuital current of driving circuit becomes 0, so that can carry out the leakage current measurement of driving circuit.
Under the existing situation, when using differential AB class amplifier circuits as the output circuit of data line drive circuit, in order to break all circuital current paths at test pattern, P raceway groove and N raceway groove test MOS transistor be between the grid of P raceway groove output stage MOS transistor 131 and the power pins and between the grid and grounding pin of N raceway groove output stage MOS transistor 132, with the gate voltage fixed of P raceway groove and N raceway groove output stage MOS transistor 131 and 132 on power level and earth level.But, in differential AB class amplifier circuits of the present invention, P raceway groove and N raceway groove displacement MOS transistor 135 and 136 disconnect, and P raceway groove and N raceway groove continuous current MOS transistor 133 and 134 connections.As a result, the grid voltage of P raceway groove and N raceway groove output stage MOS transistor 131 and 132 is fixed on power level and the earth level.Different with existing example, do not need P raceway groove and N raceway groove test MOS transistor are added.In addition, for two elements in the differential AB class amplifier circuits, circuit area has reduced.Particularly, the circuit area of the driving circuit of display unit reduces greatly, because in the driving circuit of display unit, each chip has used 300 to 500 differential AB class amplifier circuits, and the driving circuit of display unit can be by highly integrated.
The common bias circuit that it is pointed out that this embodiment as shown in Figure 5 is a control circuit, wherein uses many switches, and can carry out various corrections to it.
For example, Fig. 8 is a circuit diagram, shows the correction form of the common bias circuit 2 in the driving circuit of the present invention.In the common bias circuit 2 of this correction, P raceway groove and N- channel MOS transistor 27 and 28, switch 29 and 30 and two mirror image output mos transistors of P raceway groove and N channel current mirror image circuit have been removed.Compare with the common bias circuit shown in Fig. 5, the input pin of P raceway groove and N channel current mirror image circuit plays the effect of the output node of P raceway groove and N raceway groove differential bias voltage BP1 and BN1.In the common bias circuit 2 of this correction, P raceway groove and N raceway groove differential bias voltage BP1 and BN1, P raceway groove and N raceway groove continuous current bias voltage BP2 and BN2 and P raceway groove and N raceway groove displacement bias voltage BP3 and BN3 must design in regular turn.But, compare with common bias circuit shown in Figure 5, circuit area further reduces.
In addition, also told about driving circuit at the foregoing description or in revising with a plurality of differential AB class amplifier circuits and common bias circuit.But, the present invention is not subjected to the restriction of these embodiment.A plurality of differential AB class amplifier circuits are used for amplifying simultaneously a plurality of simulating signals and common bias circuit is used for bias voltage is offered the shared treatment circuit of a plurality of differential AB class amplifier circuits including, and can obtain the same effect that driving circuit can be obtained.This point is appreciated that.
In addition, in the above-described embodiments, told about the driving circuit that includes a plurality of differential AB class amplifier circuits.But, the present invention is not subjected to the restriction of these embodiment.Differential AB class amplifier circuits is accepted to control in the various circuit according to P raceway groove and N raceway groove bias voltage therein, can obtain the same effect that driving circuit can be obtained.This point is appreciated that.
In driving circuit of the present invention and treatment circuit, in the differential AB class amplifier circuits that has full amplitude of oscillation I/O, the number of element and current path has reduced.Circuit area and power consumption obtain reducing, and can realize that the height of driving circuit and treatment circuit is integrated.That is to say, in the differential AB class amplifier circuits in driving circuit of the present invention, do not need superimposed mirror image circuit, although it needs in the difference amplifier section of the differential AB class amplifier circuits in the first existing example shown in Figure 2.In addition, in the AB class output circuit of the differential AB class amplifier circuits of the shown in Figure 3 second existing example,, just do not needed in the present invention in order to four required mirror image output mos transistors of grid voltage of control P raceway groove and N raceway groove displacement MOS transistor.Therefore, the element number in the differential AB class amplifier circuits reduces.In addition, the current path that does not have electric current I 4～I7 as shown in Figures 2 and 3.Therefore, circuit area and power consumption obtain reducing, and can realize that the height of driving circuit is integrated.
In addition, under the existing situation, when using differential AB class amplifier circuits as the output circuit of data line drive circuit, in order to break all circuital current paths at test pattern, make an addition to P raceway groove and N raceway groove test MOS transistor between the grid of P raceway groove output stage MOS transistor and the power pins and between the grid and grounding pin of N raceway groove output stage MOS transistor, and with the gate voltage fixed of P raceway groove and N raceway groove output stage MOS transistor on power level and earth level.But, do not need P raceway groove and N raceway groove test MOS transistor are added in differential AB class amplifier circuits of the present invention, and the element number of differential AB class amplifier circuits also reduced two, circuit area has just reduced like this.Particularly, be used for the driving circuit of display unit, wherein each chip has used 300 to 500 differential AB class amplifier circuits, and the circuit area and the power consumption of driving circuit have significantly reduced.
Claims (11)
1. driving circuit comprises:
A plurality of differential AB class amplifier circuits are connected in the voltage follower, a plurality of simulating signals of they inputs in parallel, and according to a plurality of data lines of described a plurality of simulating signals driving in parallel; And
Common bias circuit, it generates first bias signal set and is different from second bias signal set of described first bias signal set,
Each of wherein said a plurality of differential AB class amplifier circuits comprises:
N raceway groove differential amplifier circuit, between power pins and grounding pin, its input differential signal and first output signal is outputed on first output line according to described first bias signal set, it comprises the N channel current source MOS transistor of controlling according to first offset signal of described first bias signal set;
P raceway groove differential amplifier circuit, between described power pins and described grounding pin, be in parallel with described N raceway groove differential amplifier circuit, with the separate work of described N raceway groove differential amplifier circuit, import described differential signal and according to described first bias signal set second output signal is outputed on second output line, it comprises the P channel current source MOS transistor of controlling according to second offset signal of described first bias signal set; And
Output-stage circuit comes to generate output signal from described first and second output signals according to described second bias signal set, and described output signal is outputed to output pin,
Wherein, described common bias circuit described respectively first and second offset signals in test pattern are set to ground voltage level and mains voltage level.
2. driving circuit as claimed in claim 1, wherein said common bias circuit comprises:
Constant current source is between described power pins and described grounding pin;
A pair of P raceway groove and N channel current mirror image circuit, each exports a plurality of image current signals according to the circuital current of described constant current source from a plurality of current mirror output pins to P raceway groove and N channel current mirror image circuit; And
A pair of P raceway groove and N-channel MOS transistor; Wherein the described P channel MOS transistor in the first pair of P raceway groove and the N-channel MOS transistor is connected between one of the described a plurality of current mirror output pins and described power pins of described N channel current mirror image circuit; And its grid and drain electrode are shared to be coupled together; And the described N-channel MOS transistor in the first pair of P raceway groove and the N-channel MOS transistor is connected between one of described a plurality of current mirror output pins of described P channel current mirror image circuit and the described grounding pin; And its grid and drain electrode are shared to be coupled together
Described first and second offset signals of wherein said first bias signal set are exported out from described first pair described P raceway groove and the transistorized described grid of N-channel MOS as first and second nodes respectively.
3. driving circuit as claimed in claim 2, wherein said common bias circuit further comprises:
First switch is connected in series with described constant current source;
Second switch, and the described P channel current mirror image circuit between described power pins and described constant current source is connected in parallel;
The 3rd switch, and the described N channel current mirror image circuit between the node between described grounding pin and described P raceway groove and the N channel current mirror image circuit is connected in parallel;
The 4th switch is connected between the described grid and described power pins of the described P channel MOS transistor in described this first pair of P raceway groove and the N-channel MOS transistor; And
The 5th switch is connected between the transistorized described grid of described N-channel MOS and described grounding pin in described this first pair of P raceway groove and the N-channel MOS transistor.
4. driving circuit as claimed in claim 3, wherein said first switch is opened in test pattern, and described second to the 5th switch is closed in described test pattern.
5. driving circuit as claimed in claim 1, wherein said common bias circuit comprises:
Constant current source is between described power pins and described grounding pin; And
A pair of P raceway groove and N channel current mirror image circuit, each exports a plurality of image current signals according to the circuital current of described constant current source from a plurality of current mirror output pins to P raceway groove and N channel current mirror image circuit,
Described first and second offset signals of wherein said first bias signal set are exported out from first node between described constant current source and described P channel current mirror image circuit and the Section Point between described P raceway groove and N channel current mirror image circuit respectively.
6. driving circuit as claimed in claim 5, wherein said common bias circuit further comprises:
First switch is connected in series with described constant current source;
Second switch, and the described P channel current mirror image circuit between described power pins and described constant current source is connected in parallel; And
The 3rd switch, and the described N channel current mirror image circuit between the node between described grounding pin and described P raceway groove and the N channel current mirror image circuit is connected in parallel.
7. driving circuit as claimed in claim 6, wherein said first switch is opened in test pattern, and the described second and the 3rd switch is closed in described test pattern.
8. driving circuit comprises:
A plurality of differential AB class amplifier circuits are connected in the voltage follower, a plurality of simulating signals of they inputs in parallel, and according to a plurality of data lines of described a plurality of simulating signals driving in parallel; And
Common bias circuit, it generates first bias signal set and is different from second bias signal set of described first bias signal set,
Each of wherein said a plurality of differential AB class amplifier circuits comprises:
N raceway groove differential amplifier circuit, between power pins and grounding pin, its input differential signal and first output signal is outputed on first output line according to described first bias signal set;
P raceway groove differential amplifier circuit, between described power pins and described grounding pin, be in parallel with described N raceway groove differential amplifier circuit, with the separate work of described N raceway groove differential amplifier circuit, import described differential signal and second output signal is outputed on second output line according to described first bias signal set; And
Output-stage circuit comes to generate output signal from described first and second output signals according to described second bias signal set, and described output signal is outputed to output pin;
Wherein, described output-stage circuit comprises:
A pair of P raceway groove and N raceway groove output stage MOS transistor, wherein said P raceway groove output stage MOS transistor is connected between described power pins and the described output pin, and for its grid provides described first output signal, and described N raceway groove output stage MOS transistor is connected between described grounding pin and the described output pin, and provides described second output signal for its grid;
A pair of P raceway groove and N raceway groove continuous current MOS transistor, wherein said P raceway groove continuous current MOS transistor is connected between described power pins and described first output line, and provide the 3rd offset signal of described second bias signal set for its grid, and described N raceway groove continuous current MOS transistor is connected between described grounding pin and described second output line, and provides as the 4th offset signal one of in the offset signal of described second bias signal set for its grid; And
P raceway groove and N raceway groove displacement MOS transistor, be connected in parallel between described first and second output lines, play the effect of level regulator, the 5th offset signal of described second bias signal set wherein is provided for the grid of described P raceway groove displacement MOS transistor, and provide the 6th offset signal of described second bias signal set for the grid of described N raceway groove displacement MOS transistor
Wherein, in common bias circuit described in the test pattern described the 3rd to the 6th offset signal is set to ground voltage level, mains voltage level, described mains voltage level and described ground voltage level respectively.
9. driving circuit as claimed in claim 8, wherein said common bias circuit further comprises:
The second pair of P raceway groove and N-channel MOS transistor;
The series circuit of two P channel MOS transistors is connected in series between one of the described a plurality of current mirror output pins and described power pins of described N channel current mirror image circuit, and grid of each and shared the coupling together of drain electrode; And
Two transistorized series circuits of N-channel MOS are connected in series between one of the described a plurality of current mirror output pins and described grounding pin of described P channel current mirror image circuit, and grid of each and shared the coupling together of drain electrode,
Described P channel MOS transistor in wherein said second pair of P raceway groove and the N-channel MOS transistor is connected between one of described a plurality of current mirror output pins of described N channel current mirror image circuit and the described power pins, and its grid and shared the coupling together of drain electrode
Described N-channel MOS transistor in wherein said second pair of P raceway groove and the N-channel MOS transistor is connected between one of described a plurality of current mirror output pins of described P channel current mirror image circuit and the described grounding pin, and its grid and shared the coupling together of drain electrode
Wherein as described third and fourth offset signal of the part of described second bias signal set respectively from exporting out as described second pair described P raceway groove and third and fourth node of the transistorized described grid of N-channel MOS, and
Export out from the 5th node as described the 5th offset signal of the part of described second bias signal set, and export out from the 6th node as the described grid of one of described two N-channel MOS transistors of the described series circuit that is positioned at described P channel current mirror image circuit one side as described the 6th offset signal of the part of described second bias signal set as the described grid of one of described two P channel MOS transistors of the described series circuit that is positioned at described N channel current mirror image circuit one side.
10. driving circuit as claimed in claim 9, wherein said common bias circuit further comprises:
The 6th switch is connected between the described grid of the described P channel MOS transistor in described the 3rd node and described second pair of P raceway groove and the N-channel MOS transistor;
Minion is closed, and is connected between the transistorized described grid of described N-channel MOS in described the 4th node and described second pair of P raceway groove and the N-channel MOS transistor;
Octavo is closed, and is connected between described the 3rd node and the described grounding pin;
The 9th switch is connected between described the 4th node and the described power pins;
The tenth switch is connected between described the 5th node and the described power pins; And
The 11 switch is connected between described the 6th node and the described grounding pin.
11. driving circuit as claimed in claim 10, the wherein said the 6th and minion close and in test pattern, to be opened, and described the 8th to the 11 switch is closed in described test pattern.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003335559 | 2003-09-26 | ||
| JP335559/2003 | 2003-09-26 |
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| CN100437676C true CN100437676C (en) | 2008-11-26 |
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| CNB2004100119943A Expired - Fee Related CN100437676C (en) | 2003-09-26 | 2004-09-27 | Differential ab class amplifier circuit and drive circuit using the same |
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| Country | Link |
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| US (1) | US7170351B2 (en) |
| KR (1) | KR100620662B1 (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| US20050068105A1 (en) | 2005-03-31 |
| US7170351B2 (en) | 2007-01-30 |
| CN1607564A (en) | 2005-04-20 |
| KR20050030570A (en) | 2005-03-30 |
| KR100620662B1 (en) | 2006-09-19 |
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