TW201115908A

TW201115908A - Driving amplifier circuit

Info

Publication number: TW201115908A
Application number: TW99107669A
Authority: TW
Inventors: Uday Dasgupta
Original assignee: Mediatek Singapore Pte Ltd
Priority date: 2009-10-27
Filing date: 2010-03-16
Publication date: 2011-05-01
Also published as: CN102055417A; CN102055417B

Abstract

A driving amplifier circuit includes: a first driver for sourcing a load current to a load; a second driver for sinking the load current from the load; a first operational amplifier (op-amp) for driving the first driver; a second operational amplifier for driving the second driver; a first bias circuit for biasing the first driver; a second bias circuit for biasing the second driver; an enabling circuit for enabling either the first bias circuit or the second bias circuit according to a control signal; a digital control circuit for monitoring currents of the first driver and the second driver to generate the control signal; and an offset equalization circuit, coupled between an internal node of the first operational amplifier and an internal node of the second operational amplifier, for adjusting DC offset of at least one of the first operational amplifier and the second operational amplifier.

Description

201115908 六、發明說明：【發明所屬之技術領域】本發明有關於驅動放大器咏^㈣师口丨出的’更具體地’有關種驅動放大器電路 • 【先前技術】在放大器設計中，總需要在效率(efficiency)以及交越失真 (crossoverdistortion)之間達到均衡。傳統的AB電流驅動放大器包含耦接到一推挽級(push-pull stage)的運算放大器，用以輸出電流至負載(負載作為接收端)或者自負載接收電流(負載作爲源端）。當 AB電流驅動放大器向該負載流出電流(s〇urcing⑶汀加)時可以使 # 用PMOS驅動器，當自該負載汲取電流(sinking currennt)a夺，可以使用NMOS驅動器。傳統的服級放大器利用很小的偏移電流 (biasing current)以保證更爲平滑的交越。如果偏移電流太小，那麼放大器就會承又些父越失真。進一步說，如果兩個驅動器都承載大電流，那麼就會自電源電壓產生擊穿(shoot-thrcmgh)電流。因此，偏移電流的精確控制就是非常必要的。出版於正EE固態電路期刊，199〇年2月，第25卷，第工期 201115908 (IEEE journal of solid-state circuits，Vol. 25, No. 1，February 1990)的 A CMOS Large-Swing Low-Distortion Three-Stage Class AB Power dwp/诉er」中揭露了一種具有三級的Ag類放大器，用於解決上述問題’在此僅為參考。此電路較其它先前技術有所改進，但是此電路仍然具有複雜的電路架構。因此，迫切需要提供一種新的運算放大器，能夠簡化上述三級放大器之電路，而同時減少由驅動器所承載的電流量。【發明内容】有鑑於此，本發明目的之一在於提供一種驅動放大器電路。本發明提供—種鶴放大器電路，包含：—第—轉器，用於机出-負載電流至-負載；—第二驅動器，用於自該負载沒取該負載電m算放大器’祕到—差動輸人訊號，該第一運算放大H用於驅動該第—,轉器；—第二運算放大器，輕接到該差動輸入訊號，該第二運算放大器用於驅動該第二驅動器；一第-偏移電路，用於偏移該第—驅動器；—第二偏移電路，用於偏移該第二驅動器；一賦能電路，祕到該第—偏移電路以及该第二偏移電路，用於根據—控制訊號賦能該第—偏移電路或者該第二偏移電路；-數健制電路，雛_賦能電路，用於龄視該第-驅之電流以及該第二驅動器之電流，以產生該控制 201115908 訊號；以及一偏置等化電路，耦接在該第一運算放大器之一内部節點以及該第二運算放大器的一内部節點之間，用於調整該第— 運算放大器以及該第二運算放大器之至少一者的直流偏置，以使該第一運算放大器以及該第二運算放大器具有相同的直流偏置。本發明再提供一種驅動放大器電路，包含：一第一驅動器，用於輸出一負載電流至一負載，一第二驅動器，用於自該負載接 • 收該負載電流；一第一運算放大器，耦接到一差動輸入訊號，該第一運算放大器用於驅動該第一驅動器；一第二運算放大器，耦接到該差動輸入訊號，該第二運算放大器用於驅動該第二驅動器；一第一偏移電路，用於偏移該第一驅動器；一第二偏移電路，用於偏移該第二驅動器；一賦能電路，耦接到該第一偏移電路以及該第二偏移電路，用於根據一控制訊號賦能該第一偏移電路或者該第二偏移電路；一數位控制電路，耦接到該賦能電路，用於鲁監視該第一驅動器之電流以及該第二驅動器之電流，以產生該控制訊號；以及一外部電路，耦接到該第一運算放大器以及該第二運算放大器的該反相輸入端之間，用於調整該第一運算放大器以及該第二運算放大器的至少-者的直流電壓，以使該第一運算放大器以及該第二運算放大器具有相同直流偏置，該外部電路包含：至少一抽頭可變電阻，耦接到一參考電器，其中，當該抽頭可變電阻選擇性抽頭在不同位置時，該第_運算放大器的一直流電壓與5亥第一運鼻放大器的直流電壓不同。 201115908 本心月hi、的驅動放大器電路較先前技術電路架構更爲簡單，也能夠避免擊穿電流的問題。【實施方式】在說明書及後續的中請專利翻當巾朗了某些詞彙來指稱特定元件。所屬領財具有通常知識者應可理解，製造商可能會用不同的名詞來稱呼同—個元件。本說明書及後續的巾請專利範圍並不以名稱的差絲料區分元件的方式，献以元件在功能上的差異來作為區分的糊。在韻說明書及後續的請求項當中所提及的「包括」和「包含」係為_開放式的用語，故應解釋成包含但不限定於」。α外，「搞接」—詞在此係&含任何直接及間接的電氣連接手段。間接的電氣連接手段包括通過其他裝置進行連接。睛參閱第1圖’第1圖為根據本發明一個實施例的驅動放大器電路100的示意圖。驅動放大器電路1〇〇包含一個ρ運算放大器110以及一個Ν運算放大器12〇，其中，上述兩個運算放大器耦接一差動負載電流’並且可以將ρ運算放大器u〇以及Ν運算放大器120分別稱之爲第—運算放大器以及第二運算放大器。ρ 運算放大器110以及Ν運算放大器12〇分別耦接到PMOS驅動器 201115908201115908 VI. Description of the Invention: [Technical Field] The present invention relates to a 'more specifically' related drive amplifier circuit for a driver amplifier •^(4). [Prior Art] In amplifier design, it is always necessary to Equilibrium is achieved between efficiency and crossover distortion. A conventional AB current drive amplifier includes an operational amplifier coupled to a push-pull stage for outputting current to the load (load as the receiving end) or receiving current from the load (load as the source). When the AB current drive amplifier flows current to the load (s〇urcing(3)Tinga), the PMOS driver can be used. When the current is drawn from the load, the NMOS driver can be used. Conventional service amplifiers use a small biasing current to ensure a smoother crossover. If the offset current is too small, then the amplifier will be more distorted. Further, if both drivers are carrying a large current, a shoot-thrcmgh current is generated from the supply voltage. Therefore, precise control of the offset current is necessary. A CMOS Large-Swing Low-Distortion, published in the Journal of Solid State Electrical Circuits, February 1989, Vol. 25, No. 1, 2011, 908 (IEEE journal of solid-state circuits, Vol. 25, No. 1, February 1990) A three-stage Ag-type amplifier is disclosed in the Three-Stage Class AB Power dwp/suit er" to solve the above problem 'for reference only. This circuit is an improvement over other prior art, but this circuit still has a complex circuit architecture. Therefore, there is an urgent need to provide a new operational amplifier that simplifies the circuit of the above three-stage amplifier while reducing the amount of current carried by the driver. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a driver amplifier circuit. The invention provides a crane amplifier circuit, comprising: a first-rotator for the machine-load current to the load; and a second driver for taking the load power from the load. a differential input signal, the first operational amplification H is used to drive the first, the converter; the second operational amplifier is lightly connected to the differential input signal, and the second operational amplifier is used to drive the second driver; a first-offset circuit for shifting the first driver; a second offset circuit for offsetting the second driver; an enabling circuit, the first offset circuit and the second bias a shifting circuit for energizing the first offset circuit or the second offset circuit according to the control signal; the digital health circuit, the younger_enable circuit, for ageing the current of the first drive and the first a current of the second driver to generate the control 201115908 signal; and a bias equalization circuit coupled between the internal node of the first operational amplifier and an internal node of the second operational amplifier for adjusting the – operational amplifier and the second operation A DC bias of at least one of the amplifiers such that the first operational amplifier and the second operational amplifier have the same DC offset. The invention further provides a driving amplifier circuit comprising: a first driver for outputting a load current to a load, and a second driver for receiving the load current from the load; a first operational amplifier coupled Receiving a differential input signal, the first operational amplifier is used to drive the first driver; a second operational amplifier is coupled to the differential input signal, and the second operational amplifier is used to drive the second driver; a first offset circuit for shifting the first driver; a second offset circuit for offsetting the second driver; an enabling circuit coupled to the first offset circuit and the second bias a shifting circuit for enabling the first offset circuit or the second offset circuit according to a control signal; a digital control circuit coupled to the enabling circuit for monitoring the current of the first driver and the a current of the second driver to generate the control signal; and an external circuit coupled between the first operational amplifier and the inverting input of the second operational amplifier for adjusting the An operational amplifier and at least a DC voltage of the second operational amplifier such that the first operational amplifier and the second operational amplifier have the same DC offset, the external circuit comprising: at least one tap variable resistor coupled To a reference device, wherein the constant current of the first operational amplifier is different from the DC voltage of the first operational nose amplifier when the tap variable resistor selective tap is at different positions. 201115908 This drive's drive amplifier circuit is simpler than the prior art circuit structure, and can also avoid the problem of breakdown current. [Embodiment] In the specification and subsequent patents, the patent transcripts are used to refer to certain elements to refer to specific components. Those who have the usual knowledge should understand that manufacturers may use different nouns to refer to the same component. The scope of this specification and subsequent towel claims does not distinguish the components by the difference of the name, but the difference in function of the components is used as the distinction. The "including" and "including" mentioned in the rhyme and subsequent claims are _ open-ended terms and should be interpreted as including but not limited to. In addition to “alpha”, “words”—the words in this system contain any direct and indirect electrical connection. Indirect electrical connections include connections through other devices. 1 is a schematic view of a drive amplifier circuit 100 in accordance with one embodiment of the present invention. The driving amplifier circuit 1A includes a p operational amplifier 110 and a chirp operational amplifier 12A, wherein the two operational amplifiers are coupled to a differential load current 'and can be referred to as a p operational amplifier u and a chirp operational amplifier 120, respectively. It is a first operational amplifier and a second operational amplifier. ρ operational amplifier 110 and Ν operational amplifier 12 〇 are respectively coupled to PMOS driver 201115908

MPD以及NMOS驅動器MND，以下將pm〇S驅動器MPD以及 NMOS驅動器MND分別稱之爲第一驅動器MpD以及第二驅動器 MND。P運算放大器11〇的輸出進一步耦接到一個第一切換開關 SWp，而第一切換開關SWp耦接到偏移電流，而n運算放大器120 的輸出進一步耦接到一個第二切換開關SWn，而第二切換開關 SWn也耦接到上述偏移電流。可以透過第一偏移電路以及第二偏移電路，分別偏移第一驅動器MPD以及第二驅動器MND，在本 • 實施例中，可以透過P偏移電晶體MPB以及N偏移電晶體MNB 的方式提供偏移電流，即偏移第一驅動器MPD以及第二驅動器 MND，所以P偏移電晶體MPB以及N偏移電晶體MNB可以為第一偏移電路以及第二偏移電路的一個具體實施例。第一驅動器 MPD以及第二驅動器MND的輸出，分別透過第一比例(sca丨ing) 電路以及第二比例電路，耦接到數位控制電路丨5〇，其中，第一比例電路耦接到該第一驅動器MPD，用於產生一第一成比例(scaled) Φ 電流’該第一成比例電流與該輸出至該數位控制電路150之第一驅動器MPD之該電流成正比，而一第二比例電路，輕接到該第二驅動器_D，用於產生一第二成比例電流，該第二成比例電流與輸出至該數位控制電路150之該第二驅動器_d之該電流成正比，而上述第一比例電路以及第二比例電路在此實施例中可以分別實現為第一比例電晶體MPS以及第二比例電晶體MNS，然本發明不以此為限，任何可以實現上述功能電路皆可。所以在此實施例中，第一驅動器MPD以及第二驅動器MND的輸出分別透過 201115908 第一比例電晶體MPS以及第《 —比例電晶體MNS，耗接到數位控制電路150。而數位控制電路150的輸出控制訊號ctrl輕接到第一切換開關SWP以及第二切換開關SWn。如果控制訊號ctrl為高位準(第一邏輯位準）’則第一切換開關SWp打開，而第二切換開關SWn閉合，如果控制訊號CTRL為低(第二邏輯位準)則反之亦然。此實施例中，第一切換開關SWP以及第二切換開關swn可以稱之為一個賦能電路，用於分別耦接第一偏移電路，例如p偏移電晶體MPS ’以及第二偏移電路，例如N偏移電晶體MNS，並且根據控制訊號CTRL賦能該第一偏移電路或者第二偏移電路，而上述過程亦可總結為數位控制電路15〇監視該第一成比例電流以及該第二成比例電流’以產生該控制訊號，請注意，第1 圖中的IB代表源電流，Ccp、Ccn為電容，VDD為電源電壓，而In-、 In+代表輸入。驅動放大器電路100利用數位控制電路150以透過第一切換開關SWP或者第二切換開關SWn，啓動第一驅動器MPD或者第二驅動器_D。當第一切換開關SWP打開而第二切換開關SWn 閉合時，P運算放大器110直接耦接到第一驅動器MPD，以驅動第一驅動器MPD為負載160提供電流，所以第一驅動器MPD承載負載電流加上偏移電流’而第二驅動器MND僅僅由偏移電流偏移’即第二驅動器MND被偏移。反之亦然，當第一切換開關SWP 閉合而第二切換開關SWn打開時，N運算放大器120直接耦接到 201115908 第二驅動n卿’训於驅麵二驅動器麵自負載_收電流，第二鶴HMND承細移電流減去負載餘，而第一驅動器MPD僅僅由偏移電流偏移，即第一驅動器猶被偏移。當負載電流變爲零或者變爲正，即為—個標認：驅動放大器電路⑽需要電流流出，因此，驅㈣在這—點切換，經由此操作第一驅動H MND偏料偏移電流，而第―驅動器MpD開啓 (active)。相似地’當負載電流變爲零或者變爲負，那也是一個標遠、.驅動放大器100需要沒取電流，而驅動器在這一點再一次切換。由於驅動放大器電路100的對稱，當系統沒有訊號輸入時，穿過第一驅動器MPD以及第二驅動器mnd的電流等於偏移電流，而在負載處沒有電流。在此情況下，第一驅動器MpD或者第二驅動器MND中的任何一者都可以開啓。請參閱第2圖’第2圖為如第1圖所示的數位控制電路15〇的示意圖。比例電晶體MPS以及比例電晶體MNS承載比第一驅動器MPD以及第二驅動器MND中電流的按比例縮小 (scaled-down)的電流。數位控制電路150由第一比較器152以及第二比較器154組成(第一比較器152以及第二比較器154用於比較電流的大小，所以亦可稱之爲第一電流比較器以及第二電流比較器）’其中，第一比較器152用於將比例電晶體MPS中的電流Ip 與第一參考電流Iref_p作比較，而第二比較器154用於將比例電晶 201115908 體MNS中的電流In與第二參考電流Iref_n作比較，其中，該第一參考電流Iref-p具有位於零與該偏移第一驅動器MPD的偏移電流幅度之間的一個絕對值，該第二參考電流iref_n具有位於零與該偏移第二驅動器MND的偏移電流幅度之間的一個絕對值。第一比較器 152以及第二比較器154分別耦接到第一斯密特(Schmitt)緩存器 (buffer)162以及第二斯密特緩存器164，用於根據第一比較器152 以及第二比較器154的比較結果分別輸出第一觸發訊號以及第二觸發訊號，並作爲閂鎖單元170的輸入訊號，其中，第一觸發訊號以及第二觸發訊號分別輸入閂鎖單元170的s端以及R端(如圖所示）。上述號都輸入到閂鎖單元170，以及根據第一觸發訊號以及第二觸發訊號，設定(set)或者重置(reset)閂鎖單元】7〇 t進一步說，當沒有訊號時，因此負載電流存在，則閂鎖單元17〇仍然根據一個設定或者重置狀態而於輸出端(標記為⑹輸出一個控制訊號。該控舰雜出然後送人第三斯密特緩存^⑽，織輸出控制ifl號CTRL爿第-切換開關sWp以及第二切換開關％。 ««月參閲第1圖以及第2 EU。參考第丨圖中的驅動放大器電路 100 ’下面描述第2圖中的數位控制電路15〇。假設驅動放大器電路100的初始階段為第一切換開關SWp打開，而第二切換開關W 閉合，數健舰號CTRL為高鱗，所關練A||電路1〇〇 ^出電流’而第二驅動器MND具有偏移電流。因此通過第一驅動器MPD的電机為負載電流加上偏移電流。如果負載電流變爲零或 12 201115908 更低那麽數位控制電路i5〇的第一比較器⑸將跳脫㈣），同寺向門鎖單7〇 Π0輪出訊號，該訊號指示驅動器連接需要被切 :制M CTRL因此會變爲低位準，所以第一驅動器承 ^偏移電細帛二1_ $ MND錢絲電流減去負载電流的電The MPD and the NMOS driver MND, the pm 〇 S driver MPD and the NMOS driver MND are hereinafter referred to as a first driver MpD and a second driver MND, respectively. The output of the P operational amplifier 11A is further coupled to a first switching switch SWp, and the first switching switch SWp is coupled to the offset current, and the output of the n operational amplifier 120 is further coupled to a second switching switch SWn, and The second changeover switch SWn is also coupled to the offset current described above. The first driver MPD and the second driver MND may be respectively offset by the first offset circuit and the second offset circuit. In the embodiment, the P offset transistor MPB and the N offset transistor MNB may be transmitted. The method provides offset current, that is, offsets the first driver MPD and the second driver MND, so the P offset transistor MPB and the N offset transistor MNB can be a specific implementation of the first offset circuit and the second offset circuit. example. The outputs of the first driver MPD and the second driver MND are respectively coupled to the digital control circuit 丨5〇 through a first proportional (sca丨ing) circuit and a second proportional circuit, wherein the first proportional circuit is coupled to the first a driver MPD for generating a first scaled Φ current 'the first proportional current is proportional to the current output to the first driver MPD of the digital control circuit 150, and a second proportional circuit Lightly connected to the second driver_D for generating a second proportional current, the second proportional current being proportional to the current output to the second driver_d of the digital control circuit 150, and the above The first proportional circuit and the second proportional circuit can be implemented as the first proportional transistor MPS and the second proportional transistor MNS in this embodiment. However, the present invention is not limited thereto, and any of the above functional circuits can be implemented. Therefore, in this embodiment, the outputs of the first driver MPD and the second driver MND are respectively transmitted through the first proportional transistor MPS and the "proportional transistor MNS" of the 201115908 to the digital control circuit 150. The output control signal ctrl of the digital control circuit 150 is lightly connected to the first changeover switch SWP and the second changeover switch SWn. If the control signal ctrl is at a high level (first logic level) then the first switch SWp is turned on and the second switch SWn is closed, if the control signal CTRL is low (second logic level), and vice versa. In this embodiment, the first switching switch SWP and the second switching switch swn may be referred to as an enabling circuit for respectively coupling the first offset circuit, such as the p-offset transistor MPS' and the second offset circuit. For example, the N offset transistor MNS, and the first offset circuit or the second offset circuit is enabled according to the control signal CTRL, and the above process can also be summarized as the digital control circuit 15 monitoring the first proportional current and the The second proportional current 'to generate the control signal, please note that IB in Figure 1 represents the source current, Ccp, Ccn is the capacitor, VDD is the supply voltage, and In-, In+ represents the input. The drive amplifier circuit 100 activates the first driver MPD or the second driver_D by the digital control circuit 150 to transmit the first switch SWP or the second switch SWn. When the first switch SWP is open and the second switch SWn is closed, the P operational amplifier 110 is directly coupled to the first driver MPD to drive the first driver MPD to supply current to the load 160, so the first driver MPD carries the load current plus The upper offset current 'the second driver MND is only offset by the offset current', ie the second driver MND is offset. Vice versa, when the first changeover switch SWP is closed and the second changeover switch SWn is open, the N operational amplifier 120 is directly coupled to the 201115908 second drive nqing's training on the drive surface of the driver surface from the load _ current, second The crane HMND takes the fine current and subtracts the load remaining, while the first driver MPD is only offset by the offset current, that is, the first driver is still offset. When the load current becomes zero or becomes positive, it is a mark: the drive amplifier circuit (10) needs current to flow out, therefore, the drive (4) is switched at this point, through which the first drive H MND offset offset current is driven, The first drive MpD is active. Similarly, when the load current becomes zero or becomes negative, it is also a far distance. The driver amplifier 100 needs to take no current, and the driver switches again at this point. Due to the symmetry of the driver amplifier circuit 100, when the system has no signal input, the current through the first driver MPD and the second driver mnd is equal to the offset current, and there is no current at the load. In this case, either of the first driver MpD or the second driver MND can be turned on. Please refer to Fig. 2'. Fig. 2 is a schematic diagram of the digital control circuit 15A as shown in Fig. 1. The proportional transistor MPS and the proportional transistor MNS carry a scaled-down current compared to the currents in the first driver MPD and the second driver MND. The digital control circuit 150 is composed of a first comparator 152 and a second comparator 154 (the first comparator 152 and the second comparator 154 are used to compare the magnitude of the current, so it may also be referred to as a first current comparator and a second a current comparator) 'where the first comparator 152 is for comparing the current Ip in the proportional transistor MPS with the first reference current Iref_p, and the second comparator 154 is for converting the current in the body MNS of the proportional transistor 201115908 In is compared with a second reference current Iref_n, wherein the first reference current Iref-p has an absolute value between zero and an offset current amplitude of the offset first driver MPD, the second reference current iref_n having An absolute value between zero and the offset current amplitude of the offset second driver MND. The first comparator 152 and the second comparator 154 are respectively coupled to the first Schmitt buffer 162 and the second Schmitt buffer 164 for using the first comparator 152 and the second The comparison result of the comparator 154 outputs the first trigger signal and the second trigger signal respectively, and serves as an input signal of the latch unit 170, wherein the first trigger signal and the second trigger signal are respectively input to the s terminal and the R of the latch unit 170. End (as shown). The above numbers are all input to the latch unit 170, and set or reset the latch unit according to the first trigger signal and the second trigger signal. 7〇t further, when there is no signal, the load current If present, the latch unit 17 is still outputting a control signal according to a set or reset state (labeled as (6). The control ship is mixed and then sent to the third Schmitt cache ^ (10), and the output control ifl No. CTRL 爿 first-switch sWp and second switch %. « «Mono 1 and 2 EU. Refer to drive amplifier circuit 100 in FIG. 2 ' The digital control circuit 15 in FIG. 2 is described below. It is assumed that the initial stage of the driving amplifier circuit 100 is that the first switching switch SWp is turned on, and the second switching switch W is closed, and the number of the ship number CTRL is a high scale, and the A|| The second driver MND has an offset current. Therefore, the motor passing through the first driver MPD adds an offset current to the load current. If the load current becomes zero or 12 201115908 is lower, then the first comparator (5) of the digital control circuit i5〇 Jump (4)), with the temple door lock single 7 〇Π 0 round signal, the signal indicates that the drive connection needs to be cut: M CTRL will therefore become low level, so the first drive is offset by the electric 帛 2 1_ $ MND money wire current minus load current

一而負載U _&取。如果貞載電流再次跳脫為零或者更冋，數位控制電路15G的第二比較ϋ 154將會跳脫，因此重置問鎖早凡170。這將會引起控制訊號CTRL變爲高位準，而第二驅動器MND可財載偏移電流而第—驅㈣MpD將會輸出電流。上述兩個狀‘_為觀狀態。進―錢，斯料緩存器可以保證輸出常數訊號，而斯密特緩存器具有滯後(hysteresis)功能。這也保。且，即使電仙_在參考電流處振盈，那麼數位控制電流也不會輸出一個一直改變的控制訊號。當沒有負載電流存在時，通過第一驅動器MPD的電流將等於偏移電流，而通過_〇的電流等於負的偏移電流。因此依賴於驅動放大器電路1〇〇的先前的狀態，控制§fl號CTRL可以或者為高位準’或者為彳氏位準。仍然可以提供驅動放大器電路100的穩定狀態。當通過第二驅動器MND的電流(例如)接近零，那麼不會很顯著的看出來。但是當第二驅動器MND的電流變爲正，而閃鎖單元 Π0跳脫第一切換開關SWP以及第二切換開關s\Vn，所以第一驅動器MPD此時輸出電流給驅動放大器電路100，通過第二驅動器 MND的電流「跳」回到偏移電流。驅動放大器電路1〇〇因此提供 13 201115908 一在電流流出（current source)以及電流汲取(current sinking)之間自動切換的完全數位方法。在數位控制電路15〇中的斯密特緩存器的使用允許數位控制’而且也消除了數位控制電路15〇周圍的連續時間(continuous-time)回授(feedback)。該電路系統不比傳統的實現複雜’也阻止了擊穿電流(sh〇〇t-through current)的問題的產生。進一步s兑，甚至當沒有存在負載電流時，數位控制電路賦能該驅動放大器電路1〇〇總是運作於穩定狀態。在閉環(closed-loop)條件下，當沒有訊號輸入時，p運算放大器以及N運算放大器的直流偏置(dc 0ffset)可能是不同的。因此，當控制訊號為高位準時，輸出端的直流電壓將於控制訊號為低位準時不同。違閉j展直流偏置需要被等化，以避免發生電路產生超過平均值或者類比接地門檻值信號的情況。為了抵消該問題，分別依據本發明的第二實施例以及第三實施例的提供利用直流偏置校準的驅動放大器。One load U _& If the load current jumps again to zero or more, the second comparison ϋ 154 of the digital control circuit 15G will trip, so the reset lock is 170. This will cause the control signal CTRL to go to a high level, while the second driver MND can carry the offset current and the first (four) MpD will output the current. The above two states are _ _ view state. Into the money, the material buffer can guarantee the output of constant signals, while the Schmitt buffer has hysteresis function. This is also guaranteed. Moreover, even if the electric singer _ vibrates at the reference current, the digital control current will not output a control signal that has been changed. When no load current is present, the current through the first driver MPD will be equal to the offset current, while the current through _〇 is equal to the negative offset current. Therefore, depending on the previous state of the driver amplifier circuit 1 控制, the control §fl number CTRL can be either a high level or a 彳 level. A steady state of the driver amplifier circuit 100 can still be provided. When the current through the second driver MND is, for example, close to zero, it will not be noticeable. However, when the current of the second driver MND becomes positive, and the flash lock unit Π0 trips off the first changeover switch SWP and the second changeover switch s\Vn, the first driver MPD outputs a current to the drive amplifier circuit 100 at this time. The current of the second driver MND "jumps" back to the offset current. The driver amplifier circuit 1 thus provides a fully digital method of automatically switching between current source and current sinking. The use of a Schmitt buffer in the digital control circuit 15A allows for digital control' and also eliminates the continuous-time feedback around the digital control circuit 15A. This circuit system is no more complex than conventional implementations and also prevents the occurrence of sh〇〇t-through current problems. Further, even when there is no load current, the digital control circuit is enabled. The drive amplifier circuit 1 〇〇 always operates in a stable state. Under closed-loop conditions, the DC offset (dc 0ffset) of the p-op amplifier and the N op amp may be different when there is no signal input. Therefore, when the control signal is high, the DC voltage at the output will be different when the control signal is low. The DC offset of the yoke must be equalized to avoid the occurrence of a circuit that exceeds the average or analog ground threshold signal. In order to counteract this problem, a drive amplifier calibrated with a DC offset is provided in accordance with the second embodiment of the present invention and the third embodiment, respectively.

清參考第3圖。第3圖為根據本發明的第二實施例的驅動放大器電路300的示意圖。除驅動放大器電路300包含偏置等化 (offset equalization)電路310外，驅動放大器電路30〇的電路與第一實施例的電路基本相同。偏置等化電路31〇耦接到p運算放大器110以及N運算放大器120的内部節點(internal node)上。偏置等化電路310選擇性地調整p運算放大器110以及n運算放大器 120的一者或者兩者的直流偏置，以保證P運算放大器丨10以及N 201115908 運算放大器120均具有相等的直流偏置。偏置等化電路31〇可以各種方式實現。偏置等化電路310可以包含多個加權電流源或者夕個電阻。偏置等化電路31Q可以透過控制訊號的使用而校準，，或者在測試級校準。本領域技術人員可以瞭解，組成偏置等化電路的各個單元可以進行很多修改和變形，但是沒有偏離偏置等化的效果。偏置等化電路因此不僅限於上述實現，在不偏離本發明的精神的範圍内，可以對設計做各種修改和變形。 · W 本發明也提供了另一個可以達到同樣的效果但是不需要校準的電路。請參考第4圖。第4圖為根據本發明的第三實施例的驅動放大器電路400的示意圖。可以使用外部電路調整p運算放大器110以及N運算放大器120的直流偏置，在此實施例中，外部電路可以實施為外部電阻。在電路4〇〇中，p運算放大器11〇以及 N運算放大器120的兩者的反相輸入端，都連接到多個電阻化八、 Rcb、Rda、Rdb 以及 Rt ’ 其中 ’ Rt 為抽頭可變(tapped variable)電 • 阻。此外，電阻Rca以及Rcb連接到接地端。具體說來，電阻Rda 以及Rdb串聯耦接抽頭可變電阻RT，電阻Rda耦接到P運算放大器的反相輸入端，以及電阻RDB耦接到N運算放大器的反相輸入端’電阻Rca以及Rcb串聯耦接在接地端、電阻Rda以及電阻Rdb 之間。並且電阻Rb以及Ra串聯耦接在驅動放大器電路400的輸出端以及輸入電壓Vin之間，用於設定一閉環增益。A電阻對以及B電阻對(即，以及Rcb，以及RDA以及rdb)具有相同的值(電阻值）。電阻RT具有比其他電阻更小的電阻值，例如，電阻RT具 15 201115908 有比電阻Rca、R〇b、R〇a以及Rdb小幾個數量級的電阻值。電阻 RT的抽頭(tap)具有參考電壓Vref。參考電壓Vref的值以及其他電阻的值可以選擇為，例如當RT的抽頭處在中點時，p運算放大器 110以及N運算放大器12〇的反相輸入端的出現某一電壓(類比地)。當該柚頭被從中點移走，分別的反相輸入端的直流電壓不同。因此，如果確實在P運算放大器110以及N運算放大器12〇之間存在直流偏置的話，透過移走電阻！^的抽頭，那麼直流偏置可以校正(corrected)。以此方式，控制電壓就可以從高位準切換到低位準(反之亦然）’因此在驅動放大器電路4〇〇的輪出端就不會有電壓的改變。在第4圖巾’電阻^以及Rb為搞接於輸人電壓心以及負載160之間的電阻。本發明因此提供了没取電流以及流入電流(如㈣㈣ sourdngcurrent)的自動控制，也提供了用於補償任何直流偏置的方法，該直流龍在自動控制發生時，在運算放A||上出現。任何熟1此項技藝者’在不脫離本發明之精神和範圍内，當可做些#的更賴潤飾，因此本發明之保護制當視所附之申請專利範圍所界定者為準。【圖式簡單說明】第1圖為根據本發明的__個實施例的驅動放大器電路的示意 201115908 圖。第2圖為如第1圖所示的數位控制電路的示意圖。 - 第3圖為根據本發明的第二實施例的驅動放大器電路的示意，圖。第4圖為根據本發明的第三實施例的驅動放大器電路的示立圖。【主要元件符號說明】 100〜驅動放大器電路； 110〜P運算放大器； 120〜N運算放大器； 150〜數位控制電路； 160〜負載； 152〜第一比較器； 154〜第二比較器； 162〜第一斯密特緩存器； 164〜第二斯密特緩存器； 170〜閂鎖單元； 180〜第三斯密特緩存器； 300〜驅動放大器電路； 310〜偏置等化電路； 17 201115908 400〜驅動放大器電路； swp〜第一切換開關； swn〜第二切換開關； MPD〜第一驅動器； MND〜第二驅動器； MPB-P偏移電晶體； MNB〜N偏移電晶體； MPS，MNS〜比例電晶體； φ CTRL〜控制訊號；See Figure 3 for details. Figure 3 is a schematic illustration of a drive amplifier circuit 300 in accordance with a second embodiment of the present invention. The circuit of the drive amplifier circuit 30A is substantially the same as the circuit of the first embodiment except that the drive amplifier circuit 300 includes an offset equalization circuit 310. The bias equalization circuit 31 is coupled to the p operational amplifier 110 and the internal node of the N operational amplifier 120. The bias equalization circuit 310 selectively adjusts the DC bias of one or both of the p operational amplifier 110 and the n operational amplifier 120 to ensure that the P operational amplifier 丨10 and the N 201115908 operational amplifier 120 have equal DC offsets. . The bias equalization circuit 31 can be implemented in various ways. The bias equalization circuit 310 can include a plurality of weighted current sources or a single resistor. The bias equalization circuit 31Q can be calibrated by the use of control signals, or calibrated at the test level. Those skilled in the art will appreciate that the various components that make up the bias equalization circuit can be modified and deformed in many ways, but without the effect of offsetting the equalization. The biasing equalization circuit is thus not limited to the above-described implementation, and various modifications and changes can be made to the design without departing from the spirit of the invention. · W The present invention also provides another circuit that achieves the same effect but does not require calibration. Please refer to Figure 4. Fig. 4 is a schematic diagram of a drive amplifier circuit 400 in accordance with a third embodiment of the present invention. The external circuit can be used to adjust the DC bias of the p operational amplifier 110 and the N operational amplifier 120. In this embodiment, the external circuit can be implemented as an external resistor. In the circuit 4A, the inverting input terminals of both the p operational amplifier 11A and the N operational amplifier 120 are connected to a plurality of resistive VIII, Rcb, Rda, Rdb, and Rt ' where 'Rt is a tap variable (tapped variable) electricity resistance. Further, the resistors Rca and Rcb are connected to the ground. Specifically, the resistors Rda and Rdb are coupled in series with the tap variable resistor RT, the resistor Rda is coupled to the inverting input of the P operational amplifier, and the resistor RDB is coupled to the inverting input of the N operational amplifier 'resistors Rca and Rcb The series is coupled between the ground, the resistor Rda, and the resistor Rdb. The resistors Rb and Ra are coupled in series between the output of the driver amplifier circuit 400 and the input voltage Vin for setting a closed loop gain. The A resistor pair and the B resistor pair (i.e., Rcb, and RDA and rdb) have the same value (resistance value). Resistor RT has a smaller resistance than other resistors. For example, resistor RT 15 201115908 has several orders of magnitude smaller than resistors Rca, R〇b, R〇a, and Rdb. The tap of the resistor RT has a reference voltage Vref. The value of the reference voltage Vref and the value of the other resistors may be selected such that, for example, when the tap of the RT is at the midpoint, a certain voltage (analog) occurs at the inverting input terminals of the p operational amplifier 110 and the N operational amplifier 12A. When the pomelo head is removed from the midpoint, the DC voltages at the respective inverting inputs are different. Therefore, if there is a DC offset between the P operational amplifier 110 and the N operational amplifier 12A, the resistance is removed by transmission! The tap of ^, then the DC offset can be corrected. In this way, the control voltage can be switched from a high level to a low level (and vice versa) so that there is no voltage change at the wheel-out of the driver amplifier circuit 4A. In the fourth figure, the resistances and Rb are the resistances between the input voltage and the load 160. The present invention thus provides automatic control of no current draw and current flow (such as (4) (4) sourdngcurrent), and also provides a method for compensating for any DC offset that occurs on the operational amplifier A|| when automatic control occurs. . Any of the skilled artisans will be able to make some of the refinements of the present invention without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram of a drive amplifier circuit according to an embodiment of the present invention 201115908. Fig. 2 is a schematic diagram of a digital control circuit as shown in Fig. 1. - Figure 3 is a schematic view of a drive amplifier circuit in accordance with a second embodiment of the present invention. Fig. 4 is a perspective view showing a drive amplifier circuit according to a third embodiment of the present invention. [Major component symbol description] 100~ drive amplifier circuit; 110~P operational amplifier; 120~N operational amplifier; 150~digit control circuit; 160~ load; 152~1 first comparator; 154~second comparator; First Schmitt buffer; 164~second Schmitt buffer; 170~latch unit; 180~third Schmitt buffer; 300~drive amplifier circuit; 310~bias equalization circuit; 17 201115908 400~ drive amplifier circuit; swp~first switch; swn~second switch; MPD~first driver; MND~second driver; MPB-P offset transistor; MNB~N offset transistor; MPS, MNS~proportional transistor; φ CTRL~ control signal;

Ib〜源電流， V〇d〜電源電壓；Ib ~ source current, V〇d ~ power supply voltage;

In-，In+〜輸入；In-, In+~ input;

Ccp，Ccn〜電容；Ccp, Ccn~ capacitor;

Ip〜電流，Ip~ current,

In〜電流，In ~ current,

Iref-p 〜第一參考電流；Iref-p ~ first reference current;

Iref-n 〜第二參考電流；Iref-n ~ second reference current;

Vin〜輸入電壓；Vin~ input voltage;

Ra、Rb、Rca、Rcb、Rda、Rdb、電阻。 18Ra, Rb, Rca, Rcb, Rda, Rdb, resistance. 18

Claims

201115908 七、申請專利範圍： - 1. 一種驅動放大器電路，包含： • 一第一驅動器，用於流出一負載電流至一負載；一第二驅動器，用於自該負載汲取該負載電流； -第-運算放大器，接到—差動輸人訊號，該第一運算放大器用於驅動該第一驅動器； • U算放大11 ’祕卿差動輸人訊號，該第二運算放大器用於驅動該第二驅動器；一第一偏移電路，用於偏移該第一驅動器；一第二偏移電路，用於偏移該第二驅動器； -賦能電路’祕到該第—偏移電路以及該第二偏移電路，用於根據-控觀號賦能該第—偏移電路或者該第二偏移電路； -數位控制電路’雛職賦能電路，祕監視該第一驅動鲁器之電流以及該第二驅動器之電流，以產生該控制訊號；以及 -偏置等化電路，_在該第—運算放大器之—内部節點以及該第二運算放大ϋ的-内部節點之間，驗機該第—運算放大器以及該第二運算放大器之至少—者的直流偏置，以使該第一運算放大器以及邊第二運算放大器具有相同的直流偏置。 2.如申請專利範圍第1項所述之驅動放大器電路，其中，該賦能電路包含： I 201115908 一第一切換開關，用於根據該控制訊號’將該第—驅動器輕接至該第一偏移電路；以及一第二切換開關，用於根據該控制訊號’將該第二驅動器輕接至該第二偏移電路。 3.如申請專利範圍第2項所述之驅動放大器電路，其中當該控制號具有一第一邏輯位準時，該第一切換開關打開，該第二切換開關閉合，以使該第一驅動器開啓及該第二驅動器被偏移；當該控制訊號具有一第二邏輯位準時，該第一切換開關閉合，而 δ亥第二切換開關開啓，以使該第一驅動器被偏移及該第二驅動器開啓。 4·如申請專利範圍第1項所述之驅動放大器電路，其中，該數位控制電路將該第一驅動器之電流與一第一參考電流作比較，乂及將邊第二驅動器之電流與一第二參考電流做比較，以及該數鲁控制電路利用比較結果產生該控制訊號，以用於該賦能電路。 •如申請專利範圍第4項所述之驅動放大器電路，其中，該數位控制電路包含：一第一電流比較器，用於將該第一驅動器之該電流與該第〆參考電流做比較；一第二電流比較器，用於將該第二驅動器之該電流與該第二 20 201115908 參考電流做比較； -第-斯密特緩存n，祕龍第_電流比較器，用於根據該第-電流比較器之—比較結果，輸出一第一觸發訊號；一第一斯密特緩存11 ’输龍第三電流味n，用於根據該第二電流比較器之—比較結果，輸出-第二觸發訊號；以及 -閃鎖單7L ’缺_第—斯密特緩存器以及該第二斯密特緩存器、’用於根據該第一觸發訊號以及該第二觸發訊號，輪出 • 該控制訊號。 6.如申„月專利範圍第5項所述之驅動放大器電路，其中，該數位控制電路進一步包含：第二斯密特緩存器’輕接到該閃鎖單元，用於緩存該控制訊號。鲁 L如申睛專利範圍第5項所述之驅動放大器電路，其中，該一參考電流具有位於零與已偏移之該第一驅魅之— 幅度間之一紹电〇〇、、f值，邊第二參考電流具有位於零與該偏移第二驅動益之-偏移電流幅度間之一絕對值。 8·如申請專利範11第1項所述之驅動放大H電路，進一步包含：第比例電路，輕接到該第一驅動器，用於產生一第一成 21 201115908 比例電流，該第-成比例電流與該輪出至該數位控制電路之該第一驅動器之電流成比例；以及 -第二比例電路，制該第二驅動器，用於產生—第二成比例電流，該第二成比例的電流與輪出至該數位控制電路之該第 * 二驅動器之該電流成比例；其中’該數位控制電路監視該第一成比例電流以及該第二成比例電流，以產生該控制訊號。 9. 如申請專利範圍第丨項所述之驅動放大器電路，其中，該 ® 偏置等化電路包含多個加權電流源或者多個電阻。 10. 如申請專利範圍第丨項所述之驅動放大器電路，其中，該偏置等化電路可以被校準。 11· 一種驅動放大器電路，包含：一第-驅動器，用於流出一負載電流至一負載； · 一第二驅動器，用於自該負載汲取該負載電流；第運鼻放大器，輕接到一差動輸入訊號，該第一運算放大器用於驅動該第一驅動器；一第二運算放大器，耦接到該差動輸入訊號，該第二運算放 · 大器用於驅動該第二驅動器；一第一偏移電路，用於偏移該第一驅動器； 22 201115908 一第二偏移電路，用於偏移該第二驅動器；一賦能電路，耦接到該第一偏移電路以及該第二偏移電路，用於根據一控制訊號賦能該第一偏移電路或者該第二偏移電路； 1 一數位控制電路，耦接到該賦能電路，用於監視該第一驅動器之電流以及該第二驅動器之電流，以產生該控制訊號；以及一外部電路’耦接到該第一運算放大器以及該第二運算放大器的反相輸入端之間，用於調整該第一運算放大器以及該第二運 ^ 算放大器的至少一者的直流偏置，以使該第一運算放大器以及該第二運真放大器具有相同直流偏置，其中該外部電路包含：至少一抽頭可變電阻，耦接到一參考電器，其中，當該抽頭可變電阻選擇性抽頭在不同位置時，該第一運算放大器的一直流電壓與該第二運算放大器的直流電壓不同。 12. 如申請專利範圍第11項所述之驅動放大器電路，其特徵在於，該外部電路進一步包含： # 一第一電阻以及一第二電阻，串聯耦接該抽頭可變電阻，該第一電阻耦接到該第一運算放大器的反相輸入端，以及該第二電阻耦接到該第二運算放大器的反相輸入端；以及一第三電阻以及一第四電阻，串聯耦接在接地端、該第一電阻以及該第二電阻之間。 13. 如申請專利範圍第12項所述之驅動放大器電路，進一步包含： 23 201115908 --第五電阻以及一第六電阻’串聯轉接在該驅動放大器電路的輸出端以及該輸入電壓之間，用於設定一閉環增益。 14. 如申請專利範圍第12項所述之驅動放大器電路，其中，該第-電阻以及該第二電阻具有_電阻值，該第三電阻以及該第四電阻具有_f阻值，以及該_可變f阻具有比該第一電阻以及該第三電阻更小的一電阻值。 15. 如申請專利範圍第u項所述之驅動放大器電路，其中，⑩ 該賦能電路包含： ' -第-切換開關’用於根據該控制訊號將該第一驅動器搞接到該第一偏移電路；以及 -第二切換開關’麟根據該控制減將該第二驅動器柄接到該第二偏移電路。 ,I6.如申睛專利範圍第u項所述之驅動放大器電路，其中，鲁當該控制訊號具有—第一邏輯位準時，該第一切換開關為打開，而4第一切換開關閉合，以使該第—驅動器為開啟而該第二驅動器為被偏移；以及當該控制訊號與有—第二邏輯位準時，該第一切換開關合以及該第二切換開關為打開，以使該第一驅動器為被偏移以及該第二驅動器為驅動器。 17.如申請專利範圍第u項所述之驅動放大器電路，其中，該數位控制電路將該第-驅動器以及該第二驅㈣的電流與參考 24 201115908 電流做比較，然後利用比較結果以產生該控制訊號，從而傳輸給該賦能電路。 t 18.如申請專利範圍第Π項所述之驅動放大器電路，其中，該數位控制電路包含：一第一電流比較器，用於將該第一驅動器的電流與一第一參考電流做比較；一第二電流比較器，用於將該第二驅動器的電流與一第二參 ®考電流做比較；一第一斯密特緩存器，耦接到該第一電流比較器，用於依據 s亥第一電流比較器的一比較結果輸出一第一觸發訊號；一第二斯密特緩存器，耦接到該第二電流比較器，用於依據。亥第一電(;IL比較器的一比較結果輸出一第二觸發訊號；以及一閂鎖器，耦接到該第一斯密特暫存器以及該第二斯密特緩存器，用於依據該第一觸發訊號以及該第二觸發訊號輸出該控制 φ 訊號。 19. 如申請專利範圍第18項所述之驅動放大器電路，其中，該數位控制訊號進一步包含： _ 一第三斯密特緩存器，耦接到該閂鎖器，用於緩存該控制訊 .號。 20. 如申請專利範圍第18項所述之驅動放大器電路，其中，該第一參考電流與有位於零以及該已偏移第一驅動器的—偏移電 25 201115908 流幅度之間之，對值’以及該第二參考電流具有位於零以及該已偏移第·一，驅動器的一偏移電流幅度之間之一絕對值。 21.如申請專利範圍第η項所述之驅動放大器電路，進一步包含：一第一比例電路，轉接到該第一驅動器，用於產生與該第一驅動器的電流成比例的一第一成比例電流，從而傳輸給該數位控制電路；以及一第二比例電路，耦接到該第二驅動器，用於產生與該第二驅動器的電流成比例的一第二成比例電流，從而傳輸給該數位控制電路；其中’該數位控制電路監視該第一成比例電流以及該第二成比例電流’以產生該控制訊號》八、圖式： 26201115908 VII. Patent application scope: - 1. A driver amplifier circuit comprising: • a first driver for discharging a load current to a load; a second driver for extracting the load current from the load; An operational amplifier, which receives a differential input signal, the first operational amplifier is used to drive the first driver; • a U amplification 11 ' secretive differential input signal, the second operational amplifier is used to drive the first a second driver; a first offset circuit for shifting the first driver; a second offset circuit for offsetting the second driver; - an enabling circuit 'secret to the first-offset circuit and the a second offset circuit, configured to enable the first offset circuit or the second offset circuit according to the control flag; - the digital control circuit's the enablement circuit, and monitor the current of the first driver And a current of the second driver to generate the control signal; and a bias equalization circuit, between the internal node of the first operational amplifier and the internal node of the second operational amplifier - the operational amplifier and a second operational amplifier is at least - by DC bias, so that the edge of the first operational amplifier and a second operational amplifier having the same DC bias. 2. The driver amplifier circuit of claim 1, wherein the enabling circuit comprises: I 201115908 a first switch for lightly connecting the first driver to the first according to the control signal An offset circuit; and a second switch for lightly connecting the second driver to the second offset circuit according to the control signal. 3. The driver amplifier circuit of claim 2, wherein when the control number has a first logic level, the first switch is opened, and the second switch is closed to enable the first driver to be turned on. And the second driver is offset; when the control signal has a second logic level, the first switch is closed, and the second switch is turned on, so that the first driver is offset and the second The drive is turned on. 4. The driver amplifier circuit of claim 1, wherein the digital control circuit compares the current of the first driver with a first reference current, and the current of the second driver and the first The two reference currents are compared, and the digital control circuit uses the comparison result to generate the control signal for the enabling circuit. The driver amplifier circuit of claim 4, wherein the digital control circuit comprises: a first current comparator for comparing the current of the first driver with the second reference current; a second current comparator for comparing the current of the second driver with the second 20 201115908 reference current; - a - Schmidt buffer n, a crypto-current comparator, for using the first The current comparator compares the result and outputs a first trigger signal; a first Schmitt buffer 11 'the third current smell n of the dragon, for outputting the second according to the comparison result of the second current comparator Trigger signal; and - flash lock single 7L 'missing_first-Schmidt buffer and the second Schmitt buffer, 'for rotating according to the first trigger signal and the second trigger signal Signal. 6. The driver amplifier circuit of claim 5, wherein the digital control circuit further comprises: a second Schmitt buffer 'lightly connected to the flash lock unit for buffering the control signal. The drive amplifier circuit of claim 5, wherein the reference current has a first offset between the zero and the offset - one of the amplitudes, and an f value The second reference current has an absolute value between zero and the offset second drive benefit-offset current amplitude. 8. The drive amplification H circuit of claim 11, wherein the method further comprises: a first ratio circuit coupled to the first driver for generating a first 21 201115908 proportional current, the first proportional proportional current being proportional to a current of the first driver that is rotated to the digital control circuit; a second proportional circuit for producing a second proportional current, the second proportional current being proportional to the current that is turned to the second driver of the digital control circuit; Wherein the digital control circuit monitors the first proportional current and the second proportional current to generate the control signal. 9. The drive amplifier circuit according to the scope of the application, wherein the offset, etc. The circuit includes a plurality of weighted current sources or a plurality of resistors. 10. The driver amplifier circuit of claim 2, wherein the bias equalization circuit can be calibrated. 11. A driver amplifier circuit comprising: a first driver for discharging a load current to a load; a second driver for extracting the load current from the load; and a nose amplifier for lightly receiving a differential input signal, the first operational amplifier For driving the first driver; a second operational amplifier coupled to the differential input signal, the second operational amplifier is for driving the second driver; and a first offset circuit for offsetting the a first driver; 22 201115908 a second offset circuit for offsetting the second driver; an enabling circuit coupled to the first offset circuit and the first An offset circuit, configured to enable the first offset circuit or the second offset circuit according to a control signal; 1 a digital control circuit coupled to the enabling circuit for monitoring current of the first driver and a current of the second driver to generate the control signal; and an external circuit coupled between the first operational amplifier and the inverting input of the second operational amplifier for adjusting the first operational amplifier and the And dc biasing of at least one of the second operational amplifiers, wherein the first operational amplifier and the second operational amplifier have the same DC offset, wherein the external circuit comprises: at least one tap variable resistor coupled And to a reference device, wherein when the tap variable resistor selectively taps at different positions, the DC voltage of the first operational amplifier is different from the DC voltage of the second operational amplifier. 12. The driver amplifier circuit of claim 11, wherein the external circuit further comprises: #一第一电阻 and a second resistor coupled to the tap variable resistor in series, the first resistor An inverting input coupled to the first operational amplifier, and the second resistor is coupled to the inverting input of the second operational amplifier; and a third resistor and a fourth resistor coupled in series to the ground Between the first resistor and the second resistor. 13. The driver amplifier circuit of claim 12, further comprising: 23 201115908 - a fifth resistor and a sixth resistor 'connected in series between the output of the driver amplifier circuit and the input voltage, Used to set a closed loop gain. 14. The driver amplifier circuit of claim 12, wherein the first resistor and the second resistor have a _ resistance value, the third resistor and the fourth resistor have a _f resistance value, and the _ The variable f resistance has a resistance value smaller than the first resistance and the third resistance. 15. The driver amplifier circuit of claim 5, wherein the enabling circuit comprises: '-the first-switching switch' for connecting the first driver to the first bias according to the control signal And shifting the circuit; and - the second switching switch 'the second driver handle is connected to the second offset circuit according to the control. I6. The driving amplifier circuit of claim 5, wherein when the control signal has a first logic level, the first switching switch is open, and the fourth first switching switch is closed, The first driver is turned on and the second driver is turned off; and when the control signal and the second logic level are present, the first switch is turned on and the second switch is turned on to enable the first switch A drive is offset and the second drive is a drive. 17. The driver amplifier circuit of claim 5, wherein the digital control circuit compares the current of the first driver and the second driver (four) with a current of reference 24 201115908, and then uses the comparison result to generate the The control signal is transmitted to the enabling circuit. The driver amplifier circuit of claim 2, wherein the digital control circuit comprises: a first current comparator for comparing current of the first driver with a first reference current; a second current comparator for comparing the current of the second driver with a second reference current; a first Schmitt buffer coupled to the first current comparator for A comparison result of the first current comparator outputs a first trigger signal; a second Schmitt buffer coupled to the second current comparator for use. a first power (a comparison result of the IL comparator outputs a second trigger signal; and a latch coupled to the first Schmitt register and the second Schmitt buffer for The control φ signal is output according to the first trigger signal and the second trigger signal. 19. The driver amplifier circuit of claim 18, wherein the digital control signal further comprises: _ a third Schmitt a buffer, coupled to the latch, for buffering the control signal. 20. The driver amplifier circuit of claim 18, wherein the first reference current is located at zero and the Offset the first driver - offset power 25 201115908 between the amplitudes of the flow, the value of 'and the second reference current has a position between zero and the offset one, one offset current amplitude of the driver 21. The drive amplifier circuit of claim n, further comprising: a first proportional circuit coupled to the first driver for generating a current proportional to the current of the first driver a first proportional current, which is transmitted to the digital control circuit; and a second proportional circuit coupled to the second driver for generating a second proportional current proportional to the current of the second driver, Thereby transmitting to the digital control circuit; wherein 'the digital control circuit monitors the first proportional current and the second proportional current ' to generate the control signal" VIII, Figure: 26