CN100413029C - 电路装置的制造方法 - Google Patents
电路装置的制造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 229920005989 resin Polymers 0.000 claims abstract description 67
- 239000011347 resin Substances 0.000 claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 238000000034 method Methods 0.000 claims description 42
- 238000005530 etching Methods 0.000 claims description 36
- 238000007789 sealing Methods 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 238000000576 coating method Methods 0.000 abstract description 7
- 239000011248 coating agent Substances 0.000 abstract description 6
- 230000004888 barrier function Effects 0.000 description 13
- 239000000463 material Substances 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 11
- 238000005755 formation reaction Methods 0.000 description 11
- 239000011888 foil Substances 0.000 description 9
- 239000000203 mixture Substances 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 7
- 239000000945 filler Substances 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000000428 dust Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229920005992 thermoplastic resin Polymers 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011256 inorganic filler Substances 0.000 description 1
- 229910003475 inorganic filler Inorganic materials 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
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Abstract
一种电路装置的制造方法,可容易且高精度地进行导电图案从包覆树脂的露出。在本发明的电路装置的制造方法中,在形成于电路衬底(16)表面的导电图案(18)上形成部分向上方突出的突出部(25)。其次,利用包覆树脂(26)包覆也包括突出部(25)的电路衬底16的表面。然后,进行包覆树脂(26)的蚀刻,使突出部(25)的上面露出。然后,进行电路元件(14)的固定及电连接。最后,密封形成于表面的电路,完成混合集成电路装置(10)。
Description
技术领域
本发明涉及电路装置的制造方法,特别是涉及具有包覆导电图案的包覆树脂的电路装置的制造方法。
背景技术
参照图7说明现有混合集成电路装置的结构(例如参照专利文献1)。图7(A)是混合集成电路装置100的立体图,图7(B)是图7(A)的X-X’线剖面图。
现有的混合集成电路装置100具有如下结构,其包括:矩形衬底106;绝缘层107,其设于衬底106的表面;导电图案108,其形成于该绝缘层107上;电路元件104,其固定在导电图案108上;金属细线105,其将电路元件104和导电图案108电连接;引线101,其和导电图案108电连接。另外,混合集成电路装置100的整体利用密封树脂102密封,形成于绝缘层107表面的导电图案108除去电连接的位置外的区域利用包覆树脂109包覆。
下面说明上述的混合集成电路装置的制造方法。首先,在由金属构成的电路衬底106的表面形成绝缘层107。其次,进行导电图案108的构图,构成规定的电路。然后,形成包覆树脂109,覆盖除去固定电路元件104的区域外的导电图案108。然后,经由电路元件104的固定、及密封树脂102的形成等工序完成上述的混合集成电路装置100。
专利文献1:特开平6-177295号公报(第4页、第1图)
但是,在上述这样的混合集成电路装置的制造方法中,利用刻蚀工序部分地除去包覆树脂109,露出导电图案108。具体地说,在涂敷包覆树脂109,使其全面地包覆导电图案108后,利用刻蚀工序选择地除去包覆树脂。但是,在该方法中,考虑刻蚀工序的精度,需要采用设置边界余量的设计,这阻碍了装置整体的小型化。另外,为部分地除去包覆树脂109而进行的刻蚀工序本身使制造成本提高。
发明内容
本发明是鉴于上述问题点而开发的,本发明的主要目的在于,提供一种电路装置的制造方法,可容易且高精度地使导电图案从包覆树脂露出。
本发明的电路装置的制造方法包括:在电路衬底表面形成形成有沿厚度方向突出的突出部的导电图案的工序;在所述电路衬底的表面形成包覆树脂,使其包覆所述导电图案的工序;通过从表面蚀刻所述包覆树脂,使所述突出部从所述包覆树脂露出的工序。
另外,在本发明的电路装置的制造方法中,将电路元件与所述突出部电连接。
在本发明的电路装置的制造方法中,一样地从表面除去所述包覆树脂,使所述突出部露出。
在本发明的电路装置的制造方法中,进行所述蚀刻直至部分露出所述突出部的侧面。
在本发明的电路装置的制造方法中,所述电路衬底是由金属构成的衬底,在覆盖所述电路衬底的表面形成的绝缘层表面形成所述导电图案。
根据本发明的电路装置的制造方法,可不使用曝光掩模,而高精度地使导电图案部分地从包覆树脂露出。具体地说,在利用包覆树脂包覆形成比其它区域突出的突出部的导电图案后,可通过从表面同样除去包覆树脂,使突出部露出。因此,由于不象现有例那样进行刻蚀工序即可进行导电图案的部分露出,故可进行排除由刻蚀工序产生的误差的图案的设计。因此,可实现电路装置整体的小型化。另外,由于排除了刻蚀工序,故可提供降低了制造成本的电路装置的制造方法。
附图说明
图1是本发明的电路装置的立体图(A)、剖面图(B)、剖面图(C);
图2(A)-(E)是说明本发明的电路装置的制造方法的剖面图;
图3(A)-(F)是说明本发明的电路装置的制造方法的剖面图;
图4是说明本发明的电路装置的剖面图(A)、剖面图(B)、立体图(C);
图5(A)、(B)、(C)是说明本发明的电路装置的剖面图;
图6是说明本发明的电路装置的制造方法的剖面图;
图7是现有电路装置的立体图(A)、剖面图(B)。
具体实施方式
参照图1说明作为本发明的电路装置之一例的混合集成电路装置10的结构。图1(A)是混合集成电路装置10的立体图,图1(B)是图1(A)的X-X’线剖面的剖面图。图1(C)是在导电图案18上形成突出部25的区域的放大剖面图。
本形态的混合集成电路装置10具有在表面形成绝缘层17的电路衬底16和在该绝缘层17表面构图的导电图案18。另外,除电连接区域外的部分的导电图案18利用包覆树脂26包覆。另外,和导电图案18电连接的电路元件14利用密封树脂12密封。下面将详细说明这样构成的混合集成电路装置10。
电路衬底16从散热的方面来看,最好是由金属或陶瓷等构成的衬底。但是,也可以是挠性板或树脂构成的印刷线路板等,只要是至少衬底表面被绝缘处理的衬底即可。另外,作为电路衬底16的材料,作为金属可采用Al、Cu或Fe等、作为陶瓷可采用Al2O3、AlN。除此之外,也可以采用机械强度及散热性优良的材料作为电路衬底16的材料。另外,在采用Al作为电路衬底16的材料时,也可以在电路衬底16的表面形成氧化膜。
在此,参照图1(B),为使从载置于电路衬底1 6表面的电路元件14产生的热顺畅地排出到外部,将电路衬底16的背面从密封树脂12露出到外部。另外,为提高装置整体的耐湿性,也可以利用密封树脂12密封也包括电路衬底16背面的整体。
电路元件14固定于导电图案18上,由电路元件14和导电图案18构成规定的电路。电路元件14采用晶体管或二极管等有源元件、或电容及电阻等无源元件。另外,功率类半导体元件等发热量大的元件也可以介由由金属构成的散热片固定在电路衬底16上。在此,利用面朝上接合法安装的有源元件等介由金属细线15和导电图案18电连接。
作为具体例,上述的电路元件14可列举LSI芯片、电容、电阻等。
另外,在半导体元件14A的背面和接地电位连接时,半导体元件14A的背面利用焊料或导电膏等固定。在半导体元件14A的背面浮置时,使用绝缘性粘接剂固定半导体元件14A的背面。另外,在半导体元件14A利用面朝下接合法安装时,介由由焊锡等构成的补片电极安装。
另外,上述电路元件14可采用控制大电流的功率类晶体管,例如功率管理操作***、GTBT(栅控双极型晶体管)、IGBT(绝缘栅双极型晶体管)、半导体开关元件等。另外,也可以使用功率类IC。近年来,由于芯片的尺寸小且薄型化,具有高性能,故与以前相比,产生大量的热。例如,控制计算机的CPU等就是如此。
导电图案18由铜等金属构成,和电路衬底16绝缘形成。在导出引线11的边形成由导电图案18构成的焊盘。引线11在此是从一个侧边导出多条,但也可以从多个侧边导出引线11。另外,也可以形成多层导电图案18。此时,在最上层的导电图案18上形成突出部25。
突出部25是比导电图案18的其它区域更向上方突出的部分,其上面从包覆树脂26露出。突出部25的上面与电路元件14或引线11电连接。突出部25突出的高度例如为数十μm程度,可根据需要增减。
绝缘层17在电路衬底16的表面整个区域上形成,具有绝缘导电图案18和电路衬底16的作用。另外,绝缘层17是在树脂中高填充氧化铝等无机填充物形成的,由导热性优良的材料构成。导电图案18的下端和电路衬底16的表面的距离(绝缘层17的最小厚度)根据耐压而改变其厚度,但优选50μm程度或50μm以上。另外,在电路衬底16由绝缘性材料构成时,可省去该绝缘层17,构成混合集成电路装置10。
引线11固定在设于电路衬底16周边部的焊盘上,具有例如与外部进行输入、输出的功能。在此,在一边上设有多个引线11。但引线11和焊盘的粘接经由焊锡(焊料)等导电性粘接剂进行。
密封树脂12通过使用热硬性树脂的传递膜模制或使用热塑性树脂的注入膜模制形成。在此,为密封电路衬底16及形成于其表面的电路,形成密封树脂12,电路衬底16的背面从密封树脂12露出。另外,除模制进行的密封之外的密封方法也可以适用于本形态的混合集成电路装置,例如,可使用利用树脂的罐封进行的密封、利用壳体件进行的密封等密封方法。
包覆树脂26在电路衬底16的表面形成,其使突出部25的上面露出而覆盖导电图案18。通过设置该包覆树脂26,可抑制制造工序的中途阶段附着的导电性粉尘使导电图案18相互短路。另外,在制造工序中途或使用状态下,可防止损伤导电图案18。
参照图1(B),小片焊盘13A、接合焊盘13B及焊盘13C是由从包覆树脂26部分露出的突出部25构成的部位。在小片焊盘13A上介由焊料19固定电路元件14。在接合焊盘13B上引线接合金属细线15,其是和电路元件14电连接的焊盘。焊盘13C是介由焊料固定引线11的焊盘,在电路衬底16的周边部排列形成有多个。
参照图1(C),突出部25的上面从包覆树脂26露出,但包括与上面连续的侧面也可以从包覆树脂露出。通过该结构,即使在除去包覆树脂26的蚀刻时有产生偏差的情况下,也可以使突出部25的上面可靠地从包覆树脂26露出。另外,在考虑在露出的突出部25上介由焊锡等焊料固定电路元件14的情况时,可在也含有侧面部的突出部26上粘附焊料,因此,可通过焊料提高连接强度。形成突出部25的部分的导电图案18对应突出部25突出的量增厚。因此,由于突出部25作为散热片起作用,故可提高散热效果。
另外,也可以在电路元件14的下方延伸导电图案18。此时,电路元件14和在其下方延伸的导电图案18利用包覆导电图案18的包覆树脂26绝缘。通过这样的结构,可在电路元件14的下方形成构成电路的配线,可提高装置整体的配线密度。
其次,参照图2及其后的附图,说明本实施例的电路装置的制造方法。
第一工序:在本工序中,进行具有突出部25的导电图案18的形成。首先,参照图2(A)及图2(B),在表面形成有绝缘层的电路衬底16上粘贴导电箔20。然后,在导电箔20的表面构图抗蚀剂21。导电箔20可采用以铜为主材料的材料、以Fe-Ni或Al为主材料的材料。导电箔20的厚度根据形成的导电图案18的厚度不同而不同。抗蚀剂21覆盖对应形成突出部25的预定区域的导电箔20的表面。
参照图2(C),其次,以抗蚀剂21为蚀刻掩模,进行湿式蚀刻,进行不形成抗蚀剂21的主面的蚀刻。利用该蚀刻蚀刻未由抗蚀剂21包覆的区域的导电箔20表面,形成凹部23。通过本工序,由抗蚀剂21覆盖的部分构成凸状突出的突出部25。在本工序结束后,剥离抗蚀剂21。
参照图2(D)及图2(E),然后,进行粘接于电路衬底16的导电箔20的构图。具体地说,在形成符合预定形成的导电图案18的形状的抗蚀剂21后,进行湿式蚀刻来进行构图。在此,包覆含有突出部25的导电图案18的抗蚀剂21,也覆盖突出部25的周边部。这是由于考虑了构图抗蚀剂21时的掩模偏差。这样,考虑抗蚀剂21的构图而更多地覆盖突出部25,可可靠地利用蚀刻进行导电箔20的分离。即,在本实施例中,进行导电图案18的构图,使其在突出部25的周边部形成边缘部18D。
如上所述,边缘部18D是使形成突出部25的区域溢出而形成的部位。因此,平面地包围突出部25而形成边缘部18D。换句话说,通过使抗蚀剂21比突出部25稍宽地形成而形成边缘部18D。这样,通过较宽地形成抗蚀剂21,进行将形成突出部25的导电图案18平面溢出的包覆,可进行稳定的蚀刻。即,由于湿式蚀刻是各向同性的,故导电图案18进行侧面蚀刻,构图后的导电图案18的侧面形成锥状。因此,通过这样较宽地进行蚀刻,可防止侧面蚀刻侵蚀导电图案18。
其次,参照图3说明形成导电图案18的另一方法。该图所示的构图方法基本上和参照图2说明的上述方法相同,不同点在于,在导电图案1 8的表面及背面两侧设置突出部25。下面以该不同点为中心进行说明。另外,在下面的说明中,将向上方突出,从包覆树脂露出的突出部称为突出部25A。将向下方突出,埋入绝缘层17中的突出部称为突出部25B。
参照图3(A),首先,形成在背面形成的突出部25B。具体地说,在对应预定形成的突出部25B的区域形成抗蚀剂21进行蚀刻,形成突出部25B。
参照图3(B),将导电箔20附着在绝缘层的表面上,使突出部25B埋入绝缘层17。利用蚀刻形成的突出部25B的侧面构成弯曲形状。因此,可抑制在形成突出部25B的位置产生空隙。
其次,参照图3(C)及图3(D),为形成在纸面上向上方突出的突出部25A,而进行抗蚀剂21的形成,进行蚀刻。由此,形成突出部25A。在此,突出部25A和突出部25B在相同的位置形成,但也可以在分别不同的位置形成。
其次,参照图3(E)及图3(F),介由重新构图而形成的抗蚀剂21进行蚀刻,形成导电图案18。
第二工序:在本工序中,利用包覆树脂包覆除突出部25之外的区域的导电图案18。具体地说,本工序中,形成包覆树脂26,使其全面地覆盖含有突出部25的导电图案18,然后,从表面全面地蚀刻包覆树脂26。通过本工序,设于导电图案18上的突出部25从包覆树脂露出。
首先,参照图4(A),在电路衬底16的表面形成包覆树脂26,使其全面地覆盖含有突出部25表面的导电图案18。包覆树脂26的材料可采用热硬性或热可塑性树脂两种。另外,包覆树脂26的形成方法有层积片状树脂片的方法。另外,在电路衬底16的表面涂敷液状或半固形状的树脂,也可以形成包覆树脂26。包覆树脂26的材料考虑之后的蚀刻工序,优选不添加填充物的树脂。另外,即使在向包覆树脂26内混入填充物时,也可以使混入的填充物的量比绝缘层17少。当混入大量的填充物时,有可能阻碍蚀刻的工序。另外,为均等地进行之后的蚀刻,优选使包覆树脂26的表面平坦化。
其次,参照图4(B)通过从表面蚀刻包覆树脂26,使突出部25的上面从包覆树脂26露出。在本工序中,不使用蚀刻掩模,均匀地蚀刻包覆树脂26的表面整个区域。因此,伴随蚀刻的进行,突出部25的上面从包覆树脂26露出。在本工序中,考虑蚀刻偏差,有时也进行蚀刻直至突出部25的侧面露出。具体地说,在以使突出部25的上面露出的程度进行包覆树脂26的蚀刻时,由于蚀刻的偏差,突出部25的上面有可能不会露出。因此,在本实施例中,通过进行包覆树脂26的蚀刻,直至突出部25的侧面部露出,使突出部25的上面可靠地露出。
参照图4(C)的立体图说明通过本工序进行突出部25的露出后的状态。该图中,被包覆树脂26包覆的部分的导电图案18由虚线表示。
参照同图,利用在表面露出的突出部25形成多个电连接区域,在本实施例中,将它们总称为焊盘。沿电路衬底16的一侧边形成有多个焊盘13C。这些焊盘13C是固定作为外部端子的引线的部位。小片焊盘13A是固定半导体元件等电路元件14的焊盘,其具有和预定载置的电路元件14相同程度的平面大小。另外,接合焊盘13B是为使用金属细线等和电路元件14电连接,而露出的焊盘。
第三工序:在本工序中进行电路元件的固定等。参照图5(A),首先,介由焊锡或导电膏等将电路元件14固定在导电图案18上。在此,可在一张电路衬底16上形成多个构成一个混合集成电路装置的单元24,并一并地进行小片接合及引线接合。在此,通过面朝上接合法安装有源元件,但也可以根据需要通过面朝下接合法进行。
参照图5(B)详细说明介由焊料19进行电路元件14的固定的情况。如上所述,在本实施例中,突出部25的上面及侧面也可以从包覆树脂26露出。而且,在这种情况下,覆盖突出部25的上面及侧面附着焊料19。这样,通过形成焊料19,可将焊料19的侧面构成无蜂腰状的圆滑的曲面。通过这种形状的焊料19,可提高对热应力等外力的可靠性。
参照图5(C),介由金属细线15进行电路元件14和导电图案18的电连接。在本实施例中,除去电连接位置外的导电图案18的表面利用包覆树脂26包覆。因此,即使在由本工序产生导电性粉尘的情况下,也可以防止该粉尘附着所造成的导电图案18相互的短路。
在上述工序结束后,进行各单元24的分离。各单元的分离可通过使用冲压机的冲切、切割等进行。然后,将引线11固定在各单元的电路衬底1 6上。
参照图6,进行各电路衬底16的树脂密封。在此,通过使用热硬性树脂的传递模模制进行密封。即,在由上模型30A及下模型30B构成的模型30中收纳电路衬底16,然后,通过使两模型相互咬合,进行引线11的固定。然后,在向模腔31内封入树脂后,进行树脂密封的工序。利用以上的工序制造图1所示的混合集成电路装置。
Claims (9)
1. 一种电路装置的制造方法,其特征在于,包括:在用于安装电路元件的电路衬底表面,形成一体地形成有沿厚度方向局部突出的突出部的导电图案的工序;在所述电路衬底的表面形成包覆树脂,使其包覆所述导电图案的工序;通过从表面蚀刻所述包覆树脂,使所述突出部的上面及侧面的一部分从所述包覆树脂露出的工序;将电路元件经由与所述突出部的上面以及侧面接触的焊锡电连接的工序。
2. 如权利要求1所述的电路装置的制造方法,其特征在于,通过均匀地从表面除去所述包覆树脂,使所述突出部露出。
3. 如权利要求1所述的电路装置的制造方法,其特征在于,所述电路衬底是由金属构成的衬底,在覆盖所述电路衬底的表面形成的绝缘层表面形成所述导电图案。
4. 如权利要求1所述的电路装置的制造方法,其特征在于,所述焊料的侧面是无蜂腰状的圆滑的曲面。
5. 如权利要求1所述的电路装置的制造方法,其特征在于,还包括通过密封树脂至少覆盖所述电路衬底的上表面的工序,以密封所述电路元件。
6. 一种电路装置,其特征在于,包括:用于安装电路元件的电路衬底;形成于所述电路衬底的上表面,且一体地设有局部沿厚度方向突出的突出部的导电图案;以露出所述突出部的上面及侧面的一部分的方式覆盖所述导电图案的包覆树脂;经由与所述突出部的上面及侧面的一部分相接触的焊料,安装于所述突出部的电路元件。
7. 如权利要求6所述的电路装置,其特征在于,还包括至少覆盖所述电路衬底的上表面的密封树脂,以密封所述电路元件。
8. 如权利要求6所述的电路装置,其特征在于,所述焊料的侧面是无蜂腰状的圆滑的曲面。
9. 如权利要求6所述的电路装置,其特征在于,所述电路衬底是由金属构成的衬底,在覆盖所述电路衬底的表面而形成的绝缘层表面形成所述导电图案。
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JP2004162655A JP2005347356A (ja) | 2004-05-31 | 2004-05-31 | 回路装置の製造方法 |
JP162655/04 | 2004-05-31 |
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CN1705085A CN1705085A (zh) | 2005-12-07 |
CN100413029C true CN100413029C (zh) | 2008-08-20 |
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US (1) | US20050263482A1 (zh) |
JP (1) | JP2005347356A (zh) |
KR (1) | KR100738134B1 (zh) |
CN (1) | CN100413029C (zh) |
TW (1) | TWI317997B (zh) |
Cited By (1)
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CN103392384A (zh) * | 2010-12-23 | 2013-11-13 | 法雷奥电机控制***公司 | 具有绝缘金属基板的印刷电路板 |
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JP2011129873A (ja) | 2009-11-17 | 2011-06-30 | Sony Corp | 固体撮像装置およびその製造方法、電子機器 |
EP2827364B1 (en) * | 2012-03-15 | 2019-11-27 | Fuji Electric Co., Ltd. | Semiconductor device |
JP5987719B2 (ja) * | 2013-02-13 | 2016-09-07 | 三菱電機株式会社 | 半導体装置 |
CN106686932B (zh) | 2015-11-05 | 2019-12-13 | 精能医学股份有限公司 | 植入式电子装置的防水结构 |
CN111601453B (zh) * | 2020-05-30 | 2024-03-15 | 广东航能电路科技有限公司 | 一种新型柔性电路板 |
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- 2005-05-24 KR KR1020050043631A patent/KR100738134B1/ko not_active IP Right Cessation
- 2005-05-27 US US11/139,142 patent/US20050263482A1/en not_active Abandoned
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KR20060049442A (ko) | 2006-05-19 |
US20050263482A1 (en) | 2005-12-01 |
KR100738134B1 (ko) | 2007-07-10 |
JP2005347356A (ja) | 2005-12-15 |
CN1705085A (zh) | 2005-12-07 |
TWI317997B (en) | 2009-12-01 |
TW200539408A (en) | 2005-12-01 |
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