CN100412661C - Display device - Google Patents
Display device Download PDFInfo
- Publication number
- CN100412661C CN100412661C CNB2006100912366A CN200610091236A CN100412661C CN 100412661 C CN100412661 C CN 100412661C CN B2006100912366 A CNB2006100912366 A CN B2006100912366A CN 200610091236 A CN200610091236 A CN 200610091236A CN 100412661 C CN100412661 C CN 100412661C
- Authority
- CN
- China
- Prior art keywords
- film
- atom
- alloy
- resistivity
- display device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A display device in which interconnection-electrode comprising a Cu alloy film having a lower electrical resistivity than Al alloy and a transparent conductive film are directly connected not by way of a refractory metal thin film, wherein the Cu alloy film contains Zn and/or Mg in a total amount from 0.1 to 3.0 at %, or Ni and/or Mn in a total amount from 0.1 to 5 at %, thereby enabling the direct connection at low resistivity between the Cu alloy film and the transparent electrode without using a barrier metal, and giving high display quality in a case of application, for example, to a liquid crystal display.
Description
Technical field
The present invention relates to a kind of thin film display device, more particularly, the present invention relates to a kind of novel display device that comprises the low-resistivity interconnecting parts (as composed component) of following structure, transparent and electrically conductive film directly is connected with the Cu alloy film in this structure, this structure example is as being used in the active and passive matrix flat-panel monitor (FPD), for example LCD, reflective film, optical element etc.
Background technology
For FPD, comprise LCD, more and more need the interconnection material of low-resistivity in recent years.Especially, in LCD, demand reduces the gate line of the thin film transistor (TFT) (TFT) be used to drive pixel and the resistivity of signal wire (power supply and drain line) consumingly, has for example used heat-resisting Al alloys such as Al-Nd at present.
But along with the appearance of the large scale display board of 40 or the bigger model that for example are used for liquid crystal display TV equipment, from the angle of the signal delay problem of gate line and signal wire, Ag and Cu have attracted people to note as the resistivity material lower than Al alloy.But from the angle of liquid crystal display applications, there are several problems in Ag and Cu.In the situation of pure Ag, for example adhesion of existence and glass substrate and SiN dielectric film, the performance by wet etching preparation interconnection, Ag element interior poly-etc.And, the example that uses pure Cu metal or Cu alloy is for example disclosed in JP-A 2003-58079 and 2003-297584 communique, although they have those problems as above-mentioned Ag, they have applied on some high-end monitors.
Summary of the invention
Giving one of problem that Cu metal and Cu alloy point out is exactly their easy oxidations.In the situation of present normally used Al alloy interconnect, when being connected with the transparency electrode of for example being made by indium tin oxide target (ITO), for example refractory metal such as Mo, Cr or its alloy is connected described gate interconnection and source/drain interconnects the two with being called barrier metal between the two in the interconnection of gate interconnection and source/drain.This is because when ITO directly is connected with Al, owing to form the Al oxidation film on the interface between Al and the ITO, it is impossible that increase of electrical connection resistivity or electrical connection become.
Such problem also takes place in the situation of using pure Cu or Cu alloy film.This is because the easy oxidation in atmosphere of the surface of Cu film forms the Cu oxidation film, also oxidation easily in the oxygen plasma cineration step that Cu uses on the surface when catching resist.And, sputter forms the situation that the ITO film is made transparency electrode on the Cu film surface of the electrical connection that is used for Cu film and ITO film etc., the oxygen that adds during owing to the oxygen that derives from target material when forming the ITO film or owing to film forming forms thin-oxide film as the ITO/Cu interface on Cu film surface.This oxidation film makes Cu interconnection increase with the resistivity that is connected between the transparency electrode, thereby makes for example display quality variation such as gradual change of LCD.
The potential barrier metals such as for example Mo that use between Al alloy film and transparency electrode at present have the effect that prevents on Al alloy film surface oxidation and advantageously keep the resistivity between Al alloy film and the transparency electrode, and in the situation of using Cu or Cu alloy rather than Al alloy, it also is effective using described barrier metal.But, in this existing method, because the barrier metal that need be formed for the forming barrier metal layer sputter film formation chamber of Mo etc. for example, this has increased installation cost, because the productive temp time (tact time) when forming film increases, so reduced throughput rate and increased cost.Finished the present invention based on above-mentioned situation, the present invention aims to provide a kind of display device, it uses the resistivity Cu alloy film lower than Al alloy to be used for being connected with ELD, and do not use barrier metal layer just can directly to connect, and when for example being applied to LCD, can guarantee high display quality with low-resistivity with respect to transparency electrode.
In order to address this problem, an aspect of of the present present invention is intended to a kind ofly not adopt refractory metal film and the direct-connected display device of electrode of will interconnect-comprise Cu alloy film and nesa coating, wherein to contain Zn that total amount is 0.1 atom %～3.0 atom % and/or Mg or total amount be Ni and/or the Mn of 0.1 atom %～0.5 atom % to the Cu alloy film, and wherein except above-mentioned element, the Cu alloy film also contains Fe that total amount is 0.02 atom %～1.0 atom % and/or the P of Co and 0.005 atom %～0.5 atom %.
In the display device of the present invention aspect this, indium tin oxide target (ITO) or indium zinc oxide (IZO) are preferably as nesa coating, it is exceedingly useful as thin slice connection electrode (tab connection electrode) that nesa coating is laminated to those films that form on the Cu alloy film that contains above-mentioned designed element, for example as having the low LCD that is electrically connected resistivity and high display quality.
This aspect of the present invention can provide high performance display device at low cost, can access the Cu alloy film and contact with for example the direct of the low contact resistance between the nesa coating such as ITO or IZO, and can omit the use barrier metal layer.
According to above-mentioned aspect of the present invention, in the situation that nesa coating and Cu metal film are in contact with one another, because at least a element that is selected among Zn, Mg, Ni and the Mn is included in the Cu metal film slightly, so can be suppressed at the Cu oxidation film growth that forms on the Cu metallic film surface, thereby contact resistance can be controlled to low stable status, therefore, in LCD etc., display quality is maintained the high-caliber while, reduce number of steps and processing cost significantly.
Description of drawings
Describe embodiment of the present invention in detail with reference to following accompanying drawing.Wherein:
Fig. 1 is the schematic cross section that expression is installed in the example of the liquid crystal display device structure on the liquid crystal indicator;
Fig. 2 is the amplification schematic cross section of example of the cross-sectional structure of expression thin film transistor (TFT);
Fig. 3 is the amplification schematic cross section that the step that forms thin-film transistor structure continuously is described;
Fig. 4 is the amplification schematic cross section that the step that forms thin-film transistor structure continuously is described;
Fig. 5 is the amplification schematic cross section that the step that forms thin-film transistor structure continuously is described;
Fig. 6 is the amplification schematic cross section that the step that forms thin-film transistor structure continuously is described;
Fig. 7 is the amplification schematic cross section that the step that forms thin-film transistor structure continuously is described;
Fig. 8 is the amplification schematic cross section that the step that forms thin-film transistor structure continuously is described;
Fig. 9 is the amplification schematic cross section that the step that forms thin-film transistor structure continuously is described;
Figure 10 is the figure that is illustrated in the relation between the heat treatment temperature and resistivity in several samples that embodiment uses; With
Figure 11 is the figure that is illustrated in the relation between the heat treatment temperature and void level in several samples that embodiment uses.
Embodiment
With reference to accompanying drawing, example as active matrix type display, describe the preferred embodiment according to display device of the present invention particularly, but the present invention is in no way limited to the scheme explained, it can be implemented in meeting the OK range of describing later of the invention described above main idea.
Fig. 1 is mounted in the signal of the liquid crystal display device structure on the liquid crystal indicator that the present invention uses and amplifies cross-sectional view.
LCD shown in Figure 1 has thin film transistor (TFT) (TFT) array substrate 1, the relative substrate 2 relative with tft array substrate 1 and is arranged in tft array substrate 1 and the liquid crystal layer that serves as optical modulation layer 3 between the substrate 2 relatively.Tft array substrate 1 comprises thin film transistor (TFT) (TFT) 4, nesa coating (pixel electrode) 5 that is arranged on the insulating glass substrate 1a and the interconnecting parts 6 that comprises sweep trace and signal wire.
Relatively substrate 2 is included in the common electrode 7 that forms on the whole surface on tft array substrate 1 this side, is arranged in the locational color filter 8 relative with nesa coating 5 and is arranged in the locational photomask 9 relative with thin film transistor (TFT) (TFT) 4 or the interconnecting parts on tft array substrate 16.
And polarization plates 10 (a) and 10 (b) are arranged on the outside surface of the insulating substrate that constitutes tft array substrate 1 and relative substrate 2, are arranged on the relative substrate 2 being included in the oriented film 11 that liquid crystal molecule in the liquid crystal layer 3 is directed to predetermined direction.
In the LCD of this structure, with the orientation direction of the liquid crystal molecule in the electric field controls liquid crystal layer 3 that forms between relative substrate 2 and the nesa coating (pixel electrode) 5, by the photocontrol of modulation by the liquid crystal layer 3 between tft array substrate 1 and the relative substrate 2 through the amount of the transmitted light of relative substrate 2 with display image.
And, be with 12 usefulness driving circuits 13 and control circuit 14 drive TFT arrays by the TAB that guides to the tft array outside.
In the accompanying drawings, spacer 15, encapsulant 16, diaphragm 17, diffuser plate 18, prismatic lens 19, optical plate 20, reflecting plate 21, back of the body lamp 22, maintenance frame 23 and printed substrate 24 have been expressed respectively.
Fig. 2 is that cross-sectional view is amplified in the signal that expression is applied to the example of structure of the TFT part on the array substrate that the present invention uses.As shown in Figure 2, form sweep trace 25 with the Cu metal film on the glass substrate 1a, a part of sweep trace 25 serves as the gate electrode 26 of carrying out thin film transistor switch control.And, form signal wire so that with the mode transverse scan line 25 of gate insulating film 27, a part of signal wire serves as the source electrode 28 of thin film transistor (TFT) with the Cu metal film.This generally is called bottom gate polar form (bottom gate type).
In the pixel region on gate insulating film 27, nesa coating 5 is to use for example at In
2O
3In mix the SnO of about 10 quality % the ITO film form.Drain electrode 29 with the film formed thin film transistor (TFT) of Cu alloy is electrically connected with nesa coating 5 by directly contacting.
When through sweep trace 25 when gate electrode 26 applies gate voltage for tft array substrate 1, thin film transistor (TFT) is opened, the driving voltage that is supplied to signal wire in advance 29 is supplied to transparent conductor 25 from source electrode 28 through draining.Then, when the driving voltage with certain level is supplied to nesa coating 5, produce electric potential difference, make the liquid crystal molecule orientation that is included in the liquid crystal layer 3 carry out optical modulation (with reference to Fig. 1) with respect to counter electrode 2.
The main points of the preparation process of tft array substrate are described with reference to the example of Fig. 3～Fig. 9 then.The thin film transistor (TFT) example that forms as on-off element in the present embodiment has gone out to use the amorphous silicon of hydrogenation to make the amorphous silicon TFT of semiconductor layer.At first, form the thick thin Cu film of about 200nm earlier, make thin Cu film form pattern to form gate electrode 26 and sweep trace 25 (Fig. 3) through wet etching by sputter on glass substrate 1a.Then, as shown in Figure 4, usefulness plasma CVD method etc. forms the thick gate insulating film (silicon nitride film: SiN of about 300nm under about 350 ℃ substrate temperature
x).Under about 300 ℃ substrate temperature, form the n of the thick doping P of the thick amorphous hydrogenated silicon film (a-SiH) of about 150nm and about 50 nm thereon continuously
+-amorphous hydrogenated silicon film (n
+A-SiH) (Fig. 5).
Then, as shown in Figure 6, make amorphous hydrogenated silicon film (a-SiH) and n through dry ecthing
+-amorphous hydrogenated silicon film (n
+A-SiH) form pattern.Then, as shown in Figure 7, laminated and thick Mo layer (bottom) and the thick Cu metal level of about 200nm of the about 50nm of formation makes the Cu/Mo laminate film form pattern has been integrated signal wire with formation source electrode and the drain electrode that contacts with the ITO nesa coating through wet etching.And, use source electrode and drain electrode to make mask and remove n through dry ecthing
+Amorphous silicon film (n
+A-SiH).
Then, as shown in Figure 8, in plasma CVD equipment, form silicon nitride film (SiNx) to the thickness of about 300nm with the formation diaphragm.This film is usually in the film formation temperature, and for example about 250 ℃ form down.Then, make silicon nitride film (SiNx) formation pattern and make contact hole be formed up to silicon nitride film (SiNx) through dry ecthing.And, remove step through the polymkeric substance of oxygen plasma ashing, after use for example non-amine type striping (stripping) solution is implemented the striping processing to photoresist, remove the Cu oxidation film that forms by the oxygen plasma ashing with the hydrofluorite of dilution.
At last, as shown in Figure 9, at room temperature form the thick ITO nesa coating of for example about 150nm, form pattern to form pixel electrode (ITO nesa coating) 5, finished the tft array substrate through wet etching through sputter.
In the tft array substrate that forms according to described preparation process, ITO nesa coating (pixel electrode) 5 and directly be in contact with one another with the film formed drain electrode of Cu metal.And ITO nesa coating 5 also directly contacts with the TAB part of the sweep trace that is connected with gate electrode.Display device of the present invention above-mentioned steps production, outstanding feature of the present invention is to mix the element-specific of the selection of scheduled volume separately in Cu, as the Cu alloy film that is used in the interconnecting parts, this characteristics are described in the back.As the element that is included in the Cu alloy film, select Zn and/or Mg, or Ni and/or Mn.But select above-mentioned element as solid solution in the Cu metal but not solid solution in the element of Cu oxidation film.When solid wherein is dissolved with the Cu alloy of above-mentioned element when oxidized, because not solid solution of element (Zn, Ni, Mn and Mg) is in the Cu oxidation film, so clean out above-mentioned element, enrichment under the interface of the Cu oxidation film that oxidation forms, this enrichment layer suppresses the further growth of Cu oxidation film.Therefore, form in the step in the oxygen ashing or at the laminate film with the ITO nesa coating, the growth of Cu oxidation film also minimizes.Especially, in the laminated and film of ITO formed, Cu alloy film and nesa coating remained on the favo(u)red state that electrically contacts.
In order for example to obtain 10 by forming this enrichment layer
-5～10
-4Ω cm
2The lower contact resistance of the order of magnitude, preferably comprise 0.1 atom % or higher altogether, more preferably 0.2 atom % or the higher element that is selected from one or more kinds among Zn, Ni, Mn and the Mg, like this, do not insert barrier metal, sufficient conductance can be guaranteed by direct connection, for example display performances such as the gray scale demonstration degradation of liquid crystal can be prevented.As a result, form step, shorten the productive temp time, can improve throughput rate significantly by omitting potential barrier metal film.
When also considering by thermal treatment reduction resistivity, in the situation of Zn and/or Mg, the total amount of mixing the element of Cu alloy film is reduced to 3.0 atom % or littler, more preferably 2.0 atom % or littler, in the situation of Ni and/or Mn, total amount is reduced to 0.5 atom % or littler, more preferably 0.4 atom % or littler.
Because the drawing stress that the thermal treatment in the subsequent step produces, the Cu metal film produces the defectives such as grain-boundary crack that for example are called the space sometimes.But, mixing in the situation of one or more kinds among above-mentioned Zn, Ni, Mn and the Mg with Fe and P or Co and P, when thermal treatment, they slightly are deposited to crystal boundary as FeP or CoP compound, provide to strengthen crystal boundary to suppress the effect that the space takes place.Therefore, under surpassing 300 ℃ high temperature in the situation of experience thermo-lag, preferred adding is the Fe of 0.02 atom %～1.0 atom % and/or the P of Co and 0.005 atom %～0.5 atom % altogether after film forms.
As nesa coating, although, can certainly use indium zinc oxide (IZO) as above-mentioned frequent use indium tin oxide target (ITO).
Another preferred embodiment of display device is that wherein nesa coating is layered on the Cu alloy, and as TAB (modulation sheet) connection electrode.
[embodiment]
Describe formation of the present invention, function and effect particularly with reference to embodiment, but the present invention is limited by the following example never.
Embodiment
(#1737 is produced by Corning Co., is used to estimate resistivity and stable on heating size: 50.8 mm diameters * 0.7 mm thickness at glass substrate; Be used to estimate the size of contact resistivity: 101.6mm diameter * 0.7mm thickness), use dc magnetron sputtering method (pressure of foundation (basepressure): 0.27 * 10
-3Pa or lower; Argon pressure: 0.27Pa; Argon gas flow velocity: 30sccm; Sputtering power: DC200W; Interelectrode distance: 50.4mm; Substrate temperature: room temperature), use compound sputtering target and sputtering equipment (HSM-552, produce by Shimazu Seisakusho) form the film of sample separately with the thickness of 300nm, wherein respectively with predetermined number with the fragment (size: 5mm * 5 mm * 1mm is thick) of the alloying element shown in the following table 1～13 be arranged in the sputtering target made by pure Cu (size: diameter 101.6mm * thickness 5mm), described sample comprises:
Pure Cu (sample No.1);
Cu-Zn alloy (sample No.2～6);
Cu-Mg alloy (sample No.7～11);
Cu-Mn alloy (sample No.12～16);
Cu-Ni alloy (sample No.17～21);
Cu-Zn-Fe-P alloy (sample No.22～26);
Cu-Mg-Fe-P alloy (sample No.27～31);
Cu-Mn-Fe-P alloy (sample No.32～36);
Cu-Ni-Fe-P alloy (sample No.37～41);
Cu-Zn-Mg alloy (sample No.42～45);
Cu-Mn-Ni alloy (sample No.46～49);
Cu-Zn-Co-P alloy (sample No.50～54);
Cu-Mg-Co-P alloy (sample No.55～59);
Cu-Mn-Co-P alloy (sample No.60～64) and
Cu-Ni-Co-P alloy (sample No.65～69).
Then, test the metal of the film that is used to estimate with ICP (inductively coupled plasma) emission spectrometry or ICP mass spectroscopy and form, estimate resistivity, contact resistivity and thermotolerance with following method.
Resistivity
In order to estimate resistivity, make with photoetching process and wet etch method that (#1737 is produced size: 50.8mm diameter * 0.7mm thickness) go up the pattern that each the thin Cu film that forms forms 100 μ m live widths and 10mm line length by Corning Co. at glass substrate.In this case, use and to comprise sulfuric acid: nitric acid: the liquid mixture of the acid mixture of acetate=50: 10: 10 is made wet etchant.Then, with vacuum heat treatment equipment (vacuum tightness: 0.27 * 10
-3Pa or littler) carries out the thermal treatment of 250 ℃ * 30 minutes or 350 ℃ * 30 minutes, before vacuum heat and afterwards, at room temperature measure the resistivity of each sample with the DC4-probe method.Resistivity with each thin Cu film of above-mentioned step measurements.Resistivity is carried out qualified/defective judgement, those samples that are lower than 5.0 μ Ω cm for the resistivity after 250 ℃ * 30 minutes the thermal treatment are judged as " qualified " (individual pen), for resistivity is that 5.0 μ Ω cm or those higher samples are judged as " defective " (cross), for the resistivity after 350 ℃ * 30 minutes the thermal treatment is that those samples of 4.0 μ Ω cm are judged as " qualified " (individual pen), and resistivity is lower than 4.0 μ Ω cm or bigger sample and is judged as " defective " (again number).
Table 1 and 2 is illustrated in the resistivity of measuring after the thermal treatment of 250 ℃ * 30 minutes or 350 ℃ * 30 minutes.Find out from showing to show, the total amount of Zn and Mg less than the situation of 3.0 atom % in or in the situation of total amount at Ni and Mn less than 0.5 atom %, satisfy the desired value (after 250 ℃ * 30 minutes the thermal treatment after the thermal treatment of 5.0 μ Ω cm or 350 ℃ * 30 minutes 4.0 μ Ω cm) of resistivity.And, be that 1.0 atom % or littler and P content are in 0.5 atom % or the littler situation in the total amount of Fe or Co, satisfy the desired value (after 250 ℃ * 30 minutes the thermal treatment after the thermal treatment of 5.0 μ Ω cm and 350 ℃ * 30 minutes 4.0 μ Ω cm) of resistivity.
Table 1
Table 2
[contact resistivity-dry-etching method]
For of the variation of testing contact resistance rate, measure the contact resistivity of the contact hole that forms with dry-etching method with engraving method.The detailed content that forms the method for contact is described below.
To each the thin Cu film that on glass substrate, forms, form the thick thin SiN film of 300nm with plasma CVD equipment.Substrate heating temperature is set at 250 ℃ or 350 ℃, comprises that the rough handling of glass substrate and the net heat processing time that CVD handles are set at 0.5 hour.Then, contact hole is carried out photoetching, use the dry ecthing of ICP type dry etcher contact hole (10 * 10 μ m square shapes: 1) be formed up to SiN.Then, through the oxygen ashing be immersed in the non-amine resist stripping solution and remove resist, with the basal surface of the hydrofluoric acid clean contact of buffering.Then, form the ITO film, thin ITO film is made Kelvin's pattern of 100 μ m live widths and 400 μ m line lengths with the dc magnetron sputtering method.In this case, the ITO etching solution that uses Nagase Chemtex Co. to produce is made wet etchant.Measure resistivity with four probe methods,, calculate the contact resistivity of per unit area based on known contact hole area and contact resistance value based on the voltage drop compound mensuration contact resistance value of the contact portion at Cu/ITO interface.
Use above-mentioned steps, preparation can be measured Kelvin's pattern of the contact resistance between each thin Cu film and the thin ITO film to measure contact resistance.For judge contact resistance qualified/defective, in 100 measuring points, get rid of the point of 5 peaked points and 5 minimum value, the average contact resistivity of 90 points is less than 5 * 10 altogether
-4Ω cm
2Those pattern evaluations be " qualified " (individual pen), showing average contact resistivity those pattern evaluations bigger than above-mentioned value is " defective " (cross).And discrete in order to estimate, in the measurement result of 100 points, contact resistivity surpasses 5 * 10
-4Ω cm
2The pattern evaluation of ratio (failure than) less than 10% be " qualified " (individual pen), this ratio be 10% or bigger pattern evaluation be " defective " (cross).Carry out under 250 ℃ or 350 ℃ that cvd film forms and thermal treatment, the evaluation result of contact resistivity that is formed with the sample of contact hole with dry method is illustrated in following table 3～5 and table 6～8.See that from table 3～8 pure Cu and Cu alloy satisfy the criterion of acceptability of average contact resistivity.But, when comparing with pure Cu, be selected among Zn, Ni, Mn and the Mg one or more and plant the total content of elements to be that 0.1 atom % or bigger Cu-(Zn, Ni, Mn, Mg) alloy film and Cu-(Zn, Ni, Mn, Mg)-(Fe, Co)-P alloy film show less contact resistivity discrete, obtain the lower contact resistance of high reliability.
[contact resistivity-wet etch process]
For of the variation of testing contact resistance rate, the contact hole that wet etch process forms is measured contact resistivity with engraving method.The detailed content that forms the method for contact hole is described below.
To each the Cu film that on glass substrate, forms, form the thick thin SiN film of 300nm with plasma CVD equipment.Substrate heating temperature is set at 250 ℃ or 350 ℃, comprises that the rough handling of glass substrate and the net heat processing time that CVD handles are set at 0.5 hour.Then, contact hole is carried out photoetching, contact hole (10 * 10 μ m square shapes: 1) be formed up to SiN with wet etching.The hydrofluorite of buffering is used for wet etching.Then, form the ITO film, will approach the ITO film with photoetching process and wet etching and make Kelvin's pattern of 100 μ m live widths and 400 μ m line lengths to estimate contact resistance value by the dc magnetron sputtering method.In this case, the ITO etching solution that uses Nagase Chemtex Co. to produce is made wet etchant.Use identical shaped pattern to measure resistivity, based on the voltage drop compound mensuration contact resistance value of the contact portion at Cu/ITO interface, based on the contact resistivity of known contact hole area and contact resistance value unit of account area with four probe methods.
Use above-mentioned steps, preparation can be measured Kelvin's pattern of the contact resistance between each thin Cu film and the thin ITO film to measure contact resistance.For judge contact resistance qualified/defective, in 100 measuring points, get rid of the point of 5 peaked points and 5 minimum value, the average contact resistivity of 90 points is less than 5 * 10 altogether
-4Ω cm
2Those pattern evaluations be " qualified " (individual pen), showing average contact resistivity those pattern evaluations bigger than above-mentioned value is " defective " (cross).And discrete in order to estimate, in the measurement result of 100 points, contact resistivity surpasses 5 * 10
-4Ω cm
2Ratio (failure than) those pattern evaluations less than 10% be " qualified " (individual pen), this ratio be 10% or those bigger pattern evaluations be " defective " (cross).
Carry out under 250 ℃ or 350 ℃ that cvd film forms and thermal treatment, the evaluation result of contact resistivity that is formed with the sample of contact hole with dry method is illustrated in following table 3～5 and table 6～8.See that from table pure Cu and Cu alloy satisfy the criterion of acceptability of average contact resistivity.But, when comparing with pure Cu, be selected among Zn, Ni, Mn and the Mg one or more and plant the total content of elements to be that 0.1 atom % or bigger Cu-(Zn, Ni, Mn, Mg) alloy film and Cu-(Zn, Ni, Mn, Mg)-(Fe, Co)-P alloy film show less contact resistivity discrete, obtain the lower contact resistance of high reliability.
[contact resistivity-contact reliability test]
After wet etching forms contact with above-mentioned same procedure, carry out the contact reliability test by positively implementing the oxygen ashing.This simulation air oxidation when Cu and Cu alloy film are stored in the atmosphere, the detailed content that forms the method that contacts is described below.
To each thin Cu film that on glass substrate, forms, implement the preparation that interconnects of photoetching and wet etching.As wet etchant, use to comprise sulfuric acid: nitric acid: the acid mixture of acetate=50: 10: 10.Then, form thin SiN film with plasma CVD equipment with the thickness of 300nm.Substrate heating temperature is set at 250 ℃ or 350 ℃, and it comprises that also the rough handling of glass substrate and the net heat processing time that CVD handles are set at 0.5 hour.
Then, contact hole is applied photoetching, SiN is carried out contact etch with wet etching.As wet etchant, use the hydrofluorite of buffering.Then, use incineration equipment in oxygen atmosphere, to carry out ashing treatment and contact the bottom surface with oxidation.Then,, form the thick ITO film of 100nm respectively, implement photoetching and wet etching then, estimate the variation of contact resistance value with the ashing time for above-mentioned sample.Use identical shaped pattern 100 points to be measured resistivity, based on the voltage drop compound mensuration contact resistance value of the contact portion at Cu/ITO interface, based on the contact resistivity of known contact hole area and contact resistance value unit of account area with four probe methods.
Use above-mentioned steps, preparation can be measured Kelvin's pattern of the contact resistance between each thin Cu film and the thin ITO film to measure contact resistance.For judge contact resistance qualified/defective, in 100 measuring points, get rid of the point of 5 peaked points and 5 minimum value, the average contact resistivity of 90 points is less than 5 * 10 altogether
-4Ω cm
2Those pattern evaluations be " qualified " (individual pen), showing average contact resistivity those pattern evaluations bigger than above-mentioned value is " defective " (cross).And discrete in order to estimate, in the measurement result of 100 points, contact resistivity surpasses 5 * 10
-4Ω cm
2Ratio (failure than) those pattern evaluations less than 10% be " qualified " (individual pen), this ratio be 10% or those bigger pattern evaluations be " defective " (cross).
Carry out cvd film and form and thermal treatment under 250 ℃ or 350 ℃, after forming contact hole with wet method, the evaluation result of the contact resistivity of 10 minutes sample of ashing treatment is illustrated in the following table 3～8.See that from table 3～8 pure Cu shows high contact resistivity and big dispersing.On the other hand, when comparing with pure Cu, the total content that is selected from one or more kinds among Zn, Ni, Mn and the Mg is that 0.1 atom % or bigger Cu-(Zn, Ni, Mn, Mg) alloy film and Cu-(Zn, Ni, Mn, Mg)-(Fe, Co)-P alloy film show lower average contact resistivity and less dispersing, and obtains favourable contact.This shows that use Cu alloy seldom produces air oxidation and improve one's methods income when preparation process.
[thermotolerance]
" the AZ P4110 " that uses Clariant Japan Co. to produce makes " AZ developer " that photoresist and same company produce and makes development of photoresist liquid and carry out photoetching (step: apply photoresist → preroast → exposure → development of photoresist → washing → drying); Use comprises sulfuric acid: nitric acid: the wet etchant of the mixed acid of acetic acid=50: 10: 10 is carried out wet etching (step: wet etching → washing → drying → photoresist is removed (stripping) → drying), and each thin Cu film that will be used for evaluation be made the bar paten of live width/distance between centers of tracks=10 μ m/10 μ m. Then, 350 ℃ of of following of each thin Cu film is implemented vacuum heat (vacuum tightnesss:0.27 * 10-3Pa or less than 0.27 * 10
-3Pa) 30 minutes, on the sample surfaces after the thermal treatment, use wet etchant to carry out photoetch to about 10nm, estimate the thermotolerance of each thin Cu film.
In the Cu film, when heat-treating, on the side of upper surface and interconnection, form concave defects (space).Then, strengthen the space that forms by thermal treatment, under optical microscope, observe the void level of analytical unit area by the surface of the Cu after the photoetch thermal treatment.Then, be 1.0 * 10 with void level
-8N/m
2Or littler those are evaluated as " excellence " (two circle), and void level is 1.0 * 10
8N/m
2Or higher and 1.0 * 10
10N/m
2Or littler those are evaluated as " well " (individual pen) ((two circle) and (individual pen) all are: " qualified "), and void level surpasses 1.0 * 10
10N/m
2Those be evaluated as " defective " (cross).
The result is illustrated in table 9 and 10.In carrying out 350 ℃ * 30 minutes the situation of vacuum heat, for pure Cu, thermotolerance is inadequate, yet Cu-(Zn, Ni, Mn, the Mg) alloy film that is selected from the total content of one or more the kind elements among Zn, Ni, Mn and the Mg has sufficient thermotolerance.And, see that Cu-(Zn, Ni, Mn, Mg)-(Fe, the Co)-P alloy film that contains Fe or Co and P has more excellent thermotolerance.
Table 9
Thermotolerance
| Sequence number | The composition of interconnect electrode (atom %) | 250 ℃ of thermal treatments in-0 5 hours | 350 ℃ of thermal treatments in-0 5 hours |
| 1 | Cu | ○ | × |
| 2 | Cu-0.05Zn | ○ | × |
| 3 | Cu-0.12Zn | ◎ | ○ |
| 4 | Cu-2.1Zn | ◎ | ○ |
| 5 | Cu-3.0Zn | ◎ | ○ |
| 6 | Cu-4.0Zn | ◎ | ○ |
| 7 | Cu-0.05Mg | ○ | × |
| 8 | Cu-0.15Mg | ◎ | ○ |
| 9 | Cu-1.3Mg | ◎ | ○ |
| 10 | Cu-3.0Mg | ◎ | ○ |
| 11 | Cu-4.7Mg | ◎ | ○ |
| 12 | Cu-0.06Mn | ○ | × |
| 13 | Cu-0.13Mn | ◎ | ○ |
| 14 | Cu-0.3Mn | ◎ | ○ |
| 15 | Cu-0.5Mn | ◎ | ○ |
| 16 | Cu-0.9Mn | ◎ | ○ |
| 17 | Cu-0.05Ni | ○ | × |
| 18 | Cu-0.13Ni | ◎ | ○ |
| 19 | Cu-0.3Ni | ◎ | ○ |
| 20 | Cu-0.5Ni | ◎ | ○ |
| 21 | Cu-0.9Ni | ◎ | ○ |
| 22 | Cu-2.1Zn-0.01Fe-0.003P | ◎ | ○ |
| 23 | Cu-2.1Zn-0.023Fe-0.005P | ◎ | ◎ |
| 24 | Cu-2.1Zn-0.1Fe-0.05P | ◎ | ◎ |
| 25 | Cu-2.1Zn-0.9Fe-0.5P | ◎ | ◎ |
| 26 | Cu-2.1Zn-1.2Fe-0.7P | ◎ | ◎ |
| 27 | Cu-2.1Mg-0.01Fe-0.003P | ◎ | ○ |
| 28 | Cu-2.1Mg-0.023Fe-0.005P | ◎ | ◎ |
| 29 | Cu-2.1Mg-0.1Fe-0.05P | ◎ | ◎ |
| 30 | Cu-2.1Mg-0.9Fe-0.4P | ◎ | ◎ |
| 31 | Cu-2.1Mg-1.2Fe-0.7P | ◎ | ◎ |
| 32 | Cu-0.5Mn-0.01Fe-0.005P | ◎ | ○ |
| 33 | Cu-0.5Mn-0.025Fe-0.01P | ◎ | ◎ |
| 34 | Cu-0.5Mn-0.1Fe-0.05P | ◎ | ◎ |
| 35 | Cu-0.5Mn-0.9Fe-0.4P | ◎ | ◎ |
| 36 | Cu-0.5Mn-1.2Fe-0.6P | ◎ | ◎ |
Table 10
Thermotolerance
| Sequence number | The composition of interconnect electrode (atom %) | 250 ℃ of thermal treatments in-0 5 hours | 350 ℃ of thermal treatments in-0 5 hours |
| 37 | Cu-0.5Ni-0.01Fe-0.005P | ◎ | ○ |
| 38 | Cu-0.5Ni-0.025Fe-0.01P | ◎ | ◎ |
| 39 | Cu-0.5Ni-0.1Fe-0.05P | ◎ | ◎ |
| 40 | Cu-0.5Ni-0.9Fe-0.4P | ◎ | ◎ |
| 41 | Cu-0.5Ni-1.2Fe-0.7P | ◎ | ◎ |
| 42 | Cu-0.03Zn-0.05Mg | ◎ | ○ |
| 43 | Cu-0.5Zn-2.3Mg | ◎ | ◎ |
| 44 | Cu-1.5Zn-1.0Mg | ◎ | ◎ |
| 45 | Cu-3.2Zn-2.3Mg | ◎ | ◎ |
| 46 | Cu-0.03Mn-0.04Ni | ○ | ◎ |
| 47 | Cu-0.1Mn-0.1Ni | ◎ | ○ |
| 48 | Cu-0.2Mn-0.2Ni | ◎ | ○ |
| 49 | Cu-0.6Mn-0.6Ni | ◎ | ○ |
| 50 | Cu-2.1Zn-0.01Co-0.005P | ◎ | ○ |
| 51 | Cu-2.1Zn-0.025Co-0.01P | ◎ | ◎ |
| 52 | Cu-2.1Zn-0.1Co-0.05P | ◎ | ◎ |
| 53 | Cu-2.1Zn-0.9Co-0.5P | ◎ | ◎ |
| 54 | Cu-2.1Zn-1.4Co-0.6P | ◎ | ◎ |
| 55 | Cu-2.1Mg-0.01Co-0.005P | ◎ | ○ |
| 56 | Cu-2.1Mg-0.025Co-0.01P | ◎ | ◎ |
| 57 | Cu-2.1Mg-0.1Co-0.05P | ◎ | ◎ |
| 58 | Cu-2.1Mg-0.9Co-0.4P | ◎ | ◎ |
| 59 | Cu-2.1Mg-1.2Co-0.7P | ◎ | ◎ |
| 60 | Cu-0.5Mn-0.01Co-0.005P | ◎ | ○ |
| 61 | Cu-0.5Mn-0.025Co-0.01P | ◎ | ◎ |
| 62 | Cu-0.5Mn-0.1Co-0.05P | ◎ | ◎ |
| 63 | Cu-0.5Mn-0.8Co-0.4P | ◎ | ◎ |
| 64 | Cu-0.5Mn-1.3Co-0.6P | ◎ | ◎ |
| 65 | Cu-0.5Ni-0.01Co-0.005P | ◎ | ○ |
| 66 | Cu-0.5Ni-0.025Co-0.01P | ◎ | ◎ |
| 67 | Cu-0.5Ni-0.1Co-0.05P | ◎ | ◎ |
| 68 | Cu-0.5Ni-0.9Co-0.5P | ◎ | ◎ |
| 69 | Cu-0.5Ni-1.3Co-0.7P | ◎ | ◎ |
Qualified/defective judged result concentrated area that above-mentioned test obtains is illustrated in table 11～13.Find out that from showing to show in the inadequate situation of the content of the predetermined alloying element in being included in Cu, the effect that reduces contact resistivity is tending towards becoming insufficient.On the contrary, in the too big situation of content, the resistivity of Cu alloy film itself increases, and both of these case all can not satisfy purpose of the present invention.
So, be added to the kind and the quantity of the alloying element among the Cu by control suitably, even form on Cu alloy film in display device of the present invention and the interface between the nesa coating in the processing environment of oxidation film, also can directly connect on low-resistivity ground.And the thermotolerance of the sample of compound adding Fe or Co and P is satisfactory especially, is fit to the situation that the experience elevated temperature heat lags behind.Therefore, because in liquid crystal indicator as panel display apparatus with above-mentioned tft array substrate, can make the increase and discrete the minimizing of the contact resistance between pixel electrode (transparency electrode) and the direct interconnection part, so can prevent from the display screen quality is produced adverse influence, improve display quality significantly.
Figure 10 is the heat treatment temperature of typical sample in the above-mentioned test of expression and the figure of the relation between the resistivity.Find out that from this figure for each sample, in the thermo-lag between 100 ℃ and 400 ℃, resistivity obviously reduces.In the general step of preparation LCD, after forming the Cu interconnection, under about 250～350 ℃ temperature, implement thermal treatment.
Figure 11 is the heat treatment temperature of typical sample in the above-mentioned test of expression and the figure of the relation between the void level.Under 250 ℃ heat treatment temperature, the element that is selected from one or more kinds among Zn, Mg, Mn and the Ni by interpolation can prevent to produce the space.And in the situation of the thermo-lag that experiences 350 ℃ of higher temperature, can see, use the Cu alloy that has added Fe and P can prevent to produce the space widely.
Obviously see from test findings, unlike existing example, use barrier metal, in display device of the present invention, on the interface between Cu alloy film and the nesa coating, can directly connect on low-resistivity ground.Therefore, because in liquid crystal indicator as panel display apparatus with tft array substrate, the increase of contact resistance is minimized at pixel electrode (ELD) with being connected, so can prevent from the display screen quality is produced adverse influence, improve display quality significantly.
Claims (8)
1. display device, it comprises interconnecting parts, and described interconnecting parts comprises not direct-connected Cu alloy film and nesa coating via refractory metal film, and wherein said Cu alloy film contains Zn and/or the Mg that total amount is 0.1 atom %～3.0 atom %.
2. display device, it comprises interconnecting parts, and described interconnecting parts comprises not direct-connected Cu alloy film and nesa coating via refractory metal film, and wherein said Cu alloy film contains Ni and/or the Mn that total amount is 0.1 atom %～0.5 atom %.
3. display device as claimed in claim 1, wherein said Cu alloy film contain Fe and/or the Co that total amount is 0.02 atom %～1.0 atom %, and the P of 0.005 atom %～0.5 atom %.
4. display device as claimed in claim 2, wherein said Cu alloy film contain Fe and/or the Co that total amount is 0.02 atom %～1.0 atom %, and the P of 0.005 atom %～0.5 atom %.
5. display device as claimed in claim 1, wherein said nesa coating are indium tin oxide target ITO or indium zinc oxide IZO.
6. display device as claimed in claim 2, wherein said nesa coating are indium tin oxide target ITO or indium zinc oxide IZO.
7. display device as claimed in claim 1, wherein, laminated nesa coating is to form the thin slice connection electrode on described Cu alloy film.
8. display device as claimed in claim 2, wherein, laminated nesa coating is to form the thin slice connection electrode on described Cu alloy film.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005167185 | 2005-06-07 | ||
| JP2005167185 | 2005-06-07 | ||
| JP2005272643 | 2005-09-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1877428A CN1877428A (en) | 2006-12-13 |
| CN100412661C true CN100412661C (en) | 2008-08-20 |
Family
ID=37509901
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100912366A Expired - Fee Related CN100412661C (en) | 2005-06-07 | 2006-06-07 | Display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100412661C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20130048703A (en) * | 2011-11-02 | 2013-05-10 | 히타치 덴센 가부시키가이샤 | Thin film transistor, manufacturing method therefor, and display apparatus having thin film transistor, sputtering target material |
| JP5912046B2 (en) * | 2012-01-26 | 2016-04-27 | 株式会社Ｓｈカッパープロダクツ | THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE USING THE THIN FILM TRANSISTOR |
| JP6550514B2 (en) * | 2017-11-29 | 2019-07-24 | 株式会社神戸製鋼所 | Oxide semiconductor thin film for display, thin film transistor for display and sputtering target for display |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003058079A (en) * | 2001-08-14 | 2003-02-28 | Pioneer Electronic Corp | Laminate for forming substrate with wiring, substrate with wiring, and method of forming the same |
| JP2003297584A (en) * | 2002-04-04 | 2003-10-17 | Asahi Glass Co Ltd | Lamination body for forming base body with wiring, base body with wiring, and manufacturing method of the same |
| CN1480554A (en) * | 2002-09-03 | 2004-03-10 | 铼宝科技股份有限公司 | Alloy target material for conduction film and its preparation method |
-
2006
- 2006-06-07 CN CNB2006100912366A patent/CN100412661C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003058079A (en) * | 2001-08-14 | 2003-02-28 | Pioneer Electronic Corp | Laminate for forming substrate with wiring, substrate with wiring, and method of forming the same |
| JP2003297584A (en) * | 2002-04-04 | 2003-10-17 | Asahi Glass Co Ltd | Lamination body for forming base body with wiring, base body with wiring, and manufacturing method of the same |
| CN1480554A (en) * | 2002-09-03 | 2004-03-10 | 铼宝科技股份有限公司 | Alloy target material for conduction film and its preparation method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1877428A (en) | 2006-12-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100802879B1 (en) | Display device | |
| CN101253447B (en) | Thin-film transistor substrate and display device | |
| KR101124831B1 (en) | Display device, process for producing the display device, and sputtering target | |
| US7683370B2 (en) | Source/drain electrodes, transistor substrates and manufacture methods, thereof, and display devices | |
| KR101085271B1 (en) | Al ALLOY FILM FOR DISPLAY DEVICE, DISPLAY DEVICE, AND SPUTTERING TARGET | |
| US7154180B2 (en) | Electronic device, method of manufacture of the same, and sputtering target | |
| CN102741449B (en) | Al alloy film for display device | |
| US20110147753A1 (en) | Display device, copper alloy film for use therein, and copper alloy sputtering target | |
| US20110198602A1 (en) | Aluminum alloy film for display device, display device, and sputtering target | |
| CN100334239C (en) | Ag-base alloy distribution electrode film, Ag-base alloy sputtering target for panel display | |
| WO2008069214A1 (en) | Cu ALLOY WIRING FILM, FLAT PANEL DISPLAY TFT ELEMENT USING THE Cu ALLOY WIRING FILM, AND Cu ALLOY SPUTTERING TARGET FOR MANUFACTURING THE Cu ALLOY WIRING FILM | |
| US20070228575A1 (en) | Wiring material and wiring board using the same | |
| JPWO2008018490A1 (en) | Conductive film forming method, thin film transistor, thin film transistor panel, and thin film transistor manufacturing method | |
| EP1458030A2 (en) | Novel and conductive elements for thin film transistors used in a flat panel display | |
| JP2007081385A (en) | Source drain electrode, transistor substrate and method for manufacturing the same, and display device | |
| US20190148412A1 (en) | Multilayer wiring film and thin film transistor element | |
| CN100412661C (en) | Display device | |
| JP2008211230A (en) | Silver alloy material, circuit board, electronic device, liquid crystal display device, and display device | |
| KR20100060003A (en) | Display device and cu alloy film for use in the display device | |
| JP4421394B2 (en) | Silver alloy material, circuit board, electronic device, and method of manufacturing circuit board | |
| JP4264397B2 (en) | Ag-based alloy wiring electrode film for flat panel display, Ag-based alloy sputtering target, and flat panel display | |
| JP5368717B2 (en) | Display device and Cu alloy film used therefor | |
| JP4394466B2 (en) | Method of manufacturing array substrate capable of preventing copper diffusion | |
| KR100799824B1 (en) | Source/drain electrodes, transistor substrates and manufacture methods thereof, and display devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080820 Termination date: 20210607 |