CN1004111B - Process for treating fresh laver - Google Patents

Process for treating fresh laver Download PDF

Info

Publication number
CN1004111B
CN1004111B CN 86108698 CN86108698A CN1004111B CN 1004111 B CN1004111 B CN 1004111B CN 86108698 CN86108698 CN 86108698 CN 86108698 A CN86108698 A CN 86108698A CN 1004111 B CN1004111 B CN 1004111B
Authority
CN
China
Prior art keywords
circuit
control
logic unit
signal
trigger
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CN 86108698
Other languages
Chinese (zh)
Other versions
CN86108698A (en
Inventor
孙兴民
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
XI'AN MINIATURE MOTOR PLANT
Original Assignee
XI'AN MINIATURE MOTOR PLANT
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by XI'AN MINIATURE MOTOR PLANT filed Critical XI'AN MINIATURE MOTOR PLANT
Priority to CN 86108698 priority Critical patent/CN1004111B/en
Publication of CN86108698A publication Critical patent/CN86108698A/en
Publication of CN1004111B publication Critical patent/CN1004111B/en
Expired legal-status Critical Current

Links

Images

Classifications

    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/30—Reactive power compensation

Landscapes

  • Control Of Electrical Variables (AREA)
  • Feedback Control In General (AREA)

Abstract

The present invention provides a method of processing the laver, improves the efficiency of drying treatment and freezing treatment processes of laver, by washing raw laver consisting of laver leaf of >=30mum thick, dehydrating the cleaned laver and drying and scattering the laver at least to a water-content to unable the mutual adhesion of the laver leaves. The scattering treatment is preferably carried out in a dried atmosphere in a ventilative vessel. The scattered raw laver can be dried in scattered form or frozen. Then scattered laver can be obtained.

Description

Process for treating fresh laver
Power factor calibration system (or claiming reactive compensation system) in the past, drop into, exit in control capacitor aspect the mode of electrical network, mainly contain order (stepping) control mode, counting control mode and loop control mode, and be all independent employing.For example DRP DE3148060, the clear 54-89235 of Japanese Patent Laid-Open and " Fuji's Times " V 01, the device that proposes of 57No, 6PP375～379 (1984) just belongs to this class.Wherein adopt separately the more of counting control and loop control.Counting control mode, divides into groups capacitor according to the carry ladder of binary counting exactly, the input of the mode control capacitor of progressively increasing and successively decrease according to binary system when work or exit.The advantage of this mode is to obtain more adjusting ladder with less outlet loop.For example 15 capacitors by 1: 2: 4: 8 are divided into four groups (binary countings first to fourth), with four switches, by binary counting mode coding-control, can obtain 15 and regulate ladders.Loop control mode is divided into some groups compensation condenser exactly, with some switches, makes in a certain order compensation condenser put into operation successively.When compensation condenser is wanted time out of service, also to the order when dropping into carry out successively, realize first exiting that capacitor group first drops into, the backed off after random of rear input.Its advantage is to make each group capacitor operation chance (running time) roughly equal.
But the system that above-mentioned two kinds of modes form respectively has its shortcoming: counting control mode is due to the imbalance of capacitor grouping, while particularly more arriving a high position, the capacity of capacitor is larger, can feel difficulty to selecting of switch, the operation chance difference of each group capacitor is larger simultaneously.Loop control mode is owing to requiring capacity groupings such as capacitors, and group number can not (generally be divided into six groups or eight groups) too much regularly, therefore capacity regulating ladder is few, compensation precision is poor, while use in the distribution system of larger capacity, can make bucking-out system main circuit structure complexity, use element many.
The invention provides a kind of power factor calibration system that has counting and loop control mode advantage concurrently.Accompanying drawing 1 has been described system-wide functional-block diagram, can summarize with main circuit and control circuit thereof: described main circuit is by compensation condenser (1c 1～1c mand 2c 1～2c n) and by the access of this compensation condenser or exit the switch (1k of electrical network 1～1k mand 2k 1～2k n) composition.This main circuit switch can be all contact switch (for example A.C. contactor or other electromagnetic switch), can be also all noncontacting switch; Can also be by 1k 1～1k m(claiming m group switch) uses noncontacting switch (because control the break-make of m group capacitor, work is frequent), 2k 1～2k n(claiming n group switch) uses contact switch.Compensation condenser 1c in main circuit 1, 1c 21c mthe ratio of the capacitance of (claiming m group capacitor) is 2 0: 2 1: ...: 2 m-1; 2c 1～2c n(claim n group capacitor) respectively organized capacitance and equates, and adds a condenser capacity for the capacitance sum of m group capacitor.For example, in the time of m=2, m group capacitor is two groups, first group of 1 capacitor, second group of 2 capacitor; In the time of n=5, n group capacitor is five groups, and respectively organizing capacitance is (1+2)+1=4 (only) capacitance sum.Originally, in falling (or in most of the cases), in the time that true capacitor total capacity need to change, only need to change the group number (n) of n group capacitor.Like this, bucking-out system total capacitance (while expression with the number of elements of capacitor) is 3+4n (only).Described control circuit comprises:
A. power factor (merit reactive power) converter (1), connect electrical network, measure the analog signal that represents power factor of electric network, simultaneously by this signal with represent that the fiducial value of predetermined power factor of electric network upper and lower limit compares, show that indication actual electric network power factor exceeds the logical signal of predetermined upper limit value and lower limit value, delivers to control logic unit (4).
B. voltage comparator (2), connects electrical network, measures line voltage, compares with the overvoltage set-point of specifying simultaneously, draws and represents that line voltage rises to the superpotential logical signal of appointment, delivers to control logic unit (4).
Whether c. " invalid action " detection (3), can there is according to the working condition detection system of system the logical signal of " invalid action ", delivers to control logic unit (4).
D. device (5) is sent in pulse, produces control logic unit and the necessary clock pulse signal of other circuit working (as cp 1deng) production of pulse considers that compensation condenser drops into or exit the time interval of action before and after electrical network.
E. control logic unit (4), the logical signal that power factor converter (1), voltage comparator (2) and " invalid action " detection (3) are sent here, produce the logic control signal that compensation condenser is dropped into or exited electrical network through logical operation, (the control signal M that progressively increases, successively decreases produces in this unit) this signal is delivered to (1k in main circuit by outlet change-over circuit (6) 1～1k mand 2k 1～2k n) switch.
F. export change-over circuit (6), the logic control signal that control logic unit is sent here converts the voltage or the current signal that are enough to promote main circuit work to, delivers to main circuit (1k 1～1k mand 2k 1～2k n) switch, control main circuit switch break-make, make compensation condenser drop into or exit electrical network.
The feature of native system is in control logic unit (4), to be provided with (in main circuit) m group compensation condenser to implement the binary counting control circuit of fine tuning and the circulating controling circuit to n group compensation condenser enforcement coarse adjustment,
---for the m group capacitor of fine tuning, (1c 1～1c m) through m group switch (1k 1～1k m) drop into or exit electrical network; This m group switch connects the m position binary counting control circuit (1D in control logic unit (4) by outlet change-over circuit (6) 1～1D m),
---for the n group capacitor (2c of coarse adjustment 1～2c n), through n group switch (2k 1～2k n) drop into or exit electrical network; This n group switch connects the trigger (2D of circulating controling circuit in control logic unit (4) by outlet change-over circuit (6) 1～2D n),
---(commander m group electric capacity drops into or exit electrical network) m position binary counting control circuit (1D 1～1D m) by add gate (YF 1, F 2) or subtraction door (YF 2, F 3) connect the electric shock device (2D of (commander's n group capacitor drops into or exit electrical network) circulating controling circuit 1～2D n); After m position binary counting control circuit meter is completely counted, by add gate (YF 1, F 2) or subtraction door (YF 2, F 3) to the trigger (2D of circulating controling circuit 1～2D n) send progressively increase carry or the borrow pulse that successively decreases, (2D 1～2D n) trigger is at this pulse and state memorization link (3D thereof 1～3D n, 4D 1) under the control of the signal sent here and the control signal M that progressively increases, successively decreases, work by loop control mode, like this, just form compensation condenser (1c 1～1c m) drop into or exit electrical network, be by the enforcement fine tuning of counting control mode with to compensation condenser (2c 1～2c n) drop into or exit electrical network, be the power factor calibration system of implementing coarse adjustment by loop control mode.
Adopt the present invention, the operation chance of each group capacitor is roughly equal, and outlet loop number is few, main circuit structure is simple, use element is few, and total capacity changes easily, regulates ladder many (equaling capacitor number of elements), degree of regulation high (being that each instruction regulates a capacitor), close to step-less adjustment mode.
According to counting and the power factor calibration system of endless form work, can be by microprocessor (single board computer) by means of software control, also can be by digital integrated circuit control.Accompanying drawing 1 is the corrective system functional-block diagram with digital integrated circuit control.
Accompanying drawing 2 is to count in system control unit---loop control part electrical schematic diagram, is contained among control logic unit (4).Its composition and working principle is as follows:
1. binary counting control circuit is composed in series by m position trigger, and each has a trigger and affiliated add gate (1YF thereof k1) subtraction door (1YF k2) and comprehensive door (1YF k3) composition, K=1,2 ... m-1.The output signal of comprehensive door is
Figure B86103698_8D0000041
Figure B86103698_8D0000042
(1Q krepresent binary counter circuit 1 ... K position trigger Q end output signal in m position), the output signal of comprehensive door is delivered to the input of the CL end of next bit trigger and add gate, subtraction door.Trigger impulse CP 1deliver to and trigger according to 1D 1, input CL end.Use 1Q 1～1Q kcontrol respectively 1K 1～1K mbreak-make, makes 1C 1～1C mdrop into or exit electrical network.
2. in circulating controling circuit, be provided with circuit state memory link (circuit), it is by trigger 3D 1, 3D 23Dn composition.For guaranteeing first to make 3D after start 1, set up again by R for " 1 " by " 0 " upset 1, C 1the boot trigger device 4D of charging circuit control 1, R 1with C 1coupled in series point, is connected to 4D 1input D end.4D 1output
Figure B86103698_8D0000043
end is by diode D 1with 3D 1input D end connects.3D 1the output of～3Dn triggers at different levels end is held by diode (D with input D at the corresponding levels 31～D 3n) connect; 3D 1～3Dn output Q end is held by resistance (R with next stage input D 31～R 3n) connection (wherein 3Dn and 3D 1between pass through R 3nconnect) 3D 1～3Dn output Q end causes 2D simultaneously 1add gate under～2Dn, subtraction door input.
Except 3D 1, 4D 1cL end be subject to YF 4output control outside, all the other 3D 2-3D ncL end entirely controlled by the carry pulse end CP+ that progressively increases.YF 4input and YF 3output join, another inputs termination
Figure B86103698_8D0000045
yF 3an input termination 4D 1output end, another input termination CP 1.
At the initial stage of power connection, each trigger is by " zero clearing " (clear terminal and clear circuit, not shown in FIG.), and the Q of each trigger end is electronegative potential, and Q end is high potential.Due to diode D 1clamping action, 3D 1d end be high potential, all the other 3D 2～3D nd end be electronegative potential.4D 1d terminal potential due to capacitor C 1charging effect gradually by the low height that rises to, remain on high potential later always.At first CP 1pulse comes then, 4D 1and 3D 1be " 1 " by " 0 " upset simultaneously, and 3D 2～3D nkeep original " 0 " state constant.4D later 1keep one state constant, also due to D always 1buffer action, 4D 1output to 3D 1input again without impact.At this moment, due to D 31clamping action, 3D 1input be low level; Due to R 31effect, make 3D 2input D end be high potential.When first pulse CP+ that progressively increases comes then, 3D 2and 2D 1upset is for " 1 " is (about 2D 1working method after also to mention), 3D 1upset is " 0 ".And then, due to 3D 2the control object of output, makes 3D 2d end be electronegative potential, 3D 3d end be high potential, for the circuit conversion of lower step is got ready.When second, third ... when individual CP+ arrives, 3D 3, 3D 4upset is " 1 " step by step successively.Until n-1 CP+ be while arriving, 3D nupset is " 1 ".Due to R3 neffect, make again 3D 1d end be high potential; Due to D 3neffect, 3D nd end be electronegative potential.In the time that n CP+ pulse arrives, 3D nupset is " 0 ", and 3D 1upset is " 1 ", has reached the effect of circulation conversion.And guarantee 3D 1～3D nin to only have the upset of trigger be one state at every turn, all the other are " 0 " state, remember the corresponding trigger of just having worked in circulation link with regard to utilizing the trigger of this one state to go, provide the guiding level for this grade of conversion, thereby guarantee the upset successively of the flip-flop states of circulation link.
3. circulation link is by 2D 12D ncomposition.Each group is by a trigger and affiliated add gate (2YF thereof j1) subtraction door (2YF i2) and comprehensive door (2YF i3) composition, j=1,2 ... n.The output signal of comprehensive door is deliver to the input CL end (2Q of j group trigger ifor circulation link 2D 1～2D nin j group trigger Q end output signal; 3Q jfor memory link 3D 1～3D nin j joint trigger Q end output signal).The Q end of the each trigger of memory link directly connects the addition control gate input of the each corresponding stage of circulation link; The each trigger of memory link
Figure B86103698_8D00000410
end also passes through resistance R 21～R 2nmeet the subtraction door input 2D of the each corresponding stage of circulation link 1～2D nq hold through corresponding stage isolating diode (D 21～D 2n) deliver to next stage subtraction control gate input.At different levelsly add, the output of subtraction control gate.Through Comprehensive Control behind the door, deliver to 2D 1～2D nin the CL end of each corresponding stage trigger.The control signal M that successively decreases that progressively increases causes 2D 1～2D nthe input D end of each trigger.In the time that M is high potential, the upset of can progressively increasing of the each trigger of circulation link; In the time that M is electronegative potential, the upset of can successively decreasing.2D 1～2D noutput, through 2K 1～2K nmake 2C 1～2C naccess or exit electrical network.
(1) certain one-level trigger of circulation link, must be satisfied condition for " 1 " by " 0 " upset:
A.M is high potential;
B. the trigger of memory link at the corresponding levels is in one state;
When c.CP+ pulse arrives.
For example: M is high potential, 3D 1for one state, in the time that CP+ arrives, 2D 1could be " 1 " by " 0 " upset.
Under the effect of the carry pulse CP+ that progressively increases, circulating controling circuit (comprising circuit state memory link and circulation link) is " 1 " by " 0 " upset successively.3D 1～3D nto 2D 1～2D nupset, played " guiding " effect.
(2) certain one-level trigger of circulation link, is " 0 " by " 1 " upset, must satisfy condition:
A.M is electronegative potential;
B. memory link trigger at the corresponding levels is in one state;
C. previous stage trigger is in " 0 ";
D. when the borrow pulse CP-that successively decreases arrives.
So just make the first trigger for " 1 ", first upset is " 0 "; The rear upset that is afterwards one state is " 0 ", has realized " circulation " working method.
(3) work as 2D 1～2D nwhile being all one state, due to each trigger periodic duty successively of circuit state memory link, and because its output Q end connects with subtraction couplet on the door of the each respective stages of circulation link, so the corresponding circulation link of its trigger that be one state trigger is to be " 1 " at first.In the time that the borrow pulse CP-that successively decreases arrives, with the trigger of the corresponding circulation link of memory link one state trigger, be first " 0 " by " 1 " upset.
4. progressively increase carry pulse CP+ and the generation of borrow pulse CP-of successively decreasing.
By 1D 1～1D mq end and the CP of each trigger 1cause YF 1input, YF 1output is through F 2after paraphase, export CP+; Only have m the trigger (1D when m position binary counting control circuit 1～1D m) while being all " 1 ", the trigger impulse CP being produced by pulse generator 1, could form the carry pulse CP+ that progressively increases of circulating controling circuit.By 1D 1～1D meach trigger end and CP 1cause YF 2input, YF 2output through F 3after paraphase, export CP-; Only has in the time that m d type flip flop of m position binary counting control circuit is all " 0 " CP 1could form the borrow pulse CP-that successively decreases of circulating controling circuit.

Claims (1)

1. a system for automatic correcting wire power efficiency, is made up of main circuit and control circuit thereof.Main circuit is by compensation condenser (1c 1～1c mand 2c 1～2c n) and by the access of this compensation condenser or exit the switch (1k of electrical network 1～1k mand 2k 1～2k n) composition, described control circuit comprises:
A. power factor (or reactive power) converter (1), connect electrical network, measure the analog signal that represents power factor of electric network, this signal is transformed into the logical signal that exceeds pre-determined network power factor upper and lower limit simultaneously, deliver to control logic unit (4);
B. voltage comparator (2), connects electrical network, measures line voltage, compares with specifying overvoltage set-point simultaneously, draws and represents that line voltage rises to the superpotential logical signal of appointment, delivers to control logic unit (4);
Whether c. " invalid action " detection (3), can there is " invalid action " according to the working condition detection system of system, and whether representative system is occurred to " logical signal of invalid action is delivered to control logic unit (4);
D. pulse generator (5), produces clock pulse, delivers to control logic unit (4) and other circuit;
E. control logic unit (4), the logical signal that power factor converter, voltage comparator and " invalid action " detection are sent here, produce the logical signal that drops into or exit compensation condenser through logical operation, deliver to (1k in main circuit by output conversion circuit (6) 1～1k m) and (2k 1～2k n) switch;
F. export change-over circuit (6), the logic control signal that control logic unit is sent here converts the voltage or the current signal that are enough to promote main circuit work to, delivers to main circuit (1k 1～1k m) and (2k 1～2k n) switch;
The feature of native system is in control logic unit (4), to be provided with total compensation capacity to carry out the binary counting control circuit of fine tuning (control m group compensation condenser) and total compensation capacity is carried out to the cycling circuit of coarse adjustment (controlling m group compensation condenser)
-for the m group capacitor of fine tuning, organize switch (1k through m 1～1k m) drop into or exit electrical network; This m group switch connects the m position binary counting control circuit in control logic unit (4) by outlet change-over circuit (6),
-for the n group capacitor of coarse adjustment, organize switch (2k through n 1～2k n) drop into or exit electrical network; This n group switch connects the trigger (2D of circulating controling circuit in control logic unit (4) by outlet change-over circuit (6) 1～2D n),
---after m position binary counting control circuit meter is completely counted, by add gate (YF 1, F 2) or subtraction door (YF 2, F 3) to the trigger (2D of circulating controling circuit 1～2D n) send progressively increase carry or the borrow pulse that successively decreases, (2D 1～2D n) trigger is at this pulse and state memorization link (3D thereof 1～3D n, 4D 1) under the control of the signal sent here and the control signal M that progressively increases, successively decreases, work by loop control mode, forming compensation condenser is dropped into or exits electrical network, is the power factor calibration system of implementing fine tuning and implementing coarse adjustment by loop control mode by counting control mode.
CN 86108698 1986-12-22 1986-12-22 Process for treating fresh laver Expired CN1004111B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 86108698 CN1004111B (en) 1986-12-22 1986-12-22 Process for treating fresh laver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 86108698 CN1004111B (en) 1986-12-22 1986-12-22 Process for treating fresh laver

Publications (2)

Publication Number Publication Date
CN86108698A CN86108698A (en) 1988-07-06
CN1004111B true CN1004111B (en) 1989-05-03

Family

ID=4804014

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 86108698 Expired CN1004111B (en) 1986-12-22 1986-12-22 Process for treating fresh laver

Country Status (1)

Country Link
CN (1) CN1004111B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007033599A1 (en) * 2005-09-26 2007-03-29 Ruitian Su A customer intelligent reactive power automatic compensation energy-saved device
USRE40528E1 (en) 2001-03-30 2008-10-07 Mitsubishi Denki Kabushiki Kaisha Voltage fluctuation compensating apparatus

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114336652B (en) * 2020-10-12 2024-03-15 南京南瑞继保电气有限公司 Method and device for controlling alternating current bus voltage, electronic equipment and system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE40528E1 (en) 2001-03-30 2008-10-07 Mitsubishi Denki Kabushiki Kaisha Voltage fluctuation compensating apparatus
WO2007033599A1 (en) * 2005-09-26 2007-03-29 Ruitian Su A customer intelligent reactive power automatic compensation energy-saved device
US7872453B2 (en) 2005-09-26 2011-01-18 Ruitian Su Customer intelligent reactive power automatic compensation energy-saved device

Also Published As

Publication number Publication date
CN86108698A (en) 1988-07-06

Similar Documents

Publication Publication Date Title
EP2122817B1 (en) Drive for a phase module branch of a multilevel converter
DE69933817T2 (en) Device for temperature measurement and identification of a battery pack
DE4243710C2 (en) Charging process for accumulators and switching arrangement for carrying out the process
CN86103901A (en) The root-mean-square value counting circuit of digital circuit cutout
EP1324496B1 (en) Method and arrangement for digitising a voltage
US4321477A (en) Energy management apparatus and method
KR0125242B1 (en) A/d converter and micro-computer
CN1004111B (en) Process for treating fresh laver
WO2011144509A2 (en) Inductive battery-balancing with reduced circuit complexity
CN102742116A (en) Storage-module control device
DE4106725A1 (en) BATTERY CHARGE LEVEL INDICATOR
EP0442898A1 (en) Method and apparatus for measurement of capacitance and for capacitive measurement of displacement.
WO2003071291A1 (en) Method and circuit arrangement for determining the average current consumption of a battery-operated apparatus
CN1329736C (en) Device for measuring the consumption of electrical energy
US5276603A (en) Sixteen level power supply with asynchronous controller
CN101363879B (en) Electrical level polar conversion device, electric voltage sampling apparatus and electric voltage sampling method
DE60035469T2 (en) Method for ensuring the inviolability of a chip card micro module against a power consumption analysis and corresponding micromodule
CN87104460A (en) Digital feedback double sampling high precision analog-digital converter
CN110112908A (en) A kind of charge pump, control method and chip
DE19634267C2 (en) Charging procedure for accumulators
SU1065958A1 (en) System for distributing electric load of electric power station
GB2374991A (en) Battery charge balancing system
SU1543395A1 (en) Device for adjustment of m-phase voltage
CN114094834A (en) Switched capacitor access type direct current transformer and control method thereof
CN1086236C (en) Automatic testing device of computer mouse optical coupling input signal

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C13 Decision
GR02 Examined patent application
C14 Grant of patent or utility model
GR01 Patent grant
C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee