CN100409418C - QFN chip packaging technique - Google Patents
QFN chip packaging technique Download PDFInfo
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- CN100409418C CN100409418C CNB2006100296379A CN200610029637A CN100409418C CN 100409418 C CN100409418 C CN 100409418C CN B2006100296379 A CNB2006100296379 A CN B2006100296379A CN 200610029637 A CN200610029637 A CN 200610029637A CN 100409418 C CN100409418 C CN 100409418C
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- chip
- gold thread
- plastic packaging
- lead frame
- qfn
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Packaging Frangible Articles (AREA)
Abstract
The invention offers new type QFN chip packaging technology. It includes the following steps: pressing metal sheet to form lead frame to replace PPF frame; setting chip seat and gold thread bonding point on the lead frame surface; coating silver glue on chip back plate; adhering the chip on the back plate; bonding the chip and the gold thread bonding point by gold thread; injection molding one lead frame and packaging chip and gold thread in plastics; removing the metal sheet; laser printing; stamping blue film on the back; cutting into independent piece and removing the blue film; testing and packaging finished product. It has the advantages of low cost, high welding performance, long cutting blade useful life, and no metal burr.
Description
Technical field
The present invention relates to a kind of packaging technology of QFN chip, particularly a kind of high performance QFN packaging technology belongs to integrated circuit or discrete component encapsulation technology field.
Background technology
Traditional QFN encapsulation, its encapsulation pattern mainly by after the framework encapsulation of cell array formula through being cut into independently unit, its substrate is the framework of etched back pad pasting.Mainly have the following disadvantages:
1. special-purpose high temperature resistance diaphragm need be pasted in the framework back side, and owing to heat, back side pad pasting can give out harmful chemical, causes the pollution in framework and chip routing zone, influences the bonding wire craft quality, influences product quality in the use.
2. the cost height of back side film, framework uses PPF technology, thereby the price that has caused framework than general framework height, thereby improved the cost of overall package.
3. use cutter cutting and separating device, cutter also can switch to metal in the cutting process in the cutting plastic packaging material.Cause product pin edge crimping, reduce blade life, influence product quality and SMT quality.
4. during plastic packaging, the bottom of frame pin and plastic packaging material is the same flat, and the Weldability performance is bad when surface mount.
Summary of the invention
The objective of the invention is to solve the deficiency that the said chip packaging technology exists, provide a kind of with low cost, welding performance is strong, and is best in quality, increases the QFN chip packaging technique in cutting blade life-span.This potting process is:
A, stamped metal thin plate are made lead frame, replace PPF and electroplate framework in advance; And cooperate fixed frame to replace back side high temperature pad pasting with thin plate; Chip carrier and gold thread bonding point are arranged on lead frame surface;
B, on chip carrier, be coated with elargol;
C, with chip attach to chip carrier, and curing operation after finishing;
D, chip and gold thread bonding point are carried out bonding with gold thread;
E, carry out injection molding on the surface of lead frame with plastic packaging material, plastic packaging chip and gold thread;
Peel off the sheet metal of anchor leg framework behind f, the plastic packaging;
G, with the product array that encapsulation is finished, carry out laser printing;
H, with printed product array, blue film is sticked at the back side, cuts, the product after the cutting is peeled off blue film, is divided into independent devices;
J, test, packed products.
The sheet metal thickness of lead frame is between 0.05 to 0.30mm, and sheet metal is made up of Cu alloy material.When bonding chip, there is not back side high temperature pad pasting.Plastic packaging does not comprise the thin plate plastic packaging to the anchor leg framework.
Characteristics of the present invention are that at first, novel frame replaces pad pasting PPF and electroplates framework in advance.Novel frame adopts special ram frame, replaces original back side pad pasting with sheet metal and fixes each independently frame unit.And the corresponding independence of framework indoor design does not have the muscle that links to each other to connect between each unit, the wearing and tearing that the cutter cutting metal causes when having reduced the device cutting behind plastic packaging and the minimizing and the corresponding defective of blade life.Because there is not pad pasting in the framework back side, the situation of chemical substance pollution framework and chip will be stopped, and consequent bonding wire quality problems will not exist.
Secondly, because sheet metal replaces back side pad pasting, need after plastic packaging is finished the sheet metal of lead frame is peeled off when the framework of finishing the operation of gold thread bonding is carried out the plastic packaging operation, the array plastic device aggregate that this moment, pin exposed has just produced.
Once more, on the anti-UV of the being attached to film of the plastic-sealed body of finishing the thin plate overburden operation, utilize cutting machine with colloid when separated, owing to there is not metal ribs to link to each other between the device, so only can switch to plastic packaging material during the cutter cutting, can not cut to metal, thereby prolong the life-span of cutter, the shortcoming of metallic bur power also thoroughly solves.
Above-mentioned technical process is compared with traditional QFN encapsulation has following advantage:
1. need not use the special-purpose high temperature pad pasting, reduce the influence of pernicious gas to gold thread bonding quality, the cost of material is low.
2. when the novel encapsulated body cut, cutter only can switch to colloid, can not switch to metal framework, can not cause the minimizing in cutter life-span, did not also cause the phenomenon of metallic bur power.
3. pin exposes and makes things convenient for the device surface mount, improves welding quality.
Description of drawings
Accompanying drawing 1 (comprising accompanying drawing 1a, accompanying drawing 1b, 1c) is a frame construction drawing of the present invention.
Accompanying drawing 2 is to coat elargol on the chip backing plate.
Accompanying drawing 3 is that solidify chip attach back on elargol.
Accompanying drawing 4 carries out the gold thread bonding on chip.
Accompanying drawing 5 is that the chip behind the para-linkage carries out plastic packaging.
Accompanying drawing 6 is product schematic diagrames of peeling off behind the sheet metal at the framework back side.
Accompanying drawing 7 is schematic diagrames that product is cut.
Accompanying drawing 8 (comprising accompanying drawing 8a, 8b, 8c, 8d) is the product schematic diagram that cuts into individual devices.
Label declaration in the accompanying drawing
1-chip backing plate 2-elargol
3-chip 4-gold thread
The outer plastic packaging material 6-of 5-lead frame
Embodiment
Consult shown in the accompanying drawing 1, Fig. 1 a is the vertical view of novel frame, and Fig. 1 b is the rear view of framework, and Fig. 1 c is the cross sectional view of framework; Label 1 among Fig. 1 a is the chip backing plate.Accompanying drawing 2 is to coat elargol 2 on chip backing plate 1.Accompanying drawing 3 is on elargol 2, pastes chip 3, finishes curing operation then.Accompanying drawing 4 is to carry out gold thread 4 bondings according to the characteristic of product.Accompanying drawing 5 is products that bonding is good, carries out the plastic packaging operation according to the characteristic of plastic packaging material, the 5th, and outer plastic packaging material needs after the encapsulation metal lead wire frame 6 is peeled off, and bottom pin metal is exposed, as shown in Figure 6.
Consult shown in the accompanying drawing 8, wherein: Fig. 8 a is after cutting into individual devices, the vertical view of product; Fig. 8 b is the rear view of Fig. 8 a; Fig. 8 c is a product device inside structure chart independently; Fig. 8 d is a cross sectional view.
Claims (5)
1. a QFN chip package process is characterized in that, the process of its packaging technology is:
A, stamped metal thin plate are made lead frame, replace the pre-framework (PPF) of electroplating;
B, chip carrier and gold thread bonding point are arranged on lead frame surface;
C, on chip carrier, be coated with elargol;
D, with chip attach to chip carrier, and curing operation after finishing;
E, chip and gold thread bonding point are carried out bonding with gold thread;
F, carry out injection molding on the surface of lead frame with plastic packaging material, plastic packaging chip and gold thread;
Peel off the sheet metal of anchor leg framework behind g, the plastic packaging;
H, with the product array that encapsulation is finished, carry out laser printing;
I, with printed product array, blue film is sticked at the back side, cuts, the product after the cutting is peeled off blue film, is divided into independent devices;
J, test, packed products.
2. QFN chip package process according to claim 1 is characterized in that: the sheet metal thickness of described anchor leg framework is between 0.05 to 0.30mm.
3. QFN chip package process according to claim 1 is characterized in that: described sheet metal is made up of Cu alloy material.
4. QFN chip package process according to claim 1 is characterized in that: when bonding chip, the existence of high temperature resistant pad pasting can not be arranged.
5. QFN chip package process according to claim 1 is characterized in that: plastic packaging does not comprise the plastic packaging to the sheet metal of anchor leg framework.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100296379A CN100409418C (en) | 2006-08-01 | 2006-08-01 | QFN chip packaging technique |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100296379A CN100409418C (en) | 2006-08-01 | 2006-08-01 | QFN chip packaging technique |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1905142A CN1905142A (en) | 2007-01-31 |
| CN100409418C true CN100409418C (en) | 2008-08-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100296379A Active CN100409418C (en) | 2006-08-01 | 2006-08-01 | QFN chip packaging technique |
Country Status (1)
| Country | Link |
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| CN (1) | CN100409418C (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100568476C (en) * | 2008-07-30 | 2009-12-09 | 江苏长电科技股份有限公司 | Slotted metal plate type semi-conductor package method |
| CN100568477C (en) * | 2008-07-30 | 2009-12-09 | 江苏长电科技股份有限公司 | Metal plate type semiconductor packaging method |
| CN101697348B (en) * | 2009-10-11 | 2013-06-26 | 天水华天科技股份有限公司 | Small-carrier flat-four-side pin-less packaging part and preparation method thereof |
| CN102074534B (en) * | 2009-11-24 | 2013-05-29 | 上海长丰智能卡有限公司 | Micro PCB radio frequency module and packaging method thereof |
| CN102082100B (en) * | 2009-11-30 | 2013-05-15 | 万国半导体有限公司 | Packaging method for semiconductor devices with bulged pins |
| CN102244058A (en) * | 2010-05-13 | 2011-11-16 | 群丰科技股份有限公司 | Quad flat lead-free semiconductor package and manufacturing method thereof and metal plate used in manufacturing method |
| CN102290358A (en) * | 2011-08-26 | 2011-12-21 | 上海凯虹电子有限公司 | Square flat no-pin packaging body and manufacturing method thereof |
| CN102544262A (en) * | 2012-01-17 | 2012-07-04 | 成都泰鼎科技有限公司 | LED (light-emitting diode) chip packaging process |
| CN102779763A (en) * | 2012-06-05 | 2012-11-14 | 华天科技（西安）有限公司 | Corrosion-based AAQFN product secondary plastic package processing technology |
| CN108649020A (en) * | 2018-05-18 | 2018-10-12 | 上海凯虹科技电子有限公司 | The packaging method of stacked chips and the packaging body manufactured using this method |
| CN109326529B (en) * | 2018-09-29 | 2020-04-24 | 中电智能卡有限责任公司 | DFN/QFN production process |
| CN113507785A (en) * | 2021-06-08 | 2021-10-15 | 广州致远电子有限公司 | Transformer-based packaging module preparation method |
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|---|---|---|---|---|
| CN1098558A (en) * | 1993-03-22 | 1995-02-08 | 莫托罗拉公司 | The semiconductor device of Flagless and manufacture method thereof |
| JP2001077266A (en) * | 1999-09-01 | 2001-03-23 | Matsushita Electronics Industry Corp | Manufacture of resin sealed semiconductor device |
| CN1412843A (en) * | 2001-10-15 | 2003-04-23 | 新光电气工业株式会社 | Lead frame, its manufacturing method and manufacturing method of semiconductor device using lead frame |
| CN1414629A (en) * | 2001-10-26 | 2003-04-30 | 新光电气工业株式会社 | Lead frame, its manufacturing method and manufacturing method for semiconductor device using it |
| JP2003158142A (en) * | 2001-11-21 | 2003-05-30 | Mitsui High Tec Inc | Manufacturing method of semiconductor |
| CN1577828A (en) * | 2003-07-02 | 2005-02-09 | 株式会社瑞萨科技 | Semiconductor device and lead frame |
-
2006
- 2006-08-01 CN CNB2006100296379A patent/CN100409418C/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1098558A (en) * | 1993-03-22 | 1995-02-08 | 莫托罗拉公司 | The semiconductor device of Flagless and manufacture method thereof |
| JP2001077266A (en) * | 1999-09-01 | 2001-03-23 | Matsushita Electronics Industry Corp | Manufacture of resin sealed semiconductor device |
| CN1412843A (en) * | 2001-10-15 | 2003-04-23 | 新光电气工业株式会社 | Lead frame, its manufacturing method and manufacturing method of semiconductor device using lead frame |
| CN1414629A (en) * | 2001-10-26 | 2003-04-30 | 新光电气工业株式会社 | Lead frame, its manufacturing method and manufacturing method for semiconductor device using it |
| JP2003158142A (en) * | 2001-11-21 | 2003-05-30 | Mitsui High Tec Inc | Manufacturing method of semiconductor |
| CN1577828A (en) * | 2003-07-02 | 2005-02-09 | 株式会社瑞萨科技 | Semiconductor device and lead frame |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1905142A (en) | 2007-01-31 |
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