CN100394623C - Packing substrate structure of optical diode and preparing method - Google Patents
Packing substrate structure of optical diode and preparing method Download PDFInfo
- Publication number
- CN100394623C CN100394623C CNB2006100771847A CN200610077184A CN100394623C CN 100394623 C CN100394623 C CN 100394623C CN B2006100771847 A CNB2006100771847 A CN B2006100771847A CN 200610077184 A CN200610077184 A CN 200610077184A CN 100394623 C CN100394623 C CN 100394623C
- Authority
- CN
- China
- Prior art keywords
- substrate
- layer
- optical diode
- silicon oxide
- encapsulation base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Led Device Packages (AREA)
Abstract
The present invention relates to a packing substrate structure of an optical diode and a manufacturing method. The present invention mainly adopts the steps that a first masking layer and a second masking layer are formed on a first surface and a second surface of a base plate; a first opening and a second opening are defined in the first masking layer and the second masking layer; the area of the first opening is larger than the area of the second opening; wet type etching is carried out to the base plate so as to form an optical diode packing substrate structure which is provided with a loading space and at least two conduction holes consequently, wherein the top opening of the loading space is positioned in the first surface of the base plate, and the bottom of the loading space is used for loading the optical diode; the bottom openings of the conduction holes are positioned in the second surface of the base plate, and the tops of the conduction holes are communicated with the bottom of the loading space; besides, the junction position between the side walls of the conduction holes and the bottom of the loading space is provided with at least one bevel structure. The present invention overcomes the problem that a conductive layer faults in the prior art; besides, in an integral structure, fraction defective generated during the packing of the optical diode can be reduced largely.
Description
Technical field
The present invention relates to packaging substrate structure of a kind of optical diode and preparation method thereof, relate in particular to structure of a kind of optical diode encapsulation base with the through-hole structure that prevents pedestal leakage current and conductive layer tomography and preparation method thereof.
Background technology
Light-emitting diode (Light Emitting Diode is hereinafter to be referred as LED) is a kind of luminescent device that can directly electric energy be converted into visible light and radiant energy, its luminous principle is that two terminals of both positive and negative polarity apply voltage in semiconductor, when electric current passes through, when electronics is combined with the hole, dump energy just discharges with the form of light, difference and its energy level of complying with the material of its use just make photon energy produce the light of different wave length, therefore, it is low that light-emitting diode (LED) has operating voltage usually, power consumption is little, the luminous efficiency height, emission response time is extremely short, photochromic pure, sound construction, shock resistance, vibration resistance, stable and reliable for performance, series of characteristics such as the little and cost of volume in light weight is low, its development is advanced by leaps and bounds, and now can produce the versicolor high brightness of whole visible spectrum in a large number, premium quality product.And light-emitting diode (LED) production process in the industry cycle mainly can be divided into the upstream is light-emitting diode (LED) substrate chip and substrate production, the industry in middle reaches turns to light-emitting diode (LED) chip design and makes and produce, the downstream then is light-emitting diode (LED) packaging and testing, wherein whether superior the encapsulation of light-emitting diode (LED) be to influence light-emitting diode (LED) finished product important key technology, and the encapsulation of traditional light-emitting diode mainly is divided into two kinds of circuit board type and support rack types, wherein this circuit board type utilizes composite material circuit board to carry out sealing in the mode of mold casting forming (molding) again for substrate, and support rack type utilizes metallic support to carry out sealing in the mode of jet-out plastic groove or mold casting forming (molding) again for substrate, and not good etc. the common drawback of the not enough and thermal diffusivity of temperature tolerance is all arranged under this method for packing of two kinds.
From the above, in view of this, a kind of manufacture method of base plate for packaging of light-emitting diode has been proposed in U.S. Pat 6531328B1, this method step such as Fig. 1 (a), (b), (c), (d), (e), (f) and (g), from we can find out clearly that the employed substrate of this manufacture method is the silicon substrate of being made by the silicon of 100 lattice direction 1 (shown in Fig. 1 (a)) the figure, at first on this silicon substrate 1, be coated with last layer photoresist layer 10 (shown in Fig. 1 (b)), utilize masked etch process that the photoresistance in zone 11 (exposure imaging districts) is removed (shown in Fig. 1 (c)), afterwards silicon substrate is utilized etching solution to carry out wet etching and form groove 12, and the groove 12 that etches is for having the inclined wall 13 (shown in Fig. 1 (d)) of inclination angle 54.74 degree, and shown in Fig. 1 (e), it forms this silicon substrate 1 structure chart with groove after removing photoresistance.Coat photoresist layer on the back side with this silicon substrate 1 in Fig. 1 (f) and be provided with development electrode through hole pattern in the back side of groove relative position mask, utilize mask etching and dry etching process and form half perforation 14 and guiding electrode hole 15 simultaneously, plate the insulating barrier 16 that silica or silicon nitride are finished at last on the front of this silicon substrate 1 that shown in Fig. 1 (g), will be shaped and 19 surfaces, the back side, on this insulating barrier, plate conductive layer 17, the package substrate construction of the light-emitting diode of promptly finishing foregoing invention and being disclosed.
Yet; the existing package substrate construction of above-mentioned light-emitting diode is in the process of making; owing to must carry out the etching positive and back side to this silicon substrate 1 by the mode of wet etching and dry ecthing; therefore the manufacturing process step at whole base plate for packaging can seem comparatively loaded down with trivial details; relative also can and then improve on cost of manufacture; in addition; the base plate for packaging of being finished with above-mentioned manufacture method is encapsulating the finished product that the back is finished with LED crystal particle; often having situation about can't normally conduct electricity takes place; its reason is exactly when being that this conductive layer 17 is plated on the guiding electrode hole 15 of this silicon substrate 1; the fault-layer-phenomenon that the meeting generation can not be expected; cause the raising of the packaged finished product disqualification rate of finishing of this encapsulation base and LED crystal particle; moreover be exactly to have encapsulated the finished product of LED finished on being welded in circuit board the time; 18 situation takes place to the side from the back side 19 adverse currents of this silicon substrate 1 usually to have scolder; so also can cause the leakage current of assembly excessive; and how to improve at above-mentioned deficiency, for developing topmost purpose of the present invention.
Summary of the invention
The present invention is a kind of encapsulation base manufacture method of optical diode, and this method comprises the following step: a substrate is provided; Respectively at forming first mask layer and second mask layer on the first surface of this substrate and the second surface; Define first opening and second opening on this first mask layer and this second mask layer, the area of this first opening is greater than second opening; This substrate is carried out Wet-type etching, and then form the bearing space and at least two vias that to place for optical diode respectively, make the top of these vias be communicated to the bottom of this bearing space respectively at this first opening part and this second opening part; And this substrate proceeded Wet-type etching, with the sharp edges of the sidewall intersection of the bottom of removing this bearing space and this via and form at least one inclined-plane.
According to above-mentioned conception, the encapsulation base manufacture method of optical diode of the present invention, wherein this substrate is the high impedance silicon substrate of 100 lattice direction, the high impedance silicon substrate of this 100 lattice direction is at this bearing space that carries out being etched behind this Wet-type etching, angle between its bottom and sidewall is 54.74 or 45 degree, and these vias that etched, the angle between its top and sidewall is 54.74 or 45 degree.
According to above-mentioned conception, the encapsulation base manufacture method of optical diode of the present invention, wherein this substrate utilizes concentration to carry out Wet-type etching at 20～35 percentage by weights and temperature at the potassium hydroxide or the tetramethyl-ammonium hydroxide solution of 80～95 degree Celsius.
According to above-mentioned conception, the encapsulation base manufacture method of optical diode of the present invention, wherein the formation method of this first opening and this second opening comprises the following step: this first surface and this second surface in this substrate form respectively by silicon nitride, silica or metal this first mask layer and this second mask layer; On this first mask layer and this second mask layer, form first photoresist layer and second photoresist layer respectively; Utilize first mask and second mask on these photoresist layers, to define the first photoresistance pattern and the second photoresistance pattern; And according to this first photoresistance pattern and this second photoresistance pattern described first mask layer and second mask layer are carried out etching and form this first opening and this second opening.
According to above-mentioned conception, the encapsulation base manufacture method of optical diode of the present invention also comprises the following step: this first surface and this second surface of this substrate after carrying out Wet-type etching form first insulating layer of silicon oxide; On this first insulating layer of silicon oxide of this first surface, form reflection layer; On this reflection layer, form second insulating layer of silicon oxide; And on this first silicon oxide layer of this second insulating layer of silicon oxide and this second surface, form conductive layer.
According to above-mentioned conception, the encapsulation base manufacture method of optical diode of the present invention, wherein this first insulating layer of silicon oxide forms in the mode of high-temperature oxydation.
According to above-mentioned conception, the encapsulation base manufacture method of optical diode of the present invention, wherein this reflection layer is by the very high aluminium of one deck light reflex rate or ag material is made and formed by the mode of evaporation or sputter.
According to above-mentioned conception, the encapsulation base manufacture method of optical diode of the present invention, wherein this second insulating layer of silicon oxide is formed by plasma-enhanced chemical vapor deposition PECVD method or low-temperature atmosphere-pressure chemical vapour deposition technique or low-temp low-pressure boiler tube mode.
According to above-mentioned conception, the encapsulation base manufacture method of optical diode of the present invention, wherein this conductive layer is made by TiW/Cu/Ni/Au, Ti/Cu/Ni/Au, Ti/Au/Ni/Au or AlCu/Ni/Au alloy, and its formation method comprises the following step: define first plating area and second plating area by the 3rd mask and the 4th mask on first insulating layer of silicon oxide of this second insulating layer of silicon oxide and this second surface; And add with sputter and to electroplate or mode that sputter adds chemical plating forms this conductive layer in this first plating area and this second plating area.
According to above-mentioned conception, the encapsulation base manufacture method of optical diode of the present invention, wherein this second surface can be formed with the scolder counter-flow preventing structure, and its formation method comprises the following step: defining the 3rd opening on formed this second mask layer on this second surface of this substrate; This substrate is carried out Wet-type etching, and form this scolder counter-flow preventing structure in the 3rd opening part.
According to above-mentioned conception, the encapsulation base manufacture method of optical diode of the present invention, wherein this scolder counter-flow preventing structure can be an inclined-plane or has the relief region of a plurality of concavo-convex things.
According to above-mentioned conception, the encapsulation base manufacture method of optical diode of the present invention, wherein this optical diode is light-emitting diode or laser diode.
Another aspect of the present invention is a kind of encapsulation base, be applied on the optical diode, this encapsulation base comprises: substrate, and it has first surface and second surface; Bearing space, its open top are positioned at this first surface of substrate, and its bottom is in order to carry this optical diode; And via, its bottom opening is positioned at this second surface of this substrate, and the top of this via is communicated in the bottom of this bearing space, and the bottom intersection of the sidewall of this via and this bearing space has the structure on an inclined-plane at least.
According to above-mentioned conception, described on the other hand this encapsulation base of the present invention, wherein this substrate is the high impedance silicon substrate of 100 lattice direction, and the bottom of this bearing space and the angle between sidewall are 54.74 degree or 45 degree, and the top of this via and the angle between sidewall are 54.74 degree or 45 degree.
According to above-mentioned conception, described on the other hand this encapsulation base of the present invention, wherein this second surface surrounding edge place of this substrate is formed with an inclined-plane and the scolder counter-flow preventing structure with relief region of a plurality of concavo-convex things.
According to above-mentioned conception, described on the other hand this encapsulation base of the present invention also comprises: first insulating layer of silicon oxide, and it is formed on this first surface and this second surface of this substrate; Reflection layer, it is made and is formed on this first insulating layer of silicon oxide of this first surface by aluminium or ag material; Second insulating layer of silicon oxide, it is formed on this reflection layer; And conductive layer, it is made and is formed on this first insulating layer of silicon oxide of this second insulating layer of silicon oxide and this second surface by TiW/Cu/Ni/Au, Ti/Cu/Ni/Au, Ti/Au/Ni/Au or AlCu/Ni/Au alloy.
According to above-mentioned conception, described on the other hand this encapsulation base of the present invention, also comprise adhesion layer, it is finished and is formed on the conductive layer of this first surface with Al/Ti/AuSn or Ti/Au/AuSn alloy, and then this optical diode is packaged together to cover brilliant mode and this encapsulation base by this adhesion layer.
According to above-mentioned conception, described on the other hand this encapsulation base of the present invention, its applied this optical diode is light-emitting diode or laser diode.
The encapsulation base of light-emitting diode of the present invention has not only overcome the problem of conductive layer tomography of the prior art really, and the disqualification rate that produces in the time can also making at the encapsulation optical diode on the overall structure reduces greatly.
Description of drawings
The present invention will obtain more deep understanding by following accompanying drawing and explanation:
Fig. 1 (a)～(g) is the manufacture method step schematic diagram of the base plate for packaging of prior art light-emitting diode.
Fig. 2 improves the LED package pedestal manufacture method step schematic diagram that prior art means deficiency is developed for the present invention.
Fig. 3 (a)～(i) is this optical diode encapsulation base manufacture method schematic flow sheet of the present invention.
This ramp structure schematic diagram that Fig. 4 (a) and 4 (b) have for the place, sidewall boundary of the bottom of this bearing space and this via.
Fig. 5 (a) and 5 (b) are the scolder counter-flow preventing structure generalized section that encapsulation base had of light-emitting diode.
Fig. 6 finishes the schematic diagram of encapsulation for this optical diode to cover crystal type and this encapsulation base.
Wherein, description of reference numerals is as follows:
1 silicon substrate, 10 photoresist layers
11 exposure imaging districts, 12 grooves
13 inclined walls, 14 half perforations
15 guiding electrode holes, 16 insulating barriers
17 conductive layers, 18 sides
19 back sides, 2 silicon substrates
3 optical diodes, 21 bearing spaces
22,23 vias, 24 first insulating layer of silicon oxide
25 reflection layers, 26 second insulating layer of silicon oxide
27 conductive layers, 28 adhesion layers
201 first surfaces, 202 second surfaces
2011,2012 mask layers of making by silicon nitride
2,013 first photoresist layers, 2,014 second photoresist layers
2001,2002,2003 photoresistance patterns
203,204,205 openings
211,40 inclined-planes, 212 inclined-planes
41 have the relief region of a plurality of concavo-convex things
Embodiment
See also Fig. 2, the packaging substrate structure schematic diagram that it is developed for the deficiency of improving the prior art means for the present invention, and this encapsulation base of the present invention is applied in the encapsulation process of optical diode of light-emitting diode (LED) or laser diode (Laser Diode).We can find out clearly that this encapsulation base comprises the silicon substrate 2 with first surface 201 and second surface 202 from figure, bearing space 21 and via 22,23, this silicon substrate 2 high impedance silicon substrate that is 100 lattice direction wherein, and the open top of this bearing space 21 is positioned at the side of these silicon substrate 2 these first surfaces 201, the bottom of this bearing space 21 can be in order to carrying this optical diode 3 as light-emitting diode (LED) or laser diode (Laser Diode), and the bottom opening of this via is positioned at the side of this second surface 202 of this silicon substrate 2, and this via 22,23 top is communicated in the bottom of this bearing space 21, and topmost this via 22 that is characterised in that of this encapsulation base of the present invention, the bottom intersection of 23 sidewall and this bearing space 21 has the structure on an inclined-plane 211 at least.
See also Fig. 3 (a) to Fig. 3 (i), Fig. 3 (a) to Fig. 3 (i) be this optical diode encapsulation base manufacture method schematic flow sheet of the present invention.At first, this first surface 201 in this silicon substrate 2 forms the mask layer of being made by materials such as silicon nitride, silica or metals 2011,2012 (shown in Fig. 3 (a)) respectively with this second surface 202; Shown in Fig. 3 (b), on these mask layers 2011,2012, form first photoresist layer 2013 and second photoresist layer 2014 respectively for another example; Shown in Fig. 3 (c), utilize first mask and second mask (not shown) on these photoresist layers 2013,2014, to define photoresistance pattern 2001,2002,2003 at this; Shown in Fig. 3 (d), according to these photoresistance patterns 2001,2002,2003 these mask layers 2011,2012 are carried out etching and form out 203,204,205; Shown in Fig. 3 (e), this silicon substrate 2 is carried out Wet-type etching, and then form this bearing space 21 and this via 22,23 at these opening 203,204,205 places, and form the structure on this inclined-plane 211 in the bottom intersection of the sidewall of this via 22,23 and this bearing space 21; Shown in Fig. 3 (f), this first surface 201 (surface that comprises this bearing space 21) in this silicon substrate 2 forms first insulating layer of silicon oxide 24 with this second surface 202 (sidewall surfaces that comprises these vias 22,23): shown in Fig. 3 (g), be formed with the reflection layer of being made by aluminium or ag material (aluminium and ag material light reflex rate are very high) 25 on this first insulating layer of silicon oxide 24 of this first surface 201; Shown in Fig. 3 (h), on this reflection layer 25, be formed with second insulating layer of silicon oxide 26; Last as Fig. 3 (i) shown in, at this second insulating layer of silicon oxide 26 and this first insulating layer of silicon oxide 24 (covering this first insulating layer of silicon oxide on the sidewall surfaces of these vias 22,23) just on be formed with the packaging substrate structure of finishing this optical diode as shown in Figure 2 behind the conductive layer of making by TiW/Cu/Ni/Au or Ti/Cu/Ni/Au or Ti/Au/Ni/Au or AlCu/Ni/Au alloy 27.And followingly do detailed description with regard to above-mentioned process step again.
As mentioned above, be usually located at this first surface 201 of this silicon substrate 2 and this bearing space 21 and this via 22 on this second surface 202, the 23rd, simultaneously this first surface 201 of this silicon substrate 2 is carried out etching with this second surface 202 by the mode of this Wet-type etching, thus, just can on this silicon substrate 2, form this bearing space 21 and this via 22,23 and be formed at this via 22, these inclined-plane 211 structures of the bottom intersection of 23 sidewall and this bearing space 21, and when carrying out this Wet-type etching, the present invention utilizes concentration to carry out this Wet-type etching at 20～35 percentage by weights and temperature at Celsius 80～95 potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH) solution of spending, and this potassium hydroxide (KOH) or this tetramethylammonium hydroxide (TMAH) are just solution can be that these bearing spaces 21 (shown in Fig. 3 (e)) of 54.74 degree or 45 degree and the angle theta of top and sidewall are these vias 22 of 54.74 degree or 45 degree according to the properties of crystal lattice of this silicon substrate 2 and then the angle theta that forms between bottom and sidewall respectively at this first surface 201 and this second surface 202,23 (shown in Fig. 3 (e)) and bottom and this via 22 of removing this bearing space 21, the sharp edges of 23 sidewall intersection and form this inclined-plane 211.
And about the making step of above-mentioned encapsulation base, wherein this first insulating layer of silicon oxide 24 forms in the mode of high-temperature oxydation, this reflection layer 25 is formed on this first insulating layer of silicon oxide 24 in the mode of evaporation or sputter (Sputtering), this second insulating layer of silicon oxide 26 is formed on this reflection layer 25 with plasma-enhanced chemical vapor deposition PECVD method or low-temperature atmosphere-pressure chemical vapour deposition technique or low-temp low-pressure boiler tube mode, this conductive layer 27 defines first plating area and second plating area (the via surface is contained in this plating area) with the 3rd mask and the 4th mask (not shown at this) on this second insulating layer of silicon oxide 26 and this first silicon oxide layer 24, and with sputter (Sputtering) add mode that platings (Electroplating) or sputter (Sputtering) add chemical plating (Electroless Plating) in this first plating area and this second plating area this conductive layer 27 of formation on this second insulating layer of silicon oxide 26 and this first insulating layer of silicon oxide 24.
By above-mentioned technical descriptioon, we can find clearly that the topmost feature of the present invention is exactly to be in the manufacturing process of whole encapsulation base, be simultaneously this first surface 201 of this silicon substrate 2 (the high impedance silicon substrates of 100 lattice direction) to be carried out etching with this second surface 202 in the mode of this Wet-type etching, and the solution that carries out this Wet-type etching be condition and range must be in concentration at 20～35 percentage by weights and temperature potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH) solution at 80～95 degree Celsius, so can on this silicon substrate 2, form this bearing space 21 that meets feature of the present invention, this via 22,23 and bottom and this via 22 of removing this bearing space 21, the acute angle of 23 sidewall intersection and form this inclined-plane 211, shown in Fig. 4 (a), because the formation on this inclined-plane 211, make bottom and this via 22 of this bearing space 21, the angle mitigation comparatively of 23 sidewall intersection, thus, when this conductive layer 27 is plated on this via 22, during 23 sidewalls, just can not take place because bottom and this via 22 of this bearing space 21, the acute angle of 23 sidewall intersection and when plating this conductive layer 27, cause tomography, and except in Fig. 4 (a) at this year of space 21 bottom and this via 22,23 sidewall intersection forms outside the inclined-plane 211, also can be as having two inclined-planes 211 among Fig. 4 (b), 212 structure equally also can be finished the above-mentioned function that will reach.
See also Fig. 5 (a) and Fig. 5 (b), the encapsulation base of this light-emitting diode of the present invention, except this potassium hydroxide (KOH) or this tetramethylammonium hydroxide (TMAH) solution that utilizes the certain condition scope carries out bottom and this via 22 of this Wet-type etching to remove this bearing space 21 to this substrate 2, the acute angle of 23 sidewall intersection is to form outside this feature of at least one inclined-plane, if the substrate used in the present invention cheaper general silicon substrate (non-high impedance silicon substrate) that is price then also have the scolder counter-flow preventing structure in these second surface 202 edges of this silicon substrate 2, shown in Fig. 5 (a), this scolder counter-flow preventing structure can be an inclined-plane 40 structures, can this scolder counter-flow preventing structure shown in Fig. 5 (b) be relief region 41 also with a plurality of concavo-convex things, thus, the encapsulation base of this light-emitting diode that made is finished with circuit board (this not shown) when welding, leakage current is higher improperly because of extruding causes to the side of this silicon substrate 2 from these second surface 202 adverse currents of this silicon substrate 2 just can to avoid scolder, and this above-mentioned scolder counter-flow preventing structure is finished with this Wet-type etching.Certainly, if the words of silicon substrate high impedance silicon substrate used in the present invention, because its resistance value is greater than 1000Ohm-cn, so the encapsulation base of this light-emitting diode is when welding with circuit board, can't cause the excessive problem of leakage current, therefore, on this high impedance silicon substrate, just do not need formation this scolder counter-flow preventing structure as shown in Fig. 5 (a) or Fig. 5 (b) in addition.
See also Fig. 6, its for this optical diode to cover crystal type and this encapsulation base is finished the encapsulation schematic diagram.The present invention utilizes the mode of routing and this conductive layer 27 on this silicon substrate 2 to carry out conducting except this optical diode 3 as shown in Figure 2, in addition also can be as shown in Figure 6 on the conductive layer 27 of this first surface 201 of this silicon substrate 2, form the adhesion layer of making by Al/Ti/AuSn or Ti/Au/AuSn alloy (wherein AuSn consist of 80%Au and 20%Sn or 75%Au and 25%Sn) 28, and this optical diode 3 carries out conducting by this adhesion layer 28 with this conductive layer 27, and then finish whole encapsulation process, encapsulate the effect that can reduce these silicon substrate 2 employed areas (because not having the problem of routing) and raising heat radiation and utilize this to cover crystal type.
In sum, the topmost feature of the encapsulation base of this light emitting diode of the present invention is exactly In the process of whole making, be simultaneously to this with etching solution (potassium hydroxide or tetramethylammonium hydroxide) This first surface and this second surface of high impedance silicon substrate carry out Wet-type etching, and because this etching solution Condition is to be limited to concentration at 20～35 percentage by weights and the temperature specific bars at 80～95 degree Celsius In the part scope, therefore, when with this etching solution this silicon substrate being carried out etching, except forming necessary holding Carry outside space and the via, also can form at least in the bottom of bearing space and the sidewall intersection of via The structure on an inclined-plane, this feature just can solve asking of the conductive layer tomography mentioned in the prior art Topic, and since the present invention simultaneously this first surface of this silicon substrate and this second surface are carried out wet type to lose Carve, also technological means commonly used is easy on method step, thus relatively on cost of manufacture also That comes is comparatively cheap, in addition, if this silicon substrate is to use the comparatively cheap general silicon substrate of price (non-The high impedance silicon substrate), then can form in the bottom surface of this silicon substrate (one side that is connected with circuit board) scolder The scolder adverse current that prevents counter-flow preventing structure causes that leakage current is higher improperly, thus, and institute of the present invention The encapsulation base of the light emitting diode of stating has not only overcome deficiency of the prior art really, and ties in integral body The disqualification rate that produces when the encapsulation optical diode is reduced greatly.
The present invention is appointed by those skilled in the art and executes that the craftsman thinks and be to modify the appended right of right neither disengaging as all Require the scope of institute's wish protection.
Claims (13)
1. the encapsulation base manufacture method of an optical diode, this method comprises the following step:
One substrate is provided;
On the first surface of this substrate and second surface, form first mask layer and second mask layer respectively;
Define first opening and second opening on this first mask layer and this second mask layer, the area of this first opening is greater than second opening;
This substrate is carried out Wet-type etching, and then form the bearing space of placing for optical diode and at least two vias respectively, make the top of these vias be communicated to the bottom of this bearing space respectively at this first opening part and this second opening part; And
This substrate is proceeded Wet-type etching, with the sharp edges of the sidewall intersection of the bottom of removing this bearing space and this via and form at least one inclined-plane.
2. the encapsulation base manufacture method of optical diode according to claim 1, wherein this substrate is the high impedance silicon substrate of 100 lattice direction, the high impedance silicon substrate of this 100 lattice direction is at this bearing space that carries out being etched behind this Wet-type etching, angle between its bottom and sidewall is 54.74 or 45 degree, and these vias that etched, angle between its top and sidewall is 54.74 or 45 degree, and this silicon substrate utilizes concentration to carry out Wet-type etching at 20～35 percentage by weights and temperature at the potassium hydroxide or the tetramethyl-ammonium hydroxide solution of 80～95 degree Celsius.
3. the encapsulation base manufacture method of optical diode according to claim 1, wherein the formation method of this first opening and this second opening comprises the following step:
This first surface and this second surface at this substrate form respectively by silicon nitride, silica or metal this first mask layer and this second mask layer;
On this first mask layer and this second mask layer, form first photoresist layer and second photoresist layer respectively;
Utilize first mask and second mask on these photoresist layers, to define the first photoresistance pattern and the second photoresistance pattern; And
According to this first photoresistance pattern and this second photoresistance pattern described first mask layer and second mask layer are carried out etching and form this first opening and this second opening.
4. the encapsulation base manufacture method of optical diode according to claim 1 also comprises the following step:
This first surface and this second surface of this substrate after carrying out Wet-type etching form first insulating layer of silicon oxide;
On this first insulating layer of silicon oxide of this first surface, form reflection layer;
On this reflection layer, form second insulating layer of silicon oxide; And
On this first silicon oxide layer of this second insulating layer of silicon oxide and this second surface, form conductive layer.
5. the encapsulation base manufacture method of optical diode according to claim 4, wherein this first insulating layer of silicon oxide forms in the mode of high-temperature oxydation, this reflection layer is by the very high aluminium of one deck light reflex rate or ag material is made and formed by the mode of evaporation or sputter, and this second insulating layer of silicon oxide forms with plasma-enhanced chemical vapor deposition PECVD method or low-temperature atmosphere-pressure chemical vapour deposition technique or low-temp low-pressure boiler tube mode.
6. the encapsulation base manufacture method of optical diode according to claim 4, wherein this conductive layer is made by TiW/Cu/Ni/Au, Ti/Cu/Ni/Au, Ti/Au/Ni/Au or AlCu/Ni/Au alloy, and its formation method comprises the following step:
Utilize the 3rd mask and the 4th mask on first insulating layer of silicon oxide of this second insulating layer of silicon oxide and this second surface, to define first plating area and second plating area; And
Utilize sputter to add to electroplate or mode that sputter adds chemical plating forms this conductive layer in this first plating area and this second plating area.
7. the encapsulation base manufacture method of optical diode according to claim 1, wherein this second surface is formed with the scolder counter-flow preventing structure of the relief region with an inclined-plane or a plurality of concavo-convex things, and its formation method comprises the following step:
On this second mask layer that forms on this second surface of this substrate, define the 3rd opening;
This substrate is carried out Wet-type etching, and form this scolder counter-flow preventing structure at the 3rd opening part.
8. the encapsulation base manufacture method of optical diode according to claim 1, wherein this optical diode is light-emitting diode or laser diode.
9. an encapsulation base is applied on the optical diode, and this encapsulation base comprises:
Substrate, it has first surface and second surface;
Bearing space, its open top are positioned at this first surface of substrate, and its bottom is in order to carry this optical diode; And
Via, its bottom opening are positioned at this second surface of this substrate, and the top of this via is communicated in the bottom of this bearing space, and the bottom intersection of the sidewall of this via and this bearing space has the structure on an inclined-plane at least.
10. encapsulation base according to claim 9, wherein this substrate is the high impedance silicon substrate of 100 lattice direction, and the bottom of this bearing space and the angle between sidewall are 54.74 degree or 45 degree, and the top of this via and the angle between sidewall are 54.74 degree or 45 degree.
11. encapsulation base according to claim 9, wherein this second surface surrounding edge place of this substrate is formed with an inclined-plane and the scolder counter-flow preventing structure with relief region of a plurality of concavo-convex things.
12. encapsulation base according to claim 9 also comprises:
First insulating layer of silicon oxide, it is formed on this first surface and this second surface of this substrate;
Reflection layer, it is made and is formed on this first insulating layer of silicon oxide of this first surface by aluminium or ag material;
Second insulating layer of silicon oxide, it is formed on this reflection layer; And
Conductive layer, it is made and is formed on this first insulating layer of silicon oxide of this second insulating layer of silicon oxide and this second surface by TiW/Cu/Ni/Au, Ti/Cu/Ni/Au, Ti/Au/Ni/Au or AlCu/Ni/Au alloy.
13. encapsulation base according to claim 12, also comprise adhesion layer, it is made and is formed on the conductive layer of this first surface by Al/Ti/AuSn or Ti/Au/AuSn alloy, so that this optical diode is packaged together to cover brilliant mode and this encapsulation base by this adhesion layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100771847A CN100394623C (en) | 2006-04-27 | 2006-04-27 | Packing substrate structure of optical diode and preparing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100771847A CN100394623C (en) | 2006-04-27 | 2006-04-27 | Packing substrate structure of optical diode and preparing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1851945A CN1851945A (en) | 2006-10-25 |
| CN100394623C true CN100394623C (en) | 2008-06-11 |
Family
ID=37133418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100771847A Expired - Fee Related CN100394623C (en) | 2006-04-27 | 2006-04-27 | Packing substrate structure of optical diode and preparing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100394623C (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI354383B (en) * | 2007-01-30 | 2011-12-11 | Silicon Base Dev Inc | Light diode package structure |
| CN101399305B (en) * | 2007-09-29 | 2012-11-21 | 展晶科技(深圳)有限公司 | Encapsulation construction and manufacturing method for photoelectric element |
| CN101459210A (en) * | 2007-12-14 | 2009-06-17 | 先进开发光电股份有限公司 | Encapsulation structure for photoelectric element and manufacturing process thereof |
| TWI517445B (en) * | 2010-02-12 | 2016-01-11 | 精材科技股份有限公司 | Light-emitting diode package, high-reflection submount for light-emitting diode packaging and fabrication method thereof |
| CN101814572A (en) * | 2010-03-05 | 2010-08-25 | 矽畿科技股份有限公司 | Optical diode packaging structure |
| CN101834260B (en) * | 2010-03-12 | 2012-12-26 | 国立中央大学 | Packaging substrate structure and manufacturing method thereof |
| CN102479890B (en) * | 2010-11-30 | 2014-07-02 | 中芯国际集成电路制造(北京)有限公司 | Forming method of optical platform |
| CN102479889A (en) * | 2010-11-30 | 2012-05-30 | 中芯国际集成电路制造(上海)有限公司 | Method for forming optical platform |
| TWI455380B (en) * | 2011-07-29 | 2014-10-01 | 矽品精密工業股份有限公司 | Light-emitting diode (led) package structure and its packaging method |
| CN104425229A (en) * | 2013-09-10 | 2015-03-18 | 中国科学院微电子研究所 | Fin manufacturing method |
| KR20200032361A (en) * | 2018-09-18 | 2020-03-26 | 삼성전기주식회사 | MEMS device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0945965A (en) * | 1995-07-26 | 1997-02-14 | Nichia Chem Ind Ltd | Ceramic led package and manufacture thereof |
| US6531328B1 (en) * | 2001-10-11 | 2003-03-11 | Solidlite Corporation | Packaging of light-emitting diode |
| CN1630069A (en) * | 2003-12-18 | 2005-06-22 | 株式会社日立制作所 | Package for mounting an optical element and a method of manufacturing the same |
| CN1750283A (en) * | 2004-09-14 | 2006-03-22 | 日立协和工程株式会社 | Submount for light emitting diode and its manufacturing method |
-
2006
- 2006-04-27 CN CNB2006100771847A patent/CN100394623C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0945965A (en) * | 1995-07-26 | 1997-02-14 | Nichia Chem Ind Ltd | Ceramic led package and manufacture thereof |
| US6531328B1 (en) * | 2001-10-11 | 2003-03-11 | Solidlite Corporation | Packaging of light-emitting diode |
| CN1630069A (en) * | 2003-12-18 | 2005-06-22 | 株式会社日立制作所 | Package for mounting an optical element and a method of manufacturing the same |
| CN1750283A (en) * | 2004-09-14 | 2006-03-22 | 日立协和工程株式会社 | Submount for light emitting diode and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1851945A (en) | 2006-10-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100394623C (en) | Packing substrate structure of optical diode and preparing method | |
| US7719099B2 (en) | Package structure for solid-state lighting devices and method of fabricating the same | |
| US8048694B2 (en) | Package base structure and associated manufacturing method | |
| JP4947929B2 (en) | Light emitting diode package and manufacturing process thereof | |
| EP4145543A1 (en) | Light emitting diode | |
| TWI397193B (en) | Light emitting diode chip element with heat dissipation substrate and method for making the same | |
| EP1835550A2 (en) | Package structure for solid-state lighting devices and method of fabricating the same | |
| CN102610709B (en) | Package carrier and method for manufacturing the same | |
| CN105470148A (en) | Forming method for light-emitting device chip package and supporting structure | |
| CN101868866A (en) | Improved LED structure | |
| CN108389951B (en) | A kind of deep ultraviolet LED encapsulation structure and preparation method thereof | |
| CN102610583B (en) | Package carrier and method for manufacturing the same | |
| JP2007258701A (en) | Package structure of light emitting diode, and method for manufacturing same | |
| CN104756267A (en) | Light emitting device, method for manufacturing same, and body having light emitting device mounted thereon | |
| WO2010092042A2 (en) | Silicon-based sub-mount for an opto-electronic device | |
| CN104953006A (en) | Semiconductor light emitting device | |
| CN106981550A (en) | A kind of easily encapsulation easy heat radiation upside-down mounting high voltage LED chip | |
| KR20090010445A (en) | Light emitting device package and method of making the same | |
| FI122622B (en) | Light-emitting semiconductor device and method of manufacture | |
| CN111446343B (en) | Semiconductor light emitting device | |
| KR101578266B1 (en) | Wafer Level Chip Scale Light Emitting Diode Package | |
| CN104795481B (en) | Light emitting diode and preparation method thereof | |
| TWI459595B (en) | Optical semiconductor device and manufacturing method of optical semiconductor device | |
| US9196811B2 (en) | Optical device package having a groove in the metal layer | |
| KR20110105624A (en) | Led module and fabrication method of thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080611 Termination date: 20180427 |