CN100392868C - Thin-film transistor structure - Google Patents
Thin-film transistor structure Download PDFInfo
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- CN100392868C CN100392868C CNB2003101014003A CN200310101400A CN100392868C CN 100392868 C CN100392868 C CN 100392868C CN B2003101014003 A CNB2003101014003 A CN B2003101014003A CN 200310101400 A CN200310101400 A CN 200310101400A CN 100392868 C CN100392868 C CN 100392868C
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Abstract
The present invention discloses a thin film transistor structure which is applied to liquid crystal panel displays with active arrays. The thin film transistor structure comprises a base plate, a source electrode, a drain electrode and a grid electrode. A plurality of intrinsic regions, at least one first doping region and two second doping regions are arranged on the base plate, wherein the first doping region is arranged among the intrinsic regions; the intrinsic regions are connected into a series structure by the first doping region in series; the second doping regions are respectively arranged at both ends of the series structure. The source electrode and the drain electrode are respectively connected with the second doping regions at both of the two ends of the series structure. The grid electrode is used for covering the intrinsic regions, so that the margin part of each intrinsic region is approximately aligned with the margin part of the corresponding grid electrode.
Description
Technical field
The present invention is about a kind of active type matrix liquid crystal flat panel display (Active MatrixLiquid Crystal Display that is applied to, AM-LCD) thin-film transistor structure refers to a kind of thin-film transistor structure with autoregistration inner grid (Self-Align Intra-Gate) especially.
Background technology
Progress day by day along with manufacturing technology, LCD (Liquid Crystal Display, LCD) be a kind of display element that is widely used, and its operation principle mainly is to utilize electric field to change the ordered state of liquid crystal, make the light that passes through liquid crystal produce the phenomenon that route changes, and then reach the display effect that light and shade changes.
LCD (LCD) according to the difference of technology can divide into the passive type array liquid crystal display (Passive Matrix LCD, PM-LCD) and the active type matrix LCD (Active MatrixLCD, AM-LCD).In the time of 1970, passive type array liquid crystal display (PM-LCD) has been applied to wrist-watch and portable computer, but it is relatively poor aspect brightness and visible angle, and reaction speed is slower, therefore is very restricted on using.Yet active type matrix LCD (AM-LCD) then can drive single pixel, and do not influence neighbor, performance is all very good aspect color quality and reaction speed, can be applicable to digital camera, liquid crystal projection apparatus, mobile phone usefulness liquid crystal panel, notebook computer and flat-surface television market, therefore become the main flow in present LCD (LCD) market.
Active type matrix LCD (AM-LCD) mainly can be divided into the LCD of diode structure and transistor arrangement, and Thin Film Transistor-LCD (TFT-LCD) then belongs to the latter.Basically, Thin Film Transistor-LCD (TFT-LCD) is respectively to pixel (pixel) addressing with thin-film transistor, and place the crosspoint that shows ranks as the switch that opens and closes pixel, it can be directly with transistor driving in each pixel, control its voltage, make it reach high contrast, fast reaction and than characteristics such as wide viewing angles, so its image display quality is splendid.
Generally in active type matrix liquid crystal flat panel display (AM-LCD) as the three-terminal element thin-film transistor (TFT) of switch element, according to present development trend, its structure adopts top grid kenel (Top-Gate Type) mostly, P channel thin-film transistor 1 and tool lightly doped drain (Lightly DopedDrain are arranged, LDD) the N channel thin-film transistor 2 of structure, its cross-sectional configuration as shown in Figure 1.The source electrode 12 of P channel thin-film transistor 1 and drain electrode 13 are to inject boron element by ion implantor, the source electrode 22 of N channel thin-film transistor 2 and drain electrode 23 are then injected P elements and are formed, and the leakage current (leakage current) when reducing reverse bias and add a lightly doped drain (LDD) structure 24.In above-mentioned thin-film transistor structure, grid 11,21 materials are molybdenum and tungsten alloy, and the material of grid oxic horizon 14 and insulating barrier 15 is a silicon dioxide, and wiring material is a pure aluminum metal, last whole element then with silicon nitride material as diaphragm 16.In such thin-film transistor structure, the importing of lightly doped drain (LDD) structure 24 is mainly done more hour more solving when element, and the N raceway groove is near breakdown voltage (breakdown voltage), the thermoelectronic effect (hot electron effect) at drain electrode 23 places and impact free phenomenons such as (impact ionization).
Yet in above-mentioned thin-film transistor structure, because must importing twice photomask processing at least, the generation of lightly doped drain (LDD) structure 24 injects to carry out two secondary ions respectively, so will be easy to produce the problem of optical registration deviation (Photo Misalignment), and then influence the image quality of the electrical and LCD of thin-film transistor.Therefore, how to develop a kind of optical registration offset issue that solves, and can provide the thin-film transistor structure of lightly doped drain (LDD) correlation function, make active type matrix liquid crystal flat panel display (AM-LCD) that better image quality (image characteristics) is provided, real is present urgent problem.
Summary of the invention
Main purpose of the present invention is for providing a kind of thin-film transistor structure that is applied to active type matrix liquid crystal flat panel display (AM-LCD), it is by the importing of an inner grid structure (Intra-Gate device), can reach and the suitable electrical level of existing lightly doped drain (LDD) structure, and can with the process integration of P channel thin-film transistor, to form the thin-film transistor structure of tool autoregistration inner grid.
Another object of the present invention is for providing a kind of integrated thin-film transistor structure that is applied to active type matrix LCD (AM-LCD), can omnidistance self-registered technology (Total Self-Alignprocess) to form one, and characteristic in response to element, can shorten the characteristic length (Characteristic length) of each grid of thin-film transistor, and then reach advantages such as increasing pixel aperture ratio and reduction polysilicon surface volume reflection.
For reaching above-mentioned purpose, the invention provides a kind of thin-film transistor structure, it is applied to active type matrix liquid crystal flat panel display (AM-LCD), it comprises: a substrate, have a plurality of intrinsic regions on it, comprise one first doped region and two second doped regions at least, wherein first doped region is arranged between a plurality of intrinsic regions, and a plurality of intrinsic regions form a string binding structure by first doped region polyphone, and second doped region is arranged at the two ends of series arrangement respectively and has the doping content different with first doped region; An one source pole and a drain electrode, it is linked to second doped region at series arrangement two ends respectively; And at least one grid, it covers a plurality of intrinsic regions, makes the marginal portion of each intrinsic region and the marginal portion rough alignment of corresponding grid, and the top that the grid in the thin-film transistor structure is all avoided first doped region forms.
According to above-mentioned conception, wherein substrate is the substrate with a polysilicon layer, and intrinsic region, first doped region and second doped region are arranged in the polysilicon layer.First doped region of the present invention in addition and second doped region constitute by the P elements that injects variable concentrations respectively, and wherein the doping content of second doped region is greater than the doping content of first doped region.Grid can be made by molybdenum and tungsten alloy (MoW), chromium (Cr), aluminium (Al), molybdenum (Mo), titanium (Ti), tantalum (Ta) or copper (Cu) metal again.In addition, more comprise a grid oxic horizon between intrinsic region and its corresponding grid, wherein grid oxic horizon is made of silicon dioxide.
According to above-mentioned conception, grid of the present invention constitutes a ∏ type, L type, I type or E type and distributes.
For reaching above-mentioned purpose, the present invention more provides a kind of thin-film transistor structure, it comprises: a substrate, have N intrinsic region, N-1 first doped region, two second doped regions on it, wherein N-1 first doped region is crisscross arranged between N intrinsic region, 2 second doped regions then are arranged at the outside of the 1st intrinsic region and N intrinsic region respectively and have the doping content different with first doped region, and wherein N is an integer, and N 〉=2; An one source pole and a drain electrode are linked to two second doped regions respectively; And at least one grid, it covers N intrinsic region, and the marginal portion of each active region is aimed at haply with the marginal portion of corresponding grid, and the top that the grid in the thin-film transistor structure is all avoided first doped region forms.
The present invention must make to more clearly understand the present invention by following accompanying drawing and embodiment explanation.
Description of drawings
Fig. 1 is for being applied in the active type matrix liquid crystal flat panel display (AM-LCD) schematic cross-section as the three-terminal element thin-film transistor of switch element at present;
Fig. 2 (a)-(b) is respectively the overlooking and profile of first preferred embodiment of thin-film transistor of the present invention;
Fig. 3 (a)-(b) is the schematic diagram of second preferred embodiment of thin-film transistor of the present invention, wherein Fig. 3 (a) discloses the distribution scenario of intrinsic region, first doped region and second doped region on many silicon layers, and Fig. 3 (b) then shows the distribution scenario of grid with respect to intrinsic region, first doped region and second doped region;
Fig. 4 (a)-(b) is the 3rd a preferred embodiment schematic diagram of thin-film transistor of the present invention, wherein Fig. 4 (a) discloses the distribution scenario of active region, first doped region and second doped region on many silicon layers, and Fig. 4 (b) then shows the distribution scenario of grid with respect to intrinsic region, first doped region and second doped region;
Fig. 5 (a)-(b) is the 4th a preferred embodiment schematic diagram of thin-film transistor of the present invention, wherein Fig. 5 (a) discloses the distribution scenario of intrinsic region, first doped region and second doped region on many silicon layers, and Fig. 5 (b) then shows the distribution scenario of grid with respect to intrinsic region, first doped region and second doped region; And
Fig. 6 (a)-(b) is the 5th a preferred embodiment schematic diagram of thin-film transistor of the present invention, wherein Fig. 6 (a) discloses the distribution scenario of intrinsic region, first doped region and second doped region on many silicon layers, and Fig. 6 (b) then shows the distribution scenario of grid with respect to intrinsic region, first doped region and second doped region.
Description of reference numerals in the accompanying drawing is as follows:
1:P channel thin-film transistor 2:N channel thin-film transistor
11: grid 12: source electrode
13: drain electrode 14: grid oxic horizon
15: insulating barrier 16: diaphragm
21: grid 22: source electrode
23: drain electrode 24: lightly doped drain LDD structure
31: substrate 41: grid
51: source electrode 52: drain electrode
311: 312: the first doped regions of intrinsic region
Doped region 411 in 313: the second: grid oxic horizon
Embodiment
The present invention is a kind of thin-film transistor structure that is applied to active type matrix liquid crystal flat panel display (AM-LCD), below will further specify the technology of the present invention with embodiment, but the thin-film transistor structure that can use the technology of the present invention is not limited to the embodiment that carried, the thin-film transistor structure of any suitable the technology of the present invention all can be incorporated reference at this.
See also Fig. 2, it is applied to the first preferred embodiment schematic diagram of the thin-film transistor structure of active type matrix liquid crystal flat panel display (AM-LCD) for the present invention, wherein Fig. 2 (a) is the vertical view of thin-film transistor structure, and Fig. 2 (b) then is the sectional view of thin-film transistor structure.As Fig. 2 (a) and (b), thin-film transistor structure of the present invention comprises a substrate 31, have a plurality of intrinsic regions (IntrinsicArea) 311 on it, comprise one first doped region 312 (can be n doped region (n-doping area)) and two second doped regions 313 at least, wherein a plurality of intrinsic regions 311 are contacted by first doped region 312, that is first doped region 312 between a plurality of intrinsic regions 311, and form a string binding structure with a plurality of intrinsic regions 311.
Please consult Fig. 2 (a) and (b) again, two second doped regions 313 are connected to the two ends of series arrangement.In addition, thin-film transistor structure more comprises an one source pole 51 and a drain electrode 52, and it is linked to second doped region 313 at series arrangement two ends respectively.Except that source electrode 51 and drain electrode 52, thin-film transistor structure more comprises at least one grid 41, and it covers these a plurality of intrinsic regions 311, and makes the marginal portion of each intrinsic region 311 aim at (align) haply with the marginal portion of corresponding grid 41.
In said structure, substrate 31 is the substrate of tool polysilicon layer, and intrinsic region 311, first doped region 312 and second doped region 313 etc. are arranged in the polysilicon layer.Other first doped region 312 and second doped region 313 constitute by the P elements that injects variable concentrations respectively, and wherein the doping content of second doped region 313 is greater than the doping content of first doped region 312.Grid 41 is made by molybdenum and tungsten alloy (MoW), chromium (Cr), aluminium (Al), molybdenum (Mo), titanium (Ti), tantalum (Ta) or copper (Cu) metal again.In addition, intrinsic region 311 and its 41 of corresponding grid more comprise a grid oxic horizon 411, and wherein this grid oxic horizon 411 is constituted good with silicon dioxide.
See also Fig. 3 (a) and (b), it is for the second preferred embodiment schematic diagram of thin-film transistor of the present invention, wherein Fig. 3 (a) discloses more than one the distribution scenario of intrinsic region, first doped region and second doped region in the silicon layer, and Fig. 3 (b) then shows the distribution scenario of grid with respect to intrinsic region, first doped region and second doped region.Shown in Fig. 3 (a), be different from intrinsic region that Fig. 2 discloses, the embodiment that first doped region and second doped region are arranged in a linear, intrinsic region 311 in the present embodiment, first doped region 312 and second doped region 313 are to be similar to down " L " shape arrange, that is first doped region 312 have two parts, these two parts are with the angle arrangement of about 90 degree basically, a plurality of intrinsic regions 311 then are connected with the two ends of first doped region 312 respectively, 313 intrinsic regions 311 with two ends of 2 second doped regions are connected, and source electrode and drain electrode (not shown) then are connected with second doped region 313 at two ends respectively in addition.
See also Fig. 3 (b), in the present embodiment, grid 41 structures are " L " the type arrangement, and cover a plurality of intrinsic regions 311, make the marginal portion of each intrinsic region 311 align (align) basically with the marginal portion of corresponding grid 41.First doped region 312 and second doped region 313 can constitute by the P elements that injects variable concentrations, and wherein the doping content of second doped region 313 is greater than the doping content of first doped region 312.Grid 41 also can be made by molybdenum and tungsten alloy (MoW), chromium (Cr), aluminium (Al), molybdenum (Mo), titanium (Ti), tantalum (Ta) or copper (Cu) metal again.
Similarly, in Fig. 4 (a) and in the 3rd preferred embodiment (b), intrinsic region 311, first doped region 312 and second doped region, 313 integral body are to be similar to " U " the type arrangement, that is first doped region 312 present with " U " type, a plurality of intrinsic regions 311 then are linked to the two ends of first doped region 312 respectively, 313 of two second doped regions are connected with the intrinsic region 311 at two ends respectively, and source electrode and drain electrode (not shown) then are connected with second doped region 313 at two ends respectively in addition.Grid 41 structures are the I type arranges, and covers a plurality of intrinsic regions 311, makes the marginal portion of each intrinsic region 311 align (align) with the marginal portion of corresponding grid 41.
Fig. 5 and Fig. 6 then disclose the 4th and the 5th preferred embodiment of thin-film transistor of the present invention respectively.In Fig. 5 and each embodiment shown in Figure 6, thin-film transistor structure all comprises a substrate 31, have N intrinsic region 311, N-1 first doped region 312, two second doped regions 313 on it, wherein N-1 first doped region 312 is alternately arranged between N the intrinsic region 311, two second doped regions 313 then are arranged at the outside of the 1st intrinsic region 311 and N intrinsic region 311 respectively, and wherein N is an integer and N 〉=2.In addition, thin-film transistor more comprises an one source pole and a drain electrode (not shown), it is linked to 2 second doped regions 313 respectively, and at least one grid 41, it covers this N intrinsic region 311, and the marginal portion of each intrinsic region 313 is aligned basically, with the marginal portion of corresponding grid 41 to form the thin-film transistor structure of tool autoregistration inner grid.
In Fig. 5 (a) and (b) illustrated embodiment, N equals 3, that is thin-film transistor structure has 311, two first doped regions 312 of three intrinsic regions and two second doped regions 313.Intrinsic region 311, first doped region 312 and second doped region, 313 integral body are arranged with " S " type, that is two first doped regions 312 are staggered between three intrinsic regions 311, and become the series arrangement of one " S " type.313 of two second doped regions are connected with the intrinsic region 311 at two ends respectively.Source electrode and drain electrode (not shown) then are connected with second doped region 313 respectively in addition.Grid 41 structures are " I " the type arrangement, and cover three intrinsic regions 311, make the marginal portion of each intrinsic region 311 and the marginal portion substantial registration (align) of corresponding grid 41.
Similarly, in Fig. 6 (a) and (b) illustrated embodiment, N also equals 3, that is thin-film transistor structure has 311, two first doped regions 312 of three intrinsic regions and two second doped regions 313.Intrinsic region 311, first doped region 312 and second doped region 313 be with arc shooting, that is two first doped regions 312 are staggered between three intrinsic regions 311, and 313 of two second doped regions are connected with the intrinsic region at two ends respectively.Source electrode and drain electrode (not shown) then are connected with second doped region 313 respectively in addition.Grid 41 structures are " E " type arranges, and covers three intrinsic regions 311, makes the marginal portion of each intrinsic region 311 aim at (align) haply with the marginal portion of corresponding grid 41.
In the above-described embodiments, its main principle is all similar, and its difference only is number, the arrangement of intrinsic region 311, first doped region 312 and second doped region 313 and distributes different.Because the number of intrinsic region 311, first doped region 312 and second doped region 313, arrange with distribution on difference also cause among each embodiment the grid 41 that aligns (align) with intrinsic region 311 to present dissimilar sample attitudes, and grid 41 is presented respectively with ∏ type, L type, I type or E type mode.Certainly in practical application, grid structure of the present invention can be done modulation flexibly in response to the distribution in each zone of polysilicon layer, and is not subject to the enforcement aspect of previous embodiment.
In sum, the invention provides a kind of thin-film transistor structure that is applied to the driving liquid crystal flat panel display of active type matrix (AM-LCD), it is by the importing of an inner grid structure (Intra-Gate), can reach the electrical level suitable with existing lightly doped drain (LDD), and can with the process integration of P channel thin-film transistor.The thin transistorized NMOS of N raceway groove film can form a self-registered technology (Self-Align process) after importing inner grid structure (Intra-Gate device).When redesign pixel and drive circuit, oneself is a self-registered technology for the thin transistorized PMOS of P raceway groove film, both can be integrated into an omnidistance self-registered technology (Total Self-Align process), and characteristic in response to element, can shorten characteristic length (characteristic length) D (seeing also Fig. 2) of each grid of thin-film transistor, and then reach advantages such as increasing pixel aperture ratio and reduction polysilicon surface volume reflection to label " D " shown in Figure 6.
And according to the inventor's experimental result, characteristic length D can change to some extent along with different grids 41 aspects, for example when grid 41 aspects are ∏ type or E type (shown in Fig. 2 (a), Fig. 6 (b)), its characteristic length D is less than 7 μ m, and when grid 41 aspects are L type or I type (shown in Fig. 3 (b), Fig. 4 (b), Fig. 5 (b)), its characteristic length D is less than 5 μ m, no matter but grid 41 is to present which kind of combination aspect, its characteristic length D is less than existing LDD aspect.
Simultaneously, in the above-described embodiments, because the polysilicon that is installed with for intrinsic region 311, first doped region 312 and second doped region 313 is intrinsic polysilicon (Intrinsic poly), has high value, so the voltage (Vcom) of storage capacitors (Cst) to connect high potential (＞8V), increase the electric charge that storage capacitors (Cst) can store, get so that Cst/Clc＞1.
Can appoint by those skilled in the art even if the present invention has been described in detail by the above embodiments and to execute that the craftsman thinks and be to modify as all, but neither disengaging such as the claimed scope of claims.
Claims (8)
1. thin-film transistor structure, it is applied to the active type matrix liquid crystal flat panel display, and it comprises:
One substrate, have a plurality of intrinsic regions, at least one first doped region and two second doped regions on it, wherein this first doped region is formed between these a plurality of intrinsic regions, and these a plurality of intrinsic regions form a string binding structure by this first doped region polyphone, and this second doped region is arranged at the two ends of this series arrangement respectively and has the doping content different with this first doped region;
An one source pole and a drain electrode, it is linked to this second doped region at these series arrangement two ends respectively; And
At least one grid, it covers these a plurality of intrinsic regions, and the marginal portion of each intrinsic region is aimed at the marginal portion of corresponding grid,
Wherein the grid in this thin-film transistor structure is all avoided the top formation of this first doped region, and this grid constitutes a L type, I type or E type and distributes.
2. thin-film transistor structure as claimed in claim 1, wherein, this substrate is the substrate with a polysilicon layer, and this intrinsic region, this first doped region and this second doped region are arranged at this polysilicon layer.
3. thin-film transistor structure as claimed in claim 1, wherein, this first doped region and this second doped region constitute by the P elements that injects variable concentrations respectively, and the doping content of this second doped region is greater than the doping content of this first doped region.
4. thin-film transistor as claimed in claim 1 wherein, also comprises a grid oxic horizon between this intrinsic region and corresponding this grid.
5. thin-film transistor structure as claimed in claim 1, wherein, this grid has a characteristic length, and when this grid constituted this E type, this characteristic length was less than 7 μ m, and when this grid constituted this L type and this I type, this characteristic length was less than 5 μ m.
6. thin-film transistor structure, it comprises:
One substrate, have N intrinsic region, N-1 first doped region, two second doped regions on it, wherein this N-1 first doped region is crisscross arranged between this N intrinsic region, this second doped region then is arranged at the outside of the 1st intrinsic region and this N intrinsic region respectively and has the doping content different with this first doped region, wherein N is an integer, and N 〉=2;
An one source pole and a drain electrode are linked to this second doped region respectively; And
At least one grid, it covers this N intrinsic region, and the marginal portion of each intrinsic region is aimed at the marginal portion of corresponding grid,
Wherein the grid in this thin-film transistor structure is all avoided the top formation of this first doped region, and this grid constitutes a L type, I type or E type and distributes.
7. thin-film transistor structure as claimed in claim 6, wherein, this first doped region and this second doped region constitute by the P elements that injects variable concentrations respectively, and the doping content of this second doped region is greater than the doping content of this first doped region.
8. thin-film transistor structure as claimed in claim 6, wherein, this grid has a characteristic length, and when this grid constituted this E type, this characteristic length was less than 7 μ m, and when this grid constituted this L type and this I type, this characteristic length was less than 5 μ m.
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| CNB2003101014003A CN100392868C (en) | 2003-10-17 | 2003-10-17 | Thin-film transistor structure |
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| CNB2003101014003A CN100392868C (en) | 2003-10-17 | 2003-10-17 | Thin-film transistor structure |
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| CN100392868C true CN100392868C (en) | 2008-06-04 |
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| CN109360857A (en) * | 2018-08-15 | 2019-02-19 | 南昌工程学院 | A kind of degradable self-supporting film transistor device and preparation method thereof |
Citations (4)
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|---|---|---|---|---|
| US4907041A (en) * | 1988-09-16 | 1990-03-06 | Xerox Corporation | Intra-gate offset high voltage thin film transistor with misalignment immunity |
| JPH06104438A (en) * | 1992-09-22 | 1994-04-15 | Casio Comput Co Ltd | Film transistor |
| US6034748A (en) * | 1997-04-08 | 2000-03-07 | Matsushita Electric Industrial Co., Ltd. | Thin film transistor, manufacturing method therefor and liquid crystal display unit using the same |
| US20030194839A1 (en) * | 2002-04-15 | 2003-10-16 | Lg.Philips Lcd Co. Ltd. | Polycrystalline silicon thin film transistor and method for fabricating the same |
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2003
- 2003-10-17 CN CNB2003101014003A patent/CN100392868C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4907041A (en) * | 1988-09-16 | 1990-03-06 | Xerox Corporation | Intra-gate offset high voltage thin film transistor with misalignment immunity |
| JPH06104438A (en) * | 1992-09-22 | 1994-04-15 | Casio Comput Co Ltd | Film transistor |
| US6034748A (en) * | 1997-04-08 | 2000-03-07 | Matsushita Electric Industrial Co., Ltd. | Thin film transistor, manufacturing method therefor and liquid crystal display unit using the same |
| US20030194839A1 (en) * | 2002-04-15 | 2003-10-16 | Lg.Philips Lcd Co. Ltd. | Polycrystalline silicon thin film transistor and method for fabricating the same |
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