CN100360945C - Electric voltage observation circuit - Google Patents
Electric voltage observation circuit Download PDFInfo
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- CN100360945C CN100360945C CNB2005100646950A CN200510064695A CN100360945C CN 100360945 C CN100360945 C CN 100360945C CN B2005100646950 A CNB2005100646950 A CN B2005100646950A CN 200510064695 A CN200510064695 A CN 200510064695A CN 100360945 C CN100360945 C CN 100360945C
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Abstract
The present invention relates to a voltage monitoring circuit, particularly to a circuit which is integrated in a chip and is capable of monitoring the voltage quality of the chip. The present invention is mainly characterized in that a first wave conditioner receives a voltage signal of a voltage source to be detected; the voltage signal is processed into a logic signal and output to a first logic level translator; the voltage signal is converted into a first digital signal by being processed and recorded by a buffer; a management system can read the content of the buffer by a bus, and thereby, the condition that the voltage source to be detected has high voltage surges or not is judged. Similarly, an inverter is connected in series between a second wave conditioner and a second logic level translator so as to monitor whether the voltage source to be detected has low voltage surges or not, and thereby, the combination of the circuit can be simply simulated so as to achieve the purpose for monitoring the voltage quality in the chip.
Description
Technical field
The present invention relates to a kind of electric voltage observation circuit, relate in particular to a kind of circuit that is integrated in the chip and monitors its voltage quality, the combination of available simple and easy mimic channel reaches the purpose of voltage quality in the chip monitoring.
Background technology
Along with the fierceness of electronics and information industry competition, many electronic products promote the speed of its calculation process invariably to obtain consumer's favor.Yet, chip arithmetic speed in the electronic product is accelerated its operation frequency and also must be accelerated thereupon, cause its operating voltage to diminish, so just, cause chip that the susceptibility of the variation of operating voltage is also become big relatively, that is, the instability of the operating voltage of chip action is provided, and also is to cause system to work as the one of the main reasons of machine sometimes.Yet, the instability of operating voltage in a flash just sometimes, therefore can't wait system when machine, just to go to measure, so must monitor the degree of stability of this operating voltage and record in addition at any time, stable operating voltage whether factor can be detached the system of sening as an envoy in all factors of machine, so that help the research staff to put the reason of system in order when machine.
General existing voltage detection circuit, with reference to Fig. 1, it mainly is made up of a comparer 11 and a Zener diode 12, positive input terminal at this comparer 11 is connected with one first resistance 13 and one second resistance 14, and then be connected with one the 3rd resistance 15 and this Zener diode 12 in its negative input end, and the anode of this Zener diode 12 links to each other with the other end of this second resistance 14 and direct ground connection, and, the output terminal of this comparer 11 is serially connected with one the 4th resistance 16 and a light emitting diode 17, and the anode of this light emitting diode 17 is connected with the other end of this first resistance 13 and the 3rd resistance 15, and connects a voltage source 18 to be measured simultaneously.So just, the bias effect that can be caused by this first resistance 13 and this second resistance, 14 assembly, and the effect of arrange in pairs or groups this comparer 11 and this Zener diode 12, whether luminous make the user can pass through to observe this light emitting diode 17, judges that this voltage source 18 to be measured has or not the situation of abrupt voltage wave to take place and reach detecting.
Though above-mentioned voltage detection circuit is very simple and easy, but, if it will be integrated in the chip, usually this light emitting diode 17 must be arranged at the casing outside, so that the user can directly visual this light emitting diode 17 is had or not luminously, judge that whereby the situation that has or not abrupt voltage wave takes place, yet, such circuit design just must additionally be considered the laying of circuit-line, also can increase the cost that it makes volume production.
And, this light emitting diode 17 only at that moment can be shinny what have that abrupt voltage wave takes place, and time point one mistake that takes place along with abrupt voltage wave, this light emitting diode 17 is just no longer shinny, therefore, the user must be careful at any time this light emitting diode 17 have or not luminous, luminous if the user does not really notice that at that time point that abrupt voltage wave takes place light emitting diode 17 has or not, take place just can't judge the situation that had before had or not voltage instability.Therefore, just can't get rid of voltage instability and cause system to work as the factor of machine.
Summary of the invention
For this reason, how at the existing shortcoming of above-mentioned existing voltage detection circuit, to design a kind of circuit that is integrated in the chip and monitors its voltage, available easy mimic channel reaches the purpose of voltage quality in the chip monitoring, and this is invention emphasis of the present invention.
Fundamental purpose of the present invention is to provide a kind of electric voltage observation circuit, the mainly circuit assembly by a whole ripple device and a logic level translator, and directly it being integrated in the one chip, and can reach the purpose of the operating voltage quality in the direct chip monitoring.
Secondary objective of the present invention is to provide a kind of electric voltage observation circuit, can connect a buffer by a bus by a management system, and can read the voltage quality record in it, puts the correlative factor of system when machine in order in order to the research staff.
Another purpose of the present invention is to provide a kind of electric voltage observation circuit, and the digital signal record that a logic level translator can be exported and can effectively write down voltage quality in the chip in a buffer, and then reaches the purpose of monitoring at any time.
For achieving the above object, the invention provides a kind of electric voltage observation circuit, it is mainly constructed and comprises: at least one whole ripple device, the input end of each whole ripple device can receive a voltage signal that is transmitted by a voltage source to be measured, and the upper voltage limit of setting according to described whole ripple device and lower voltage limit are to described voltage signal comparison process and export a logical signal by the output terminal of whole ripple device in addition; And at least one logic level translator, each logic level translator is equipped with one and sets end, an output terminal and a reset terminal, receive its logical signal that transmitted of corresponding whole ripple device, and treatment conversion and can export a digital signal in addition by the one output terminal.
Description of drawings
Figure 1 shows that the synoptic diagram that is electrically connected of prior art voltage detection circuit;
Figure 2 shows that the synoptic diagram that is electrically connected of one embodiment of the present invention;
Fig. 3 A is depicted as the electrical specification synoptic diagram of the second whole ripple device;
Fig. 3 B is depicted as the electrical specification synoptic diagram into the present invention's first whole ripple device;
Be respectively the sequential chart of voltage source to be measured and each logic level transition device shown in Fig. 4 A to Fig. 4 C.
Wherein, Reference numeral
11 comparers, 12 Zener diodes
13 first resistance, 14 second resistance
15 the 3rd resistance 16 the 4th resistance
17 light emitting diodes, 18 voltage sources to be measured
21 first whole ripple device 211 capacitors
22 first logic level translators, 221 phase inverters
222 first digital signals, 23 first voltage adjusting devices
231 first dynamic resistances, 232 second dynamic resistances
24 second whole ripple device 25 second logic level translators
252 second digital signals, 251 phase inverters
26 second voltage adjusting devices 261 the 3rd dynamic resistance
262 the 4th dynamic resistances, 27 voltage sources to be measured
271 voltage signals, 28 buffers
29 management systems, 291 System Management Buss
Embodiment
For feature of the present invention, structure and the function that realized are further understood and understanding, the preferred embodiment of the invention is described in detail below in conjunction with accompanying drawing:
At first, with reference to Fig. 2, be the synoptic diagram that is electrically connected of one embodiment of the present invention.As shown in the figure, it is mainly constructed and comprises one first whole ripple device 21, one second whole ripple device 24, one first logic level translator 22 and one second logic level translator 25.Wherein, input end of this first whole ripple device 21 can connect a voltage source 27 to be measured and its output terminal can connect a setting end S1 who is arranged at this first logic level translator 22, and the output terminal of first logic level translator 22 can be connected to a buffer 28.The user can connect this buffer 28 through a System Management Bus (SM Bus) 291 or ISA (Industry StandardArchitecture) bus by a management system 29, by reading the voltage monitoring data that write down in the buffer 28 like this.
The input end of the second whole ripple device 24 also can be connected to this voltage source 27 to be measured,, the output terminal of this second whole ripple device 24 then is to connect after the phase inverter 251, is connected to the setting end S2 of this second logic level translator 25 again by this phase inverter 251.
This first logic level translator 22 and this second logic level translator 25 are respectively equipped with a reset terminal (R1, R2), and, the output terminal of this first whole ripple device 21 can connect the reset terminal R1 of this first logic level translator 22 through a phase inverter 221, and the reset terminal R2 of this second logic level translator 25 then directly connects the output terminal of this second whole ripple device 24.
In addition, can between this voltage source 27 to be measured and each whole ripple device 21,24, be respectively equipped with one first voltage adjusting device 23 and one second voltage adjusting device 26.That is, the input end of first voltage adjusting device 23 is connected this voltage source 27 to be measured, and its output terminal connects the input end of this first whole ripple device 21, and the input end of this second voltage adjusting device 26 connects this voltage source 27 to be measured, and its output terminal connects the input end of this second whole ripple device 24.Wherein, this first voltage adjusting device 23 includes one first dynamic resistance 231 and one second dynamic resistance 232, and this second voltage adjusting device 26 then includes one the 3rd dynamic resistance 261 and one the 4th dynamic resistance 262.Certainly, the suitably assembly of resistance value of each dynamic resistance in each voltage adjusting device 23,26, and can linearly adjust the magnitude of voltage of this voltage source 27 to be measured to suitable voltage level.
In an embodiment of the present invention, this first logic level translator 22 and this second logic level translator 25 can be implemented with a rest-set flip-flop (RS Latch) respectively.The aforesaid first whole ripple device 21 and the second whole ripple device 24 then can be implemented with a schmitt trigger (Schmitt trigger) respectively.
With reference to Fig. 3 A and Fig. 3 B be respectively embodiment illustrated in fig. 2 in the electrical specification synoptic diagram of each whole ripple device 21,24.As shown in the figure, when input voltage Vi is higher than upper voltage limit V2, the V4 of each whole ripple device 21,24, whole ripple device 21,24 is exported the voltage level of noble potential H1, H2 respectively, and when input voltage Vi was lower than the lower voltage limit of each whole ripple device 21,24, then whole ripple device 21,24 was exported the voltage level of electronegative potential L1, L2 respectively.
With reference to Fig. 4 A to Fig. 4 C, be respectively the output timing diagram of voltage source to be measured and each logic level transition device.Wherein, the voltage signal 271 of this voltage source 27 to be measured is shown in Fig. 4 A, and when this voltage signal 271 has a too high abrupt voltage wave to take place in very first time district t1, this voltage signal 271 is when rising to a point, just can cross over the upper voltage limit V2 of this first whole ripple device 21, cause it to export the voltage level of a noble potential H1.When voltage signal 271 drops to the b point, just reach the lower voltage limit V1 of this first whole ripple device 21, make this first whole ripple device 21 export the voltage level of an electronegative potential L1.
As the first whole ripple device 21 output noble potential H1 during to the setting end S1 of this first logic level translator 22, just export the voltage level of a noble potential HQ1 after the conversion of wherethrough reason by its output terminal, shown in Fig. 4 B.Reset terminal R1 when this first whole ripple device 21 is exported electronegative potential L1 and transfer to this first logic level translator 22 after phase inverter 221 effects then can make it export the voltage level of an electronegative potential LQ1.Like this, just can intercept too high abrupt voltage wave in this voltage signal 271 effectively, and real-time operation handles and convert one first digital signal 222 to, and be recorded in this buffer 28.The purpose that intention collocation by this simple circuit assembly and design not only can reach continuous monitoring by the setting of this phase inverter 22 1, more can see through this System Management Bus 291 and this first digital signal 222 is read out in buffer 28, and then can effectively judge and monitor this voltage source 27 to be measured and have or not too high abrupt voltage wave to take place by this management system 29.
In like manner, when this voltage signal 271 had a low excessively abrupt voltage wave to take place in the second time district t2, its voltage signal just can be crossed over the lower voltage limit V3 of this second whole ripple device 24 when dropping to the c point, cause it to export the voltage level of an electronegative potential L2; When voltage signal 271 gos up to the d point, just reach the upper voltage limit V4 of this second whole ripple device 24, make this second whole ripple device 24 export the voltage level of a noble potential H2.
After this second whole ripple device 24 sees through these phase inverter 251 change voltage levels with electronegative potential L2, export the setting end S2 of this second logic level translator 25 again to, and just export the voltage level of a noble potential HQ2 after the wherethrough reason conversion by its output terminal, shown in Fig. 4 C; As the reset terminal R2 of these second whole ripple device 24 output noble potential H2, just can make it export the voltage level of an electronegative potential LQ2 to this second logic level translator 25.Like this, just can intercept low excessively abrupt voltage wave in this voltage signal 271 effectively, and real-time operation handles and convert one second digital signal 252 to, and be recorded in this buffer 28.Like this, just can see through this System Management Bus 291 and this second digital signal 252 is read out in buffer 28, and then can effectively judge and monitor this voltage source 27 to be measured and had or not low abrupt voltage wave to take place by this management system 29.Like this, just can reach the purpose of the voltage quality of this voltage source to be measured of continuous monitoring, and help the research staff to put the correlative factor of system in order when machine.
At last, with reference to Fig. 2, wherein an operating voltage input end Vcc of this first whole ripple device 21 and this second whole ripple device 25 can connect this voltage source 27 to be measured respectively.Certainly, also can be connected in series a capacitor 211 respectively between this voltage source 27 to be measured and the first whole ripple device 21 or the second whole ripple device 24, like this, this first whole ripple device 21 or this second whole ripple device 24 just can effectively be avoided the generation of voltage level-shift phenomenon, and then can promote the accuracy of its voltage quality monitoring effect.In addition, this first dynamic resistance 231, this second dynamic resistance 232, the 3rd dynamic resistance 261 or the 4th dynamic resistance 262 can be implemented with the form of CMOS electronic package respectively.Like this, just, can entire circuit be integrated in the chip by advanced now manufacture of semiconductor technology.
In sum, should know to the present invention relates to a kind of electric voltage observation circuit, relate in particular to a kind of circuit that is integrated in the chip and monitors its voltage quality, the combination of available simple and easy mimic channel realizes the purpose of voltage quality in the chip monitoring.
The above, it only is a preferred embodiment of the present invention, be not to be used for limiting scope of the invention process, promptly all equivalences of being done according to the described shape of the present patent application claim, structure, feature and spirit change and modify, and all should be included in the claim of the present invention.
Claims (15)
1. an electric voltage observation circuit is characterized in that, this electric voltage observation circuit comprises:
At least one whole ripple device, the input end of each whole ripple device can receive a voltage signal that is transmitted by a voltage source to be measured, and the upper voltage limit of setting according to described whole ripple device and lower voltage limit are to described voltage signal comparison process in addition, and export the logical signal of a correspondence by the output terminal of described whole ripple device, wherein, when described voltage signal is higher than described upper voltage limit, the logical signal of described whole ripple device output noble potential, when described voltage signal is lower than described lower voltage limit, the logical signal of described whole ripple device output electronegative potential; And
At least one logic level translator, each logic level translator is equipped with one and sets end, an output terminal and a reset terminal, and each logic level translator receives the described logical signal of corresponding whole ripple device output, in addition a digital signal is handled and be converted to logic level transition, and by described output terminal output;
Wherein, the output terminal of described whole ripple device is connected in this setting end, connects this reset terminal by a phase inverter in addition.
2. electric voltage observation circuit according to claim 1, it is characterized in that, this electric voltage observation circuit further includes a management system and a buffer that is connected with the output terminal of each logic level translator, this buffer is used for writing down the digital signal that each logic level translator produces, and this management system reads the digital signal that is stored in this buffer through a bus.
3. electric voltage observation circuit according to claim 1, it is characterized in that, this electric voltage observation circuit further includes at least one voltage adjusting device, the input end of each voltage adjusting device connects this voltage source to be measured, and the output terminal of each voltage adjusting device connect its input end of corresponding whole ripple device.
4. electric voltage observation circuit according to claim 3, it is characterized in that, described each voltage adjusting device includes one first dynamic resistance and one second dynamic resistance of serial connection respectively, and this first dynamic resistance and this second dynamic resistance are respectively a CMOS electronic package.
5. electric voltage observation circuit according to claim 1 is characterized in that, described whole ripple device is provided with an operating voltage input end, is connected to this voltage source to be measured.
6. electric voltage observation circuit according to claim 5 is characterized in that, still is provided with a capacitor between described operating voltage input end and this voltage source to be measured.
7. electric voltage observation circuit according to claim 1 is characterized in that, described whole ripple device is a schmitt trigger.
8. electric voltage observation circuit according to claim 1 is characterized in that, described logic level translator is a rest-set flip-flop.
9. electric voltage observation circuit according to claim 2 is characterized in that, described bus is one of them of a System Management Bus and an isa bus.
10. an electric voltage observation circuit is characterized in that, this electric voltage observation circuit comprises:
At least one whole ripple device, the input end of each whole ripple device can receive a voltage signal that is transmitted by a voltage source to be measured, and the upper voltage limit of setting according to described whole ripple device and lower voltage limit are to described voltage signal comparison process in addition, and export the logical signal of a correspondence by the output terminal of described whole ripple device, wherein, when described voltage signal is higher than described upper voltage limit, the logical signal of described whole ripple device output noble potential, when described voltage signal is lower than described lower voltage limit, the logical signal of described whole ripple device output electronegative potential; And
At least one logic level translator, each logic level translator is equipped with one and sets end, an output terminal and a reset terminal, and each logic level translator receives the described logical signal of corresponding whole ripple device output, in addition a digital signal is handled and be converted to logic level transition, and by described output terminal output;
Wherein, the output terminal of described whole ripple device connects this reset terminal, connects this setting end by a phase inverter in addition.
11. electric voltage observation circuit according to claim 10, it is characterized in that, this electric voltage observation circuit further includes a management system and a buffer that is connected with the output terminal of each logic level translator, this buffer is used for writing down the digital signal that each logic level translator produces, and this management system reads the digital signal that is stored in this buffer through a bus.
12. electric voltage observation circuit according to claim 10, it is characterized in that, this electric voltage observation circuit further includes at least one voltage adjusting device, the input end of each voltage adjusting device connects this voltage source to be measured, and the output terminal of each voltage adjusting device connect its input end of corresponding whole ripple device.
13. electric voltage observation circuit according to claim 10 is characterized in that, described whole ripple device is provided with an operating voltage input end, is connected to this voltage source to be measured.
14. electric voltage observation circuit according to claim 10 is characterized in that, described whole ripple device is a schmitt trigger.
15. electric voltage observation circuit according to claim 10 is characterized in that, described logic level translator is a rest-set flip-flop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100646950A CN100360945C (en) | 2005-04-20 | 2005-04-20 | Electric voltage observation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100646950A CN100360945C (en) | 2005-04-20 | 2005-04-20 | Electric voltage observation circuit |
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| Publication Number | Publication Date |
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| CN1670537A CN1670537A (en) | 2005-09-21 |
| CN100360945C true CN100360945C (en) | 2008-01-09 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100646950A Active CN100360945C (en) | 2005-04-20 | 2005-04-20 | Electric voltage observation circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI697679B (en) * | 2019-06-06 | 2020-07-01 | 佑華微電子股份有限公司 | Voltage detection circuit capable of setting voltage detection level |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101325413B (en) * | 2007-06-14 | 2011-09-14 | 旺宏电子股份有限公司 | Switching circuit for power supply |
| CN101521044B (en) * | 2008-02-28 | 2012-04-04 | 华邦电子股份有限公司 | Memorizer and voltage monitoring equipment thereof |
| CN105629028B (en) * | 2014-11-04 | 2019-03-01 | 华邦电子股份有限公司 | Detect supply voltage surging method and circuit of single-chip integrated device |
| CN105490260A (en) * | 2015-12-31 | 2016-04-13 | 山东海量信息技术研究院 | POWER platform-based OVP protection circuit |
| TWI706616B (en) * | 2020-02-12 | 2020-10-01 | 新唐科技股份有限公司 | Glitch detection circuit |
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| JPS54154365A (en) * | 1978-05-25 | 1979-12-05 | Seiko Instr & Electronics Ltd | Power supply voltage detecting circuit |
| CN1049058A (en) * | 1989-07-22 | 1991-02-06 | 云南省电力工业局试验研究所 | On-line overvoltage monitor for electric power system |
| CN1381732A (en) * | 2002-04-15 | 2002-11-27 | 威盛电子股份有限公司 | Voltage (potential) measurer |
| US6747470B2 (en) * | 2001-12-19 | 2004-06-08 | Intel Corporation | Method and apparatus for on-die voltage fluctuation detection |
| CN2636251Y (en) * | 2003-06-20 | 2004-08-25 | 武汉科技大学 | Voltage/current on-line monitor |
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2005
- 2005-04-20 CN CNB2005100646950A patent/CN100360945C/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54154365A (en) * | 1978-05-25 | 1979-12-05 | Seiko Instr & Electronics Ltd | Power supply voltage detecting circuit |
| CN1049058A (en) * | 1989-07-22 | 1991-02-06 | 云南省电力工业局试验研究所 | On-line overvoltage monitor for electric power system |
| US6747470B2 (en) * | 2001-12-19 | 2004-06-08 | Intel Corporation | Method and apparatus for on-die voltage fluctuation detection |
| CN1381732A (en) * | 2002-04-15 | 2002-11-27 | 威盛电子股份有限公司 | Voltage (potential) measurer |
| CN2636251Y (en) * | 2003-06-20 | 2004-08-25 | 武汉科技大学 | Voltage/current on-line monitor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI697679B (en) * | 2019-06-06 | 2020-07-01 | 佑華微電子股份有限公司 | Voltage detection circuit capable of setting voltage detection level |
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| CN1670537A (en) | 2005-09-21 |
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