CN100343749C - Array substrate of thin film transistor liquid crystal display and manufacturing method thereof - Google Patents
Array substrate of thin film transistor liquid crystal display and manufacturing method thereof Download PDFInfo
- Publication number
- CN100343749C CN100343749C CNB2005100070429A CN200510007042A CN100343749C CN 100343749 C CN100343749 C CN 100343749C CN B2005100070429 A CNB2005100070429 A CN B2005100070429A CN 200510007042 A CN200510007042 A CN 200510007042A CN 100343749 C CN100343749 C CN 100343749C
- Authority
- CN
- China
- Prior art keywords
- layer
- lcd
- array substrate
- thin film
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The present invention relates to a TFT-LCD array base and a making method thereof. A transparent conductor layer, a first metal layer, a first insulation layer, a semiconductor layer, a second insulation layer and a sacrificial layer orderly are formed on the base; light resistance patterns with different thickness are formed on part of the sacrificial layer by using a first light cover; a grid line which comprises a grid, a signal channel layer positioned right above the grid, a grid pad positioned on the end of the grid line, a pixel electrode and a source electrode pad are defined through a series of etching programs by using the light resistance patterns as cover veils; insulation gap walls are formed on the side walls of the grid and the grid line; a source electrode line, a source electrode and a drain electrode are formed by using a second light cover; the end of the source electrode line is connected with the source electrode pad, the source electrode is connected with the source electrode line and the signal channel layer, and the drain electrode is connected with the signal channel layer and the pixel electrode. According to the present invention, the array base can be formed only by using the two light covers.
Description
Technical field
The present invention relates to a kind of LCD manufacturing process, particularly, relate to a kind of array substrate (array substrate) and manufacture method thereof that is used in Thin Film Transistor-LCD (TFT-LCD).
Background technology
LCD includes substrate and substrate once on one, and is sandwiched in the liquid crystal layer between the substrate up and down.In general, last substrate has a colored filter (color filter) and community electrode (common electrode).And substrate has the gate line (gate lines) of horizontal expansion, the source electrode line of longitudinal extension (source lines down, or claim data line), to be positioned at gate line be the thin film transistor (TFT) (TFT) of switch module with near being used as of source electrode line infall, and by the pixel electrode in gate line and the defined zone of source electrode line.Each thin film transistor (TFT) has a grid, one source pole and a drain electrode.Grid extends out from gate line, and source electrode extends out from source electrode line.Drain electrode normally electrically connects pixel electrode by means of a contact hole (contact hole).LCD also comprises pad part (pad portions).The pad part includes a plurality of gate pads and multiple source polar cushion (or data pad), and wherein gate pad is used to provide signal voltage to gate line, and source pad is used to provide data voltage to source electrode line.These gate pads and multiple source polar cushion preferably are positioned at non-display area.
In order to make array substrate, must repeat in following substrate for example is deposition, lithography or the like many processing procedures.Yet in existing array substrate processing procedure, can use the light shield in 4～6 roads usually, therefore the shortcoming of manufacturing cost height and processing procedure complexity is arranged.
In No. the 6338989th, United States Patent (USP), people such as Ahn have proposed the manufacture method of the array substrate of a kind of TFT-LCD.This method has been used four road light shields.First road and the second road light shield are to be used for forming gate line, gate pad, data line and data pad.The 3rd road light shield is to be used for forming source electrode, drain electrode, pixel electrode and channel region is exposed.The 4th road light shield is to be used for patterning covering gate polar curve and the insulation course of gate pad and the contact hole that is connected gate pad.Yet this method is not instructed array substrate structure and the manufacture method thereof of the TFT-LCD of this case.
In No. the 6567150th, United States Patent (USP), Kim has proposed the manufacture method of the array substrate of a kind of TFT-LCD.This method has been used six road light shields.Yet this method is not instructed array substrate structure and the manufacture method thereof of the TFT-LCD of this case yet.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of twice light shield that only needs just can form the method for the array substrate of TFT-LCD, and can reduce cost and simplify processing procedure.
Another object of the present invention is to propose the array substrate of a kind of TFT-LCD.
For reaching above-mentioned purpose, the invention provides the manufacture method of the array substrate of a kind of TFT-LCD, its step comprises: form a transparent conductor layer, a first metal layer, one first insulation course, semi-conductor layer, one second insulation course and a sacrifice layer in regular turn in a substrate; Form a photoresistance pattern on this sacrifice layer of part, this photoresistance pattern comprises and comprises one first photoresist layer and one second photoresist layer, this second photoresist layer is thicker than this first photoresist layer, and wherein this first photoresist layer and this second photoresist layer are positioned at the zones of different on this sacrifice layer; With this photoresistance pattern is cover curtain, removes this sacrifice layer of part, this second insulation course and this semiconductor layer at least and forms one first opening and one second opening; Remove this first photoresist layer; With this second photoresist layer is cover curtain, removes this sacrifice layer of part and forms width and be narrower than one of this second photoresist layer residue sacrifice layer, and remove this second insulation course of part and this semiconductor layer, and make described first and second open bottom expose this substrate; Remove this second photoresist layer; With this residue sacrifice layer is the cover curtain, removes this second insulation course of part and this remaining first insulation course; Remove this surplus sacrifice layer and this first metal layer that exposes to the open air, thereby define the gate line that comprises a grid, be positioned at a channel layer, a gate pad that is positioned at this gate line end, a pixel electrode and one source pole pad directly over this grid, wherein this first opening is arranged in this gate line and near this grid; Form an insulating gap wall on the sidewall of this gate line, grid and this semiconductor layer: form one second metal level in this substrate top comprehensively; And this second metal level of patterning and form one source pole line, one source pole and a drain electrode, wherein this source electrode line intersects at this gate line, the end of this source electrode line connects this source pad, this source electrode extends out and connects partly this channel layer from this source electrode line, and this drain electrode connects partly this channel layer and this pixel electrode.
According to above-mentioned method, the present invention also provides a kind of array substrate structure of Thin Film Transistor-LCD, comprise: a substrate, have a gate line district that comprises a gate regions, a gate pad district that connects this end, gate line district, with this gate line district one of intersect the source electrode line district, be connected one of this end, source electrode line district source pad district and the pixel region between this gate line district and this source electrode line district; One transparent conductor layer is formed at the position in this substrate in this gate pad district, this gate regions, this gate line district, pixel region and this source pad district; One the first metal layer is formed at the position on this transparent conductor layer in this gate regions and this gate line district; One first insulation course is formed on this first metal layer; Semi-conductor layer is formed on this first insulation course; One insulating gap wall is formed on the sidewall of this gate line, grid and this semiconductor layer; One second insulation course is formed on this semiconductor layer of part; And one second metal level, be formed at the position above this substrate in this source electrode line district, on this semiconductor layer of part of position and on this transparent conductor layer of part of position at this pixel region in this gate regions.Wherein, it is the one source pole line that the position is used as at this second metal level in this source electrode line district, it is an one source pole and a drain electrode that position this second metal level on this semiconductor layer of part of this gate regions is used as, and this source electrode connects this source electrode line, and should drain electrode connect position this transparent conductor layer at this pixel region.
According to the manufacture method of array substrate of the present invention, just can finish array substrate structure of the present invention, thereby can reduce manufacturing cost and simplify processing procedure with the twice light shield.
For purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended icon, be described below in detail:
Description of drawings
Fig. 1 has shown the partial plan of the array substrate of Thin Film Transistor-LCD of the present invention:
Fig. 2 is that a series of deposition is carried out in its demonstration along the processing procedure diagrammatic cross-section of the X-Y broken string of Fig. 1;
Fig. 3 is the processing procedure diagrammatic cross-section along the X-Y of Fig. 1 broken string, and its demonstration is used little shadow program of the first road light shield and obtained having the photoresistance pattern of different-thickness;
Fig. 4 is the processing procedure diagrammatic cross-section along the X-Y broken string of the 1st figure, and it shows with this photoresistance pattern serves as that the cover curtain carries out etching program;
Fig. 5 is the processing procedure diagrammatic cross-section along the X-Y broken string of the 1st figure, and it shows to remove part photoresistance pattern;
Fig. 6 is that the sidewall etch processing procedure of sacrifice layer is carried out in its demonstration along the processing procedure diagrammatic cross-section of the X-Y broken string of the 1st figure;
Fig. 7 is the processing procedure diagrammatic cross-section along the X-Y broken string of the 1st figure, and its demonstration forms exposes the opening of substrate;
Fig. 8 is the processing procedure diagrammatic cross-section along the X-Y ' broken string of the 1st figure, and it shows to remove part second insulation course and photoresist layer;
Fig. 9 is that its display definition goes out gate line, grid, gate pad, pixel electrode and source pad along the processing procedure diagrammatic cross-section of the X-Y broken string of the 1st figure;
Figure 10 is the processing procedure diagrammatic cross-section along the X-Y broken string of the 1st figure, and it shows that the formation insulating gap wall is on the sidewall of gate line and grid;
Figure 11 is that little shadow program of the second road light shield is used in its demonstration along the processing procedure diagrammatic cross-section of the X-Y broken string of the 1st figure;
Figure 12 is that its display definition goes out source electrode line, source electrode and drain electrode along the processing procedure diagrammatic cross-section of the X-Y broken string of the 1st figure;
Figure 13 A～13C has shown that one of the partially-etched step of the present invention changes the manufacturing process of example;
Figure 14 A～14C has shown the manufacturing process of another variation example of the partially-etched step of the present invention; And
Figure 15 A～15C has shown the manufacturing process of another variation example of the partially-etched step of the present invention.
Symbol description
The array substrate of 100～TFT-LCD of the present invention; 200～substrate; 210～transparent conductor layer; 220～the first metal layer; 230～the first insulation courses; 240～semiconductor layer; 250～the second insulation courses; 260～sacrifice layer; 270～photoresistance pattern; 272～the first photoresist layers; 274,274 '～the second photoresist layers; 310～the first road light shields; 312～translucent area; 314～zone of opacity; 316～transparent region; 320～micro-photographing process (exposure); 410～the first openings; 420～the second openings; 260 '～remaining sacrifice layer; 610～space; 910～gate line (district); 912～grid (district); 914～channel layer; 916～gate pad (district): 918～pixel electrode (district); 920～source pad (district); 1010～insulating gap wall; 1110～semiconductor layer through mixing; 1120～the second metal levels; 1130～sheath; 1140～the second road light shields; 1142～zone of opacity: 1144～transparent region; 1150～micro-photographing process (exposure); 1160～photoresistance pattern; 1210～source electrode line (district); 1220～source electrode; 1230～drain electrode.
Embodiment
Fig. 1 has shown the partial plan of the array substrate 100 of Thin Film Transistor-LCD of the present invention, and Fig. 2～12nd, along the diagrammatic cross-section of the X-Y line segment of the 1st figure, in order to processing procedure of the present invention to be described.
See also Fig. 2, at first providing for example is a dielectric base 200 of glass, and then utilizes sedimentation to deposit a transparent conductor layer 210, a first metal layer 220, one first insulation course 230, semi-conductor layer 240, one second insulation course 250 and a sacrifice layer 260 in order in this substrate 200.Wherein, this transparent conductor layer 210 for example is indium tin oxide (ITO) or indium-zinc oxide (IZO) layer, and this first metal layer 220 for example is the metal level of the sandwich construction of Al or Al alloy or aluminous layer or aluminium alloy layer, and this first insulation course 230 for example is Si
3N
4Or SiO
2Layer, this semiconductor layer 240 for example is amorphous silicon layer (amorphous silicon), this second insulation course 250 for example is Si
3N
4Or SiO
2Layer, and this sacrifice layer 260 for example is Al or Mo or Cr or ITO or IZO.
See also Fig. 3, coating one photoresist layer (icon is not example at this with the eurymeric photoresistance) is on this sacrifice layer 260 earlier.Then, via using half light modulation cover (half-tone mask, i.e. first light shield) little shadow step 320 of 310 and form the photoresistance pattern 270 that comprises one first photoresist layer 272 and one second photoresist layer 274 on this sacrifice layer 260 partly, wherein this second photoresist layer 274 is thicker than this first photoresist layer 272.The employed half light modulation cover 310 of this embodiment includes three kinds of zones 312,314 and 316 with different transmittances, translucent area 312 corresponding first photoresist layers 272 for example, zone of opacity 314 is corresponding second photoresist layer 274, and other is a transparent region 316.
Seeing also Fig. 4, serves as cover curtain with this photoresistance pattern 270, removes this sacrifice layer 260 of part, this second insulation course 250 and this semiconductor layer 240 at least and forms one first opening 410 and one second opening 420.See also Fig. 1, the position of this first opening 410 is corresponding near the gate line 910 the grid 912 that will form in the future, and the position of this second opening 420 is corresponding to around the pixel electrode 918 that will form in the future.In the 4th figure, these openings 410,420 are example to expose first insulation course 230.
See also Fig. 5, remove this first photoresist layer 272 via ashing (ashing) program, thus form remaining second photoresist layer 274 ' in the part this sacrifice layer 260 on.
See also Fig. 6, with this remaining second photoresist layer 274 ' serve as cover curtain, carry out anisotropic etching (for example dry ecthing) and isotropic etching (for example wet etching) in regular turn and remove this sacrifice layer 260 of part, and form second photoresist layer 274 that width is narrower than residue ' a residue sacrifice layer 260 '.This step is called the lateral erosion of sacrifice layer and carves (side etching), makes that remaining second photoresist layer, 274 ' downside at this forms undercutting space (undercut) 610.When this sacrifice layer 260 for example was aluminium, then above-mentioned isotropic etching for example was to adopt the wet etching that contains salpeter solution.It should be noted that the design of the present invention, make after journey is scribed in above-mentioned lateral erosion, be positioned at this residue sacrifice layer 260 around this first opening 410 ' be discontinuous by means of first opening 410 and second opening 420.
See also Fig. 7, then with second photoresist layer 274 of this residue ' serve as the cover curtain, anisotropic is removed (for example dry ecthing) this second insulation course 250 and this semiconductor layer 240 and removal simultaneously this first insulation course 230 in these first and second openings 410,420.Afterwards, still with this remaining second photoresist layer 274 ' serve as cover curtain, anisotropic is removed (for example dry ecthing) position this first metal layer 220 and this transparent conductor layer 210 first and second opening 410,420 in, and exposes this substrate 200.
What will specify here is that the described etch sequence in above-mentioned Fig. 4～7 only is an example, and non-limiting the present invention.That is have many kinds of variation also can adopt and can access as shown in Figure 7 structure equally, in three kinds of variation of this measure for application person's reference.
The flow process of first variation sees also Figure 13 A～13C.With this photoresistance pattern 270 is the cover curtain, remove this sacrifice layer 260 of part, this second insulation course 250, this semiconductor layer 240 and this first insulation course 230 and form first opening 410 and second opening 420, these openings 410,420 are to expose this first metal layer 220.Then, remove this first photoresist layer 272 via the ashing program, thus form remaining second photoresist layer 274 ' in the part this sacrifice layer 260 on.Then, with this remaining second photoresist layer 274 ' serve as cover curtain, carry out anisotropic and isotropic etching in regular turn and remove this sacrifice layer 260 of part, and form width be narrower than this remaining second photoresist layer 274 ' residue sacrifice layer 260 ', also remove this first metal layer 220 in these first and second openings 410,420 this moment, this sacrifice layer 260 of this variation ' preferably adopt the same metal material with this first metal layer 220 for example is an aluminium.Then, with this remaining second photoresist layer 274, be the cover curtain, anisotropic is removed (for example dry ecthing) this second insulation course 250 and this semiconductor layer 240 and is removed position this transparent conductor layer 210 in these first and second openings 410,420, and exposes this substrate 200.So just can access the structure shown in the 7th figure.
The flow process of second variation sees also the 14A～14C figure.With this photoresistance pattern 270 is the cover curtain, remove this sacrifice layer 260 of part, this second insulation course 250, this semiconductor layer 240, this first insulation course 230 and this first metal layer 220 and form first opening 410 and second opening 420, these openings 410,420 expose this transparent conductor layer 210.Then, remove this first photoresist layer 272, thereby form remaining second photoresist layer 274, on this sacrifice layer 260 of part via the ashing program.Then, with this remaining second photoresist layer 274 ' serve as cover curtain, carry out anisotropic and isotropic etching in regular turn and remove this sacrifice layer 260 of part, and form second photoresist layer 274 that width is narrower than this residue ' residue sacrifice layer 260 ', this sacrifice layer 260 of this variation ' for example be aluminium, and this first metal layer 220 preferably adopts the aluminum metal of aluminium alloy or process anodizing.Then, with this remaining second photoresist layer 274 ' serve as cover curtain, anisotropic is removed (for example dry ecthing) this second insulation course 250 and this semiconductor layer 240 and is removed position this transparent conductor layer 210 in these first and second openings 410,420, and exposes this substrate 200.So just can access the structure shown in the 7th figure.
The flow process of the 3rd variation sees also Figure 15 A～15C.With this photoresistance pattern 270 is the cover curtain, remove this sacrifice layer 260 of part, this second insulation course 250, this semiconductor layer 240, this first insulation course 230, this first metal layer 220 and this transparent conductor layer 210 and form first opening 410 and second opening 420, these openings 410,420 expose this substrate 200.Then, remove this first photoresist layer 272 via the ashing program, thereby second photoresist layer 274 of formation residue ' on this sacrifice layer 260 of part.Then, with this remaining second photoresist layer 274 ' serve as cover curtain, carry out anisotropic and isotropic etching in regular turn and remove this sacrifice layer 260 of part, and form width be narrower than this remaining second photoresist layer 274 ' residue sacrifice layer 260 ', this sacrifice layer 260 of this variation ' for example be aluminium, and this first metal layer 220 preferably adopts the aluminum metal of aluminium alloy or process anodizing.Then, with second photoresist layer 274 of this residue ' serve as the cover curtain, anisotropic is removed (for example dry ecthing) this second insulation course 250 and this semiconductor layer 240.So just can access structure as shown in Figure 7.
See also Fig. 8 again, remove earlier this remaining second photoresist layer 274 ', and expose this residue sacrifice layer 260 '.With this residue sacrifice layer 260 ' serve as cover curtain, remove part this second insulation course 250 and this first insulation course 230 then.
See also the 9th figure, remove this residue sacrifice layer 260 ' with this first metal layer 220 that exposes to the open air, thereby define the gate line 910 that comprises a grid 912, be positioned at a channel layer (channel layer) 914 directly over this grid 912, be positioned at a gate pad 916, a pixel electrode 918 and the one source pole pad 920 of these gate line 910 ends, wherein this first opening 410 is arranged in this gate line 910 and near this grid 912.Here be noted that, see also Fig. 1, the present invention is by means of near the narrower design of gate line 910 width first opening 410 and first opening 410, make and after above-mentioned numerous etch process, becoming discontinuous by the semiconductor layer 240 that is positioned at first opening 410 gate line 910 tops on every side.
See also Figure 10, deposition one insulation course of complying with (not icon) is covered in this substrate 200 tops comprehensively earlier, form an insulating gap wall 1010 then via anisotropic etching (for example dry ecthing) on the sidewall of this gate line 910, this grid 912 and semiconductor layer 240, wherein this insulating gap wall 1010 for example is Si
3N
4Or SiO
2Layer.
See also Figure 11, deposit in regular turn once the semiconductor layer 1110, one second metal level 1120 and the sheath 1130 that mix in whole substrate 200 tops.Should the semiconductor layer 1110 through mixing for example be Doped n wherein
+The silicon layer of type ion, this second metal level 1120 for example are the metal levels of the sandwich construction of Al or Al alloy or aluminous layer or aluminium alloy layer, and this sheath 1130 for example is the Si3N4 layer.Afterwards, form a photoresistance pattern 1160 via little shadow step 1150 of using one second light shield 1140.Symbol 1142 is represented zone of opacity, and symbol 1144 is represented transparent region.
See also the 12nd figure, with this photoresistance pattern 1160 is the cover curtain, this sheath 1130 of patterning, this second metal level 1120 with this through mixing semiconductor layer 1110 and define by second metal level 1110 and one of constituted source electrode line (or claiming data line) 1210, an one source pole 1220 and a drain electrode 1230, wherein this source electrode line 1210 is to intersect at this gate line 910, the end of this source electrode line 1210 electrically connects this source pad 920, this source electrode 1220 extends out and electrically connects partly this channel layer 914 from this source electrode line 1210, and this drain electrode 1230 electrically connects partly these channel layers 914 and these pixel electrodes 918.At last, remove this photoresistance pattern 1160.So, via the invention described above processing procedure, can just can obtain the array substrate 100 of TFT-LCD with twice micro-photographing process (being the twice light shields).
According to above-mentioned processing procedure, the present invention also provides a kind of array substrate structure 100 of Thin Film Transistor-LCD.See also Fig. 1 and Figure 12, this array substrate structure 100 comprises: a dielectric base 200, the one source pole line district 1210, the one source pole pad district 920 that is connected these 1210 ends, source electrode line district and the pixel region 918 between this gate line district 910 and this source electrode line district 1210 that have a gate line district 910 that comprises a gate regions 912, a gate pad district 916 that connects these 910 ends, gate line district, intersect with this gate line district 910; One transparent conductor layer 210 is formed at the position in this substrate 200 in this gate pad district 916, this gate regions 912, this gate line district 910, pixel region 918 and this source pad district 920; One the first metal layer 220, be formed at the position on this transparent conductor layer 210 in this gate regions 912 and this gate line district 910: one first insulation course 230 is formed on this first metal layer 220; Semi-conductor layer 240 is formed on this first insulation course 230; One insulating gap wall 1010 is formed on the sidewall of this first metal layer 220 at least; One second insulation course 250, be formed on this semiconductor layer 240 of part: and one second metal level 1120, be formed at the position above this substrate 200 in this source electrode line district 1210, on this semiconductor layer 240 of part of position and on this transparent conductor layer 210 of part of position at this pixel region 918 in this gate regions 912.Wherein, this second metal level 1120 in this source electrode line district 1210 of position is that to be used as be one source pole line 1210, it is an one source pole 1220 and a drain electrode 1230 that position this second metal level 1120 on this semiconductor layer 240 of part of this gate regions 912 is used as, this source electrode 1220 electrically connects this source electrode line 1210, and should drain electrode 1230 electrically connect position this transparent conductor layer 210 at this pixel region 918.
The invention is characterized in the processing procedure of the array substrate of TFT-LCD: a photoresistance pattern that comprises one first photoresist layer and one second photoresist layer with the first road light shield (i.e. half light modulation cover) formation is on this sacrifice layer of part, and this second photoresist layer is thicker than this first photoresist layer; With this photoresistance pattern is cover curtain, removes this sacrifice layer of part, this second insulation course and this semiconductor layer at least and forms one first opening and one second opening; Remove this first photoresist layer; With this second photoresist layer is cover curtain, removes this sacrifice layer of part and forms the residue sacrifice layer that width is narrower than this second photoresist layer, and remove this second insulation course of part and this semiconductor layer, and make these first and second open bottom expose this substrate; Remove this second photoresist layer; With this residue sacrifice layer is the cover curtain, remove this second insulation course of part and this first insulation course: remove this surplus sacrifice layer and this first metal layer that exposes to the open air, thereby define the gate line that comprises a grid, be positioned at a channel layer, a gate pad that is positioned at this gate line end, a pixel electrode and one source pole pad directly over this grid, wherein this first opening is arranged in this gate line and near this grid; Form an insulating gap wall on the sidewall of this grid and this gate line; Form one second metal level in this substrate top comprehensively; And utilize the second road light shield to come this second metal level of patterning and form one source pole line, one source pole and a drain electrode.
According to the present invention, just can finish array substrate structure of the present invention, thereby can reduce manufacturing cost and simplify processing procedure with the twice light shield.
Though the present invention with preferred embodiment openly as above; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing many changes and modification, so protection scope of the present invention defines and is as the criterion when looking accompanying Claim.
Claims (27)
1, a kind of manufacture method of array substrate of Thin Film Transistor-LCD, its step comprises:
Form a transparent conductor layer, a first metal layer, one first insulation course, semi-conductor layer, one second insulation course and a sacrifice layer in regular turn in a substrate;
Form a photoresistance pattern on this sacrifice layer of part, this photoresistance pattern comprises one first photoresist layer and one second photoresist layer, and this second photoresist layer is thicker than this first photoresist layer, and wherein this first photoresist layer and this second photoresist layer are positioned at the zones of different on this sacrifice layer;
With this photoresistance pattern is cover curtain, removes this sacrifice layer of part, this second insulation course and this semiconductor layer at least and forms one first opening and one second opening;
Remove this first photoresist layer;
With this second photoresist layer is cover curtain, removes this sacrifice layer of part and forms width and be narrower than one of this second photoresist layer residue sacrifice layer, and remove this second insulation course of part and this semiconductor layer, and make these first and second open bottom expose this substrate;
Remove this second photoresist layer;
With this residue sacrifice layer is the cover curtain, removes this second insulation course of part and this first insulation course;
Remove this surplus sacrifice layer and this first metal layer that exposes to the open air, thereby define the gate line that comprises a grid, be positioned at a channel layer, a gate pad that is positioned at this gate line end, a pixel electrode and one source pole pad directly over this grid, wherein this first opening is arranged in this gate line and near this grid;
Form an insulating gap wall on the sidewall of this gate line, grid and semiconductor layer;
Form one second metal level in this substrate top comprehensively; And
This second metal level of patterning and form one source pole line, one source pole and a drain electrode, wherein this source electrode linear system intersects at this gate line, the end system of this source electrode line connects this source pad, this source electrode extends out and connects partly this channel layer from this source electrode line, and this drain electrode connects partly this channel layer and this pixel electrode.
2, the manufacture method of the array substrate of Thin Film Transistor-LCD as claimed in claim 1, wherein, this photoresistance pattern that comprises described first and second photoresist layer forms via little shadow step of using half light modulation cover.
3, the manufacture method of the array substrate of Thin Film Transistor-LCD as claimed in claim 1, wherein, this second metal level forms via little shadow step of using a light shield.
4, the manufacture method of the array substrate of Thin Film Transistor-LCD as claimed in claim 1, wherein, this transparent conductor layer is indium tin oxide (ITO) or indium-zinc oxide (IZO) layer.
5, the manufacture method of the array substrate of Thin Film Transistor-LCD as claimed in claim 1, wherein, this first metal layer is the metal level of the sandwich construction of Al or Al alloy or aluminous layer or aluminium alloy layer.
6, the manufacture method of the array substrate of Thin Film Transistor-LCD as claimed in claim 1, wherein, these first insulation series of strata Si
3N
4Or SiO
2Layer.
7, the manufacture method of the array substrate of Thin Film Transistor-LCD as claimed in claim 1, wherein, this semiconductor series of strata amorphous silicon layer.
8, the manufacture method of the array substrate of Thin Film Transistor-LCD as claimed in claim 1, wherein, these second insulation series of strata Si
3N
4Or SiO
2Layer.
9, the manufacture method of the array substrate of Thin Film Transistor-LCD as claimed in claim 1, wherein, this sacrifice layer is Al or Mo or Cr or ITO or IZO.
10, the manufacture method of the array substrate of Thin Film Transistor-LCD as claimed in claim 1, wherein, this insulating gap wall is Si
3N
4Or SiO
2Layer.
11, the manufacture method of the array substrate of Thin Film Transistor-LCD as claimed in claim 1, wherein, this second metal level is the metal level of the sandwich construction of Al or Al alloy or aluminous layer or aluminium alloy layer.
12, the manufacture method of the array substrate of Thin Film Transistor-LCD as claimed in claim 1 also comprises forming once the semiconductor layer that mixes under this second metal level.
13, the manufacture method of the array substrate of Thin Film Transistor-LCD as claimed in claim 1 also comprises forming a sheath on this second metal level.
14, the manufacture method of the array substrate of Thin Film Transistor-LCD as claimed in claim 13, wherein, this sheath is Si
3N
4Layer.
15, the manufacture method of the array substrate of Thin Film Transistor-LCD as claimed in claim 1, wherein, the step that forms this residue sacrifice layer and make described first and second open bottom expose this substrate comprises:
With this second photoresist layer is cover curtain, carries out lateral erosion and carves and remove this sacrifice layer of part and form this residue sacrifice layer that width is narrower than this second photoresist layer;
With this second photoresist layer is the cover curtain, and anisotropic is removed this first insulation course, this second insulation course and this semiconductor layer in these first and second openings;
With this second photoresist layer is the cover curtain, and anisotropic is removed this first metal layer and this transparent conductor layer in described first and second opening.
16, a kind of array substrate of Thin Film Transistor-LCD comprises:
One substrate, the one source pole line district, the one source pole pad district that is connected this end, source electrode line district and the pixel region between this gate line district and this source electrode line district that have a gate line district that comprises a gate regions, a gate pad district that connects this end, gate line district, intersect with this gate line district;
One transparent conductor layer is formed at the position in this substrate in this gate pad district, this gate regions, this gate line district, pixel region and this source pad district;
One the first metal layer is formed at the position on this transparent conductor layer in this gate regions and this gate line district;
One first insulation course is formed on this first metal layer:
Semi-conductor layer is formed on this first insulation course;
One insulating gap wall is formed on the sidewall of this gate line, grid and semiconductor layer:
One second insulation course is formed on this semiconductor layer of part; And
One second metal level is formed at the position above this substrate in this source electrode line district, on this semiconductor layer of part in this gate regions of position and on this transparent conductor layer of part at this pixel region of position.
17, the array substrate of Thin Film Transistor-LCD as claimed in claim 16, wherein, it is the one source pole line that the position is used as at this second metal level in this source electrode line district, it is an one source pole and a drain electrode that position this second metal level on this semiconductor layer of part of this gate regions is used as, this source electrode connects this source electrode line, and should drain electrode connect position this transparent conductor layer at this pixel region.
18, the array substrate of Thin Film Transistor-LCD as claimed in claim 15, wherein, this transparent conductor layer is indium tin oxide (ITO) or indium-zinc oxide (IZO) layer.
19, the array substrate of Thin Film Transistor-LCD as claimed in claim 16, wherein, this first metal layer is the metal level of the sandwich construction of Al or Al alloy or aluminous layer or aluminium alloy layer.
20, the array substrate of Thin Film Transistor-LCD as claimed in claim 16, wherein, this first insulation course is Si
3N
4Or SiO
2Layer.
21, the array substrate of Thin Film Transistor-LCD as claimed in claim 16, wherein, this semiconductor layer is an amorphous silicon layer.
22, the array substrate of Thin Film Transistor-LCD as claimed in claim 16, wherein, this second insulation course is Si
3N
4Or SiO
2Layer.
23, the array substrate of Thin Film Transistor-LCD as claimed in claim 16, wherein, this insulating gap wall is Si
3N
4Or SiO
2Layer.
24, the array substrate of Thin Film Transistor-LCD as claimed in claim 16, wherein, this second metal level is the metal level of the sandwich construction of Al or Al alloy or aluminous layer or aluminium alloy layer.
25, the array substrate of Thin Film Transistor-LCD as claimed in claim 16 also comprises once the semiconductor layer that mixes, and is formed under this second metal level.
26, the array substrate of Thin Film Transistor-LCD as claimed in claim 16 also comprises a sheath, is formed on this second metal level.
27, the array substrate of Thin Film Transistor-LCD as claimed in claim 26, wherein, this sheath is Si
3N
4Layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100070429A CN100343749C (en) | 2005-01-27 | 2005-01-27 | Array substrate of thin film transistor liquid crystal display and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100070429A CN100343749C (en) | 2005-01-27 | 2005-01-27 | Array substrate of thin film transistor liquid crystal display and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1632685A CN1632685A (en) | 2005-06-29 |
| CN100343749C true CN100343749C (en) | 2007-10-17 |
Family
ID=34853084
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100070429A Active CN100343749C (en) | 2005-01-27 | 2005-01-27 | Array substrate of thin film transistor liquid crystal display and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100343749C (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100428480C (en) * | 2006-06-07 | 2008-10-22 | 友达光电股份有限公司 | Pixel structure and mfg. method thereof |
| TW201044088A (en) | 2009-06-15 | 2010-12-16 | Chunghwa Picture Tubes Ltd | Pixel structure and manufacturing method thereof and display panel |
| CN101614924B (en) * | 2009-08-05 | 2011-01-05 | 福州华映视讯有限公司 | Pixel structure, manufacturing method thereof and display panel |
| CN102109721B (en) * | 2010-11-22 | 2013-04-24 | 深圳市华星光电技术有限公司 | Method for manufacturing pixel array of liquid crystal display |
| CN105261585B (en) * | 2014-07-17 | 2018-05-25 | 中芯国际集成电路制造(上海)有限公司 | Production method, chip and the MEMS device of chip |
| CN104298018B (en) * | 2014-09-23 | 2018-05-04 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display panel |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0338766A1 (en) * | 1988-04-20 | 1989-10-25 | Matsushita Electric Industrial Co., Ltd. | Method of fabricating an active matrix substrate |
| JP2001326360A (en) * | 2000-05-18 | 2001-11-22 | Sharp Corp | Method for manufacturing active matrix substrate, active matrix substrate and method for manufacturing thin film field-effect transistor |
| US6388726B1 (en) * | 1998-10-29 | 2002-05-14 | Hyundai Display Technology Inc. | Method of manufacturing liquid crystal display device |
| US20020151116A1 (en) * | 2000-07-24 | 2002-10-17 | Ryouta Matsubara | Method for manufacturing tft array substrate of liquid crystal display device |
| US6567150B1 (en) * | 1997-06-11 | 2003-05-20 | Lg. Philips Lcd Co., Ltd. | Liquid crystal display and method of manufacturing the same |
| CN1519955A (en) * | 2003-02-03 | 2004-08-11 | ���ǵ�����ʽ���� | Thin film transistor array panel, its mfg. method and mask for such panel |
-
2005
- 2005-01-27 CN CNB2005100070429A patent/CN100343749C/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0338766A1 (en) * | 1988-04-20 | 1989-10-25 | Matsushita Electric Industrial Co., Ltd. | Method of fabricating an active matrix substrate |
| US6567150B1 (en) * | 1997-06-11 | 2003-05-20 | Lg. Philips Lcd Co., Ltd. | Liquid crystal display and method of manufacturing the same |
| US6388726B1 (en) * | 1998-10-29 | 2002-05-14 | Hyundai Display Technology Inc. | Method of manufacturing liquid crystal display device |
| JP2001326360A (en) * | 2000-05-18 | 2001-11-22 | Sharp Corp | Method for manufacturing active matrix substrate, active matrix substrate and method for manufacturing thin film field-effect transistor |
| US20020151116A1 (en) * | 2000-07-24 | 2002-10-17 | Ryouta Matsubara | Method for manufacturing tft array substrate of liquid crystal display device |
| CN1519955A (en) * | 2003-02-03 | 2004-08-11 | ���ǵ�����ʽ���� | Thin film transistor array panel, its mfg. method and mask for such panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1632685A (en) | 2005-06-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1324387C (en) | Array baseboard of LCD and its producing method | |
| CN100474043C (en) | Display base plate, liquid crystal display and method for manufacturing the same | |
| RU2510712C2 (en) | Circuit board, manufacturing method of card, display panel and display device | |
| KR100804378B1 (en) | Liquid crystal display device and method of manufacturing the same | |
| CN102655156B (en) | Array substrate and manufacturing method thereof | |
| CN100343749C (en) | Array substrate of thin film transistor liquid crystal display and manufacturing method thereof | |
| US20100245735A1 (en) | Array substrate and manufacturing method thereof | |
| KR20100024730A (en) | Thin film transistor array panel and manufacturing the same | |
| CN1655039A (en) | Thin film transistor, liquid crystal display using thin film transistor, and method of manufacturing thin film transistor | |
| KR20070076860A (en) | Organic light emitting display and fabrication method thereof | |
| CN1885511A (en) | Thin film transistor substrate and method of manufacturing the same | |
| CN1170196C (en) | Making process of film transistor LCD | |
| CN1632675A (en) | Method for manufacturing dot structure of thin film transistor liquid crystal display | |
| CN1637553A (en) | Liquid crystal display device and manufacturing method thereof | |
| CN1619393A (en) | Plane switching mode liquid crystal display device and fabrication method thereof | |
| CN1873530B (en) | Display device, method of manufacturing the same and mask for manufacturing the same | |
| CN1783458A (en) | Method for manufacturing a display device and method for forming a pattern | |
| CN101599497A (en) | Thin-film transistor array base-plate and forming method thereof | |
| CN1255701C (en) | Active matrix crystal display devices and manufacturing methods thereof | |
| CN1828871A (en) | Method for making picture element structure | |
| CN101692439B (en) | Manufacturing method for a plurality of groups of substrates of thin-film transistor | |
| CN1614489A (en) | Thin film transistor substrate for horizontal electric field LCD device and its manufacture | |
| CN1740887A (en) | Array base palte and manufacture method thereof and display device with this array base palte | |
| EP1576415B1 (en) | Liquid crystal displays | |
| US5432625A (en) | Display screen having opaque conductive optical mask and TFT of semiconductive, insulating, and conductive layers on first transparent conductive film |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: YOUDA PHOTOELECTRIC CO., LTD. Free format text: FORMER NAME OR ADDRESS: GUANGHUI ELECTRONIC CO., LTD. |
|
| CP03 | Change of name, title or address |
Address after: Hsinchu, Taiwan Patentee after: AU Optronics Corporation Address before: Taoyuan County of Taiwan Province Patentee before: Guanghui Electronic Co., Ltd. |