CH686017A5 - Device comprising a substrate and at least one chip. - Google Patents

Device comprising a substrate and at least one chip. Download PDF

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Publication number
CH686017A5
CH686017A5 CH117493A CH117493A CH686017A5 CH 686017 A5 CH686017 A5 CH 686017A5 CH 117493 A CH117493 A CH 117493A CH 117493 A CH117493 A CH 117493A CH 686017 A5 CH686017 A5 CH 686017A5
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Switzerland
Prior art keywords
substrate
arrangement according
cover
chip
arrangement
Prior art date
Application number
CH117493A
Other languages
German (de)
Inventor
Jean-Pierre Roth
Kurt Kolb
Original Assignee
Microdul Ag
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Filing date
Publication date
Application filed by Microdul Ag filed Critical Microdul Ag
Priority to CH117493A priority Critical patent/CH686017A5/en
Priority to DE4411210A priority patent/DE4411210A1/en
Publication of CH686017A5 publication Critical patent/CH686017A5/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/147—Structural association of two or more printed circuits at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04—Assemblies of printed circuits
    • H05K2201/049—PCB for one component, e.g. for mounting onto mother PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10386—Clip leads; Terminals gripping the edge of a substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10515—Stacked components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H05K3/3426—Leaded components characterised by the leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/361—Assembling flexible printed circuits with other printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/368—Assembling printed circuits with other printed circuits parallel to each other

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

1 1

CH 686 017 A5 CH 686 017 A5

2 2nd

Beschreibung description

Die vorliegende Erfindung betrifft eine Anordnung mit einem Substrat und mindestens einem Chip, der in einer Abdeckmasse eingebettet ist. The present invention relates to an arrangement with a substrate and at least one chip which is embedded in a covering compound.

Zum Schutz gegen mechanische und teilweise klimatische Einflüsse werden oft die auf einem Printsubstrat (COB) oder als Teil einer Dickfilmoder Dünnfilmschaltung auf einem Keramiksubstrat, bei Dünnfilm gegebenenfalls auch auf einem Glassubstrat angeordneten Chips im sogenannten Glob-Top-Verfahren mit einem Tropfen Expoxy oder Silikonmasse abgedeckt. Dabei entsteht ein System mit mindestens drei Materialien mit verschiedenen Ausdehnungskoeffizienten. To protect against mechanical and partly climatic influences, the chips arranged on a print substrate (COB) or as part of a thick-film or thin-film circuit on a ceramic substrate, or in the case of thin-film possibly also on a glass substrate, are covered with a drop of expoxy or silicone compound using the glob-top method . This creates a system with at least three materials with different expansion coefficients.

Die unterschiedlichen Ausdehnungskoeffizienten führen zu Spannungen und Scherkräften auf Chip und Bonddrähte und gegebenenfalls zu relativen Verschiebungen (Abscherungen), und zwar nicht nur während des Herstellungsprozesses, der eine Abkühlung der Abdeckmasse und ein Auflöten von zusätzlichen Komponenten bedingt, sondern auch später bei wechselnden Umge-bungs- und Operationsstemperaturen des fertigen Moduls. The different expansion coefficients lead to stresses and shear forces on the chip and bonding wires and possibly to relative displacements (shearings), not only during the manufacturing process, which requires the masking compound to cool down and additional components to be soldered on, but also later in changing environments - And operating temperatures of the finished module.

Derartige Probleme nehmen mit zunehmender Fläche der Chips zu. Speziell problematisch wird es dort, wo mehrere, grosse Chips auf einem Substrat innerhalb einer Multichip-Insel durch den gleichen Glob-Top abgedeckt werden müssen. Such problems increase with the area of the chips. It becomes particularly problematic where several large chips on a substrate within a multichip island have to be covered by the same glob top.

Im Fall von Dick- oder Dünnschicht-Keramiksub-straten wird schon durch das Abkühlen eines Epoxy-Glob-Tops eine wesentliche Durchbiegung des Substrats festgestellt, die zu Unterbrüchen in den Leiterbahnen bzw. zu Haarrissen im Substrat und/oder der Abdeckung führen kann. In the case of thick or thin-layer ceramic substrates, the cooling of an epoxy glob top already determines a substantial deflection of the substrate, which can lead to breaks in the conductor tracks or to hairline cracks in the substrate and / or the cover.

Es ist daher Aufgabe der vorliegenden Erfindung, eine Anordnung mit einem Substrat und mindestens einem Chip mit verminderten induzierten mechanischen Kräften zu schaffen. It is therefore an object of the present invention to provide an arrangement with a substrate and at least one chip with reduced induced mechanical forces.

Diese Aufgabe wird erfindungsgemäss durch eine Anordnung nach Anspruch 1 gelöst. According to the invention, this object is achieved by an arrangement according to claim 1.

Vorteilhafte Ausgestaltungen der Erfindung sind in den weiteren Ansprüchen angegeben. Advantageous embodiments of the invention are specified in the further claims.

Die Erfindung wird nachfolgend anhand einer Zeichnung näher erläutert. Es zeigen: The invention is explained in more detail below with reference to a drawing. Show it:

Fig. 1 eine schematische Darstellung eines Substrats mit einem Chip und einer nach dem Glob-Top-Verfahren hergestellten Abdeckung, 1 is a schematic representation of a substrate with a chip and a cover produced by the glob-top method,

Fig. 2 eine ähnliche Darstellung in einem durch induzierte mechanische Kräfte gebogenen Substrat, 2 shows a similar representation in a substrate bent by induced mechanical forces,

Fig. 3 bis 9 verschiedene mit einem zusätzlichen Deckel versehene Sandwich-Anordnungen nach der Erfindung. Fig. 3 to 9 different sandwich arrangements provided with an additional lid according to the invention.

Die in Fig. 1 dargestellte ideale Anordnung nach dem Stand der Technik weist ein Substrat 1, beispielsweise ein Keramik-, Print- oder Glassubstrat auf, auf dem ein durch Bonddrähte 3 mit der Sub-strat-Metallisierung 9 verbundener Silizium-Chip 2 gelötet oder geklebt ist. The ideal arrangement according to the prior art shown in FIG. 1 has a substrate 1, for example a ceramic, printed or glass substrate, on which a silicon chip 2 is soldered or bonded by bonding wires 3 to the substrate metallization 9 is glued.

Der Chip 2 und die Bonddrähte 3 sind nach dem Glob-Top-Verfahren durch eine Epoxy- oder Silikonmasse 4 abgedeckt. In der idealen Anordnung nach The chip 2 and the bonding wires 3 are covered by an epoxy or silicone compound 4 using the glob-top method. In the ideal arrangement according to

Fig. 1 werden die induzierten mechanischen Kräfte vernachlässigt. Fig. 1, the induced mechanical forces are neglected.

Fig. 2 zeigt eine ähnliche Anordnung nach dem Stand der Technik wie Fig. 1 ohne die bei der Abkühlung auftretenden Kräfte F, die wegen der verschiedenen Ausdehnungskoeffizienten zwischen dem Substrat 1 und der Abdeckmasse 4 entstehen, zu vernachlässigen. Fig. 2 shows a similar arrangement according to the prior art as Fig. 1 without neglecting the forces F occurring during cooling, which arise because of the different expansion coefficients between the substrate 1 and the masking compound 4.

Die Kräfte F führen zu einer, zur Veranschaulichung des zu schildernden Effekts übetrieben gezeichneten Durchbiegung des Substrats und gegebenenfalls zu Rissen im Substrat selbst und damit in den auf der oberen oder unteren Substratseite aufgebrachten Leiterbahnen und/oder Widerständen und/oder in der Abdeckung und damit zu Bonddraht-Unterbrüchen. The forces F lead to a deflection of the substrate, exaggerated to illustrate the effect to be described, and possibly to cracks in the substrate itself and thus in the conductor tracks and / or resistors and / or in the cover applied to the upper or lower side of the substrate and thus to Bond wire breaks.

Die in Fig. 3 dargestellte Anordnung nach der vorliegenden Erfindung weist ein Substrat 1 auf, auf dem mehrere Chips 3 unter einer Abdeckmasse 4 aufgebracht sind. The arrangement shown in FIG. 3 according to the present invention has a substrate 1, on which a plurality of chips 3 are applied under a covering compound 4.

In dieser Anordnung ist zusätzlich ein Deckel 5 aus dem gleichen oder bezüglich Wärmeausdehnung ähnlichen Material und mit einer ähnlichen Dicke wie das Substrat 1 vorgesehen. Durch eine derartige Sandwich-Anordnung können die oben beschriebenen Probleme gänzlich verhindert oder mindestens in erheblichem Masse reduziert werden. Durch den Deckel 5 werden vor allem die Biegekräfte eliminiert, so dass das Substrat flach bleibt. In this arrangement, a cover 5 is additionally provided made of the same or similar material with regard to thermal expansion and with a similar thickness as the substrate 1. With such a sandwich arrangement, the problems described above can be completely prevented or at least reduced to a considerable extent. Above all, the bending forces are eliminated by the cover 5, so that the substrate remains flat.

Versuche mit Keramiksubstraten und Keramikdeckeln nach der Erfindung haben deutlich gezeigt, dass eine solche Anordnung die Durchbiegung des Substrats praktisch vollkommen verhindert, auch wenn der Deckel dünner als das Substrat gewählt wird, was im Interesse einer möglichst geringen totalen Bauhöhe erwünscht sein kann. Im übrigen haben diese Versuche ebenfalls eine gute Temperatur-Wechselfestigkeit gezeigt. Experiments with ceramic substrates and ceramic lids according to the invention have clearly shown that such an arrangement practically completely prevents the substrate from bending, even if the lid is chosen to be thinner than the substrate, which may be desirable in the interest of the lowest possible overall height. Moreover, these tests have also shown good thermal shock resistance.

Im Fall eines Keramiksubstrats, das als Basis einer Dickfilmschaltung dient, kann der Deckel ebenfalls aus dem gleichen Keramikmaterial bestehen und gleichzeitig als Substrat für eine weitere Dickfilmschaltung, d.h. als Komponententräger verwendet werden. Die notwendigen elektrischen Verbindungen zwischen dem Basissubstrat und der Dek-kel-Elektronik können über federnde Anschlussbeine sichergestellt werden, die gleichzeitig dafür sorgen, dass der Deckel parallel auf der Abdeckmasse aufsitzt. Eine solche Anordnung ist in Fig. 4 dargestellt, wobei der Deckel 5, diesmal als Hilfssubstrat ausgebildet, wiederum Leiterbahnen und gegebenenfalls Widerstände 6 trägt und mit weiteren, beispielsweise umhüllten, Komponenten 7 bestückt ist. In the case of a ceramic substrate serving as the base of a thick film circuit, the lid can also consist of the same ceramic material and at the same time as a substrate for a further thick film circuit, i.e. can be used as a component carrier. The necessary electrical connections between the base substrate and the cover electronics can be ensured via resilient connecting legs, which at the same time ensure that the cover sits in parallel on the covering compound. Such an arrangement is shown in FIG. 4, the cover 5, this time designed as an auxiliary substrate, again carrying conductor tracks and possibly resistors 6 and being equipped with further, for example encased, components 7.

Eine in Fig. 4 nur schematisch dargestellte An-schluss-Struktur 8 sorgt für die elektrische Verbindung der Leiterbahnebene 6 des Hilfssubstrats mit der Leiterbahnebene 9 des Hauptsubstrats. A connection structure 8 shown only schematically in FIG. 4 ensures the electrical connection of the conductor track level 6 of the auxiliary substrate to the conductor track level 9 of the main substrate.

Eine andere Variante einer solchen Anordnung ist in Fig. 5 dargestellt, bei der die Verbindung zwischen den beiden Leiterbahnebenen durch eine Leiterbahnfolie 11, beispielsweise aus Polyamid mit Cu-Leiterbahnen, realisiert ist, die auf das Substrat 1 auflaminiert ist und als Träger und Verbindungsebene der Chips dient. Die Verbindung der Leiter5 Another variant of such an arrangement is shown in FIG. 5, in which the connection between the two interconnect levels is realized by an interconnect film 11, for example made of polyamide with Cu interconnects, which is laminated onto the substrate 1 and as a carrier and connection level Serves chips. The connection of the conductors 5

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CH 686 017 A5 CH 686 017 A5

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bahnebenen 6 und 9 geschieht dadurch, dass sie mit diesen Leiterbahnebenen entweder durch Lötkontakte, beispielsweise mit der Leiterbahn 6, oder durch Wire-bonding, beispielsweise mit der Leiterbahnebene 9 elektrisch verbunden ist, und zwar gemäss Fig. 5 beispielsweise dadurch, dass die elektrischen Verbindungen durch die Leiterbahnfolie unter den Chips durchgeführt werden. Track levels 6 and 9 occur in that they are electrically connected to these track levels either by solder contacts, for example to track 6, or by wire-bonding, for example to track level 9, according to FIG. 5, for example, in that the electrical connections through the trace foil under the chips.

Anstatt eine zweite Elektronik-Trägerebene zu bilden, kann der Deckel 5, wie in Fig. 6 dargestellt, auch als ein zusätzliches Wärmeabieitungs-Element ausgebildet sein, indem er mit Kühllamellen oder einem Kühlkörper 10 versehen ist. Instead of forming a second electronics support level, the cover 5, as shown in FIG. 6, can also be designed as an additional heat dissipation element by being provided with cooling fins or a heat sink 10.

Eine weitere Möglichkeit besteht gemäss Fig. 7 darin, den Deckel 5, z.B. mit einer gitterförmigen oder durchgehenden Metallisierung 13 und gegebenenfalls auch das Substrat mit einer ebensolchen auf seiner oberen oder, wie in Fig. 7 dargestellt, unteren Seite zu versehen, um die Anordnung als Faraday-Käfig auszubilden, so dass elektrische Streufelder bzw. elektromagnetische Interferenzen verhindert werden. Another possibility according to Fig. 7 is to cover 5, e.g. with a lattice-shaped or continuous metallization 13 and, if appropriate, also to provide the substrate with the same on its upper or, as shown in FIG. 7, lower side, in order to form the arrangement as a Faraday cage, so that electrical stray fields or electromagnetic interference is prevented become.

Bei der Anordnung gemäss Fig. 4 ist durch die Anschlussstruktur 8 eine geeignete Distanzierung des Deckels gegeben, die aber eine genügend grosse Federwirkung hat, damit der Deckel durch die Benetzung mit der Abdeckmasse auf dieser «schwimmen» kann. In the arrangement according to FIG. 4, the connection structure 8 provides a suitable spacing of the cover, which, however, has a sufficiently great spring effect so that the cover can “float” on the cover compound when wetted.

Die Fig. 8 und 9 zeigen eine andere Möglichkeit, dies zu erreichen, und zwar durch Verwendung eines vorgefertigten Rahmens 14 aus Kautschuk, Silikon oder einem anderen elastischen Material, der als seitliche Begrenzung der Abdeckmasse und als Distanzhalter zwischen dem Substrat 1 und dem Deckel 5 dient. Gezeigt ist der Fall, dass eine, z.B. aus dem Foliensubstrat bestehende Multichip-Insel 11, auf dem die Chips 3 montiert und gebondet sind, ganz vom Rahmen, der z.B. als Toroid-Ring ausgebildet ist, umschlossen ist. Durch eine genaue Dosierung der Abdeckmasse kann sichergestellt werden, dass der Zwischenraum zwischen Substrat und Deckel vollkommen mit dieser Abdeckmasse gefüllt wird. Die elektrische Verbindung zwischen der Multichip-Insel und dem Rest des Substrates kann z.B. gemäss Fig. 8 durch Wire-bonding von der Inselmetallisierung auf die Substratmetallisierung oder gemäss Fig. 9 durch Lötverbindungen zwischen Inselmetallisierung und Substratmetallisierung erfolgen. 8 and 9 show another way of achieving this, namely by using a prefabricated frame 14 made of rubber, silicone or another elastic material, which acts as a lateral limitation of the covering compound and as a spacer between the substrate 1 and the lid 5 serves. The case is shown that a e.g. multichip island 11 consisting of the film substrate, on which the chips 3 are mounted and bonded, entirely from the frame, e.g. is designed as a toroid ring, is enclosed. Precise metering of the masking compound can ensure that the space between the substrate and cover is completely filled with this masking compound. The electrical connection between the multichip island and the rest of the substrate can e.g. 8 by wire bonding from the island metallization to the substrate metallization or according to FIG. 9 by solder connections between island metallization and substrate metallization.

Als Beispiele für die verwendeten Materialien und die entsprechenden Wärme-Ausdehnungskoeffizien-ten (in 10~6/°K) seien erwähnt: The following are examples of the materials used and the corresponding thermal expansion coefficients (in 10 ~ 6 / ° K):

für die Abdeckung: Epoxy 20-25 oder Silikon ca for the cover: epoxy 20-25 or silicone approx

50 50

für den Chip: Silizium 4 for the chip: silicon 4

für das Substrat: Keramik 6.7 oder Print (FR4) 17-18 for the substrate: ceramic 6.7 or print (FR4) 17-18

Der Deckel 5 kann vorzugsweise platten- oder scheibenförmig ausgebildet sein. The cover 5 can preferably be plate-shaped or disk-shaped.

Die Metallisierung 9 (Fig. 1) kann bei Printsubstraten ein Kupferlaminat sein. The metallization 9 (FIG. 1) can be a copper laminate in the case of print substrates.

Claims (10)

PatentansprücheClaims 1. Anordnung mit einem Substrat und mindestens einem Chip, der in einer Abdeckmasse eingebettet ist, dadurch gekennzeichnet, dass an der freien Oberfläche der Abdeckmasse (4) ein Deckel angeordnet ist, der einen ähnlichen Wärmeausdehnungskoeffizienten wie das Substrat aufweist.1. Arrangement with a substrate and at least one chip which is embedded in a covering compound, characterized in that a cover is arranged on the free surface of the covering compound (4), which has a similar coefficient of thermal expansion as the substrate. 2. Anordnung nach Anspruch 1, dadurch gekennzeichnet, dass der Deckel (5) durch eine Verbin-dungs-Struktur (8) mit dem Substrat (1) verbunden ist.2. Arrangement according to claim 1, characterized in that the cover (5) is connected to the substrate (1) by a connection structure (8). 3. Anordnung nach Anspruch 2, dadurch gekennzeichnet, dass der Deckel (5) als Hilfssubstrat ausgebildet, mit Leiterbahnen versehen und mit mindestens einer Komponente (7) bestückt ist.3. Arrangement according to claim 2, characterized in that the cover (5) is designed as an auxiliary substrate, is provided with conductor tracks and is equipped with at least one component (7). 4. Anordnung nach Anspruch 3, dadurch gekennzeichnet, dass die Verbindungs-Struktur (8) zugleich als eine elektrisch leitende Anschluss-Struktur für die mindestens eine Komponente (7) dient.4. Arrangement according to claim 3, characterized in that the connection structure (8) also serves as an electrically conductive connection structure for the at least one component (7). 5. Anordnung nach Anspruch 2, dadurch gekennzeichnet, dass die Verbindungs-Struktur mindestens eine Leiterbahnfolie (11) umfasst.5. Arrangement according to claim 2, characterized in that the connection structure comprises at least one conductor track film (11). 6. Anordnung nach Anspruch 5, dadurch gekennzeichnet, dass die mindestens eine Leiterbahnfolie (11) unter den Chip (3) geführt ist.6. Arrangement according to claim 5, characterized in that the at least one conductor foil (11) is guided under the chip (3). 7. Anordnung nach einem der Ansprüche 2 bis 6, dadurch gekennzeichnet, dass die Verbindungs-Struktur (8) zugleich als Halterung dient, um den Deckel (5) in einem vorbestimmten Abstand parallel zum Substrat (1) zu halten.7. Arrangement according to one of claims 2 to 6, characterized in that the connecting structure (8) also serves as a holder to hold the lid (5) parallel to the substrate (1) at a predetermined distance. 8. Anordnung nach einem der Ansprüche 1 bis 7, dadurch gekennzeichnet, dass der Deckel (5) ein Wärmeableitungs-Element (10) trägt.8. Arrangement according to one of claims 1 to 7, characterized in that the cover (5) carries a heat dissipation element (10). 9. Anordnung nach einem der Ansprüche 1 bis 8, dadurch gekennzeichnet, dass der Deckel (5) eine geerdete Metallisierung (13) aufweist.9. Arrangement according to one of claims 1 to 8, characterized in that the cover (5) has a grounded metallization (13). 10. Anordnung nach einem der Ansprüche 2 bis 9, dadurch gekennzeichnet, dass die Verbindungs-Struktur durch einen elastischen Ring (14) als Distanzhalter gebildet ist.10. Arrangement according to one of claims 2 to 9, characterized in that the connecting structure is formed by an elastic ring (14) as a spacer. 55 1010th 1515 2020th 2525th 3030th 3535 4040 4545 5050 5555 6060 6565 33rd
CH117493A 1993-04-16 1993-04-16 Device comprising a substrate and at least one chip. CH686017A5 (en)

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CH117493A CH686017A5 (en) 1993-04-16 1993-04-16 Device comprising a substrate and at least one chip.
DE4411210A DE4411210A1 (en) 1993-04-16 1994-03-31 Arrangement having a substrate and at least one chip

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DE19518027C2 (en) * 1995-05-17 1997-05-15 Lust Hybrid Technik Gmbh Process for the precise spacing encasing of components provided with functional layers and components produced thereafter
JPH11102985A (en) 1997-09-26 1999-04-13 Mitsubishi Electric Corp Semiconductor integrated circuit device
DE10230304A1 (en) * 2002-07-05 2004-01-15 Valeo Schalter Und Sensoren Gmbh Method of manufacturing an electronic circuit and electronic circuit
DE102006011753B4 (en) 2006-03-13 2021-01-28 Infineon Technologies Ag Semiconductor sensor component, method for producing a panel and method for producing semiconductor sensor components
DE102008043517B4 (en) 2008-11-06 2022-03-03 Robert Bosch Gmbh Sensor module and method for manufacturing a sensor module

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JPH02155256A (en) * 1988-12-08 1990-06-14 Mitsubishi Electric Corp Semiconductor device
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