CH616013A5 - - Google Patents

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Publication number
CH616013A5
CH616013A5 CH519877A CH519877A CH616013A5 CH 616013 A5 CH616013 A5 CH 616013A5 CH 519877 A CH519877 A CH 519877A CH 519877 A CH519877 A CH 519877A CH 616013 A5 CH616013 A5 CH 616013A5
Authority
CH
Switzerland
Prior art keywords
register
stage
level
processor
active
Prior art date
Application number
CH519877A
Other languages
German (de)
English (en)
Inventor
Michael Ian Davis
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of CH616013A5 publication Critical patent/CH616013A5/de

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806Task transfer initiation or dispatching
    • G06F9/4843Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/461Saving or restoring of program or task context
    • G06F9/462Saving or restoring of program or task context with multiple register sets

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Hardware Redundancy (AREA)
  • Storage Device Security (AREA)
  • Multi Processors (AREA)
CH519877A 1976-04-30 1977-04-27 CH616013A5 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/681,953 US4047161A (en) 1976-04-30 1976-04-30 Task management apparatus

Publications (1)

Publication Number Publication Date
CH616013A5 true CH616013A5 (ja) 1980-02-29

Family

ID=24737563

Family Applications (1)

Application Number Title Priority Date Filing Date
CH519877A CH616013A5 (ja) 1976-04-30 1977-04-27

Country Status (13)

Country Link
US (1) US4047161A (ja)
JP (1) JPS52133740A (ja)
AU (1) AU506941B2 (ja)
BE (1) BE852992A (ja)
BR (1) BR7702818A (ja)
CH (1) CH616013A5 (ja)
DE (1) DE2718051C3 (ja)
ES (1) ES458323A1 (ja)
FR (1) FR2349884A1 (ja)
GB (1) GB1557119A (ja)
IT (1) IT1115278B (ja)
NL (1) NL7704653A (ja)
SE (1) SE417552B (ja)

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US4442484A (en) * 1980-10-14 1984-04-10 Intel Corporation Microprocessor memory management and protection mechanism
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US4939640A (en) * 1981-05-22 1990-07-03 Data General Corporation Data processing system having unique microinstruction control and stack means
US4445190A (en) * 1981-06-16 1984-04-24 International Business Machines Corporation Program identification encoding
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US4680698A (en) * 1982-11-26 1987-07-14 Inmos Limited High density ROM in separate isolation well on single with chip
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US4661900A (en) * 1983-04-25 1987-04-28 Cray Research, Inc. Flexible chaining in vector processor with selective use of vector registers as operand and result registers
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US4754398A (en) * 1985-06-28 1988-06-28 Cray Research, Inc. System for multiprocessor communication using local and common semaphore and information registers
US4745545A (en) * 1985-06-28 1988-05-17 Cray Research, Inc. Memory reference control in a multiprocessor
JPH0792782B2 (ja) * 1985-09-30 1995-10-09 富士通株式会社 処理実行システム
US4837688A (en) * 1986-07-25 1989-06-06 International Business Machines Corporation Multi-channel shared resource processor
DE3750171T2 (de) * 1986-08-28 1995-02-02 Nippon Electric Co Multiaufgabenverarbeitungsgerät.
US5764922A (en) * 1986-11-04 1998-06-09 Unisys Corporation I/O system for off-loading operating system functions
JPS63170736A (ja) * 1987-01-09 1988-07-14 Toshiba Corp マイクロプロセツサ
US4805096A (en) * 1987-03-06 1989-02-14 Eta Systems, Inc. Interrupt system
US5012409A (en) * 1988-03-10 1991-04-30 Fletcher Mitchell S Operating system for a multi-tasking operating environment
US5025369A (en) * 1988-08-25 1991-06-18 David Schwartz Enterprises, Inc. Computer system
US5142638A (en) * 1989-02-07 1992-08-25 Cray Research, Inc. Apparatus for sharing memory in a multiprocessor system
US5247671A (en) * 1990-02-14 1993-09-21 International Business Machines Corporation Scalable schedules for serial communications controller in data processing systems
US5301330A (en) * 1990-10-12 1994-04-05 Advanced Micro Devices, Inc. Contention handling apparatus for generating user busy signal by logically summing wait output of next higher priority user and access requests of higher priority users
JP2561801B2 (ja) * 1993-02-24 1996-12-11 インターナショナル・ビジネス・マシーンズ・コーポレイション プロセス・スケジューリングの管理方法およびシステム
JP2521027B2 (ja) * 1993-08-27 1996-07-31 インターナショナル・ビジネス・マシーンズ・コーポレイション マルチプロセッサ及びその制御方法
US5987601A (en) * 1997-02-14 1999-11-16 Xyron Corporation Zero overhead computer interrupts with task switching
US6105051A (en) * 1997-10-23 2000-08-15 International Business Machines Corporation Apparatus and method to guarantee forward progress in execution of threads in a multithreaded processor
US6697935B1 (en) * 1997-10-23 2004-02-24 International Business Machines Corporation Method and apparatus for selecting thread switch events in a multithreaded processor
US6567839B1 (en) 1997-10-23 2003-05-20 International Business Machines Corporation Thread switch control in a multithreaded processor system
US6212544B1 (en) 1997-10-23 2001-04-03 International Business Machines Corporation Altering thread priorities in a multithreaded processor
US6076157A (en) * 1997-10-23 2000-06-13 International Business Machines Corporation Method and apparatus to force a thread switch in a multithreaded processor
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US7093260B1 (en) 2000-05-04 2006-08-15 International Business Machines Corporation Method, system, and program for saving a state of a task and executing the task by a processor in a multiprocessor system
JP2002182927A (ja) * 2000-12-13 2002-06-28 Hitachi Ltd 異種実行環境におけるレジスタの割当て方法、異種実行環境におけるソフトウェア開発方法、および、それを実行するプログラムが組み込まれたlsi
SG132507A1 (en) * 2001-02-16 2007-06-28 Sony Corp Data processing method and its apparatus
US20030014474A1 (en) * 2001-05-30 2003-01-16 Mckaig Ray S. Alternate zero overhead task change circuit
US20040172631A1 (en) * 2001-06-20 2004-09-02 Howard James E Concurrent-multitasking processor
US7178147B2 (en) * 2001-09-21 2007-02-13 International Business Machines Corporation Method, system, and program for allocating processor resources to a first and second types of tasks
US20050015768A1 (en) * 2002-12-31 2005-01-20 Moore Mark Justin System and method for providing hardware-assisted task scheduling
WO2004061662A2 (en) * 2002-12-31 2004-07-22 Globespanvirata Incorporated System and method for providing balanced thread scheduling
US7739685B2 (en) * 2005-01-06 2010-06-15 International Business Machines Corporation Decoupling a central processing unit from its tasks
US7996595B2 (en) * 2009-04-14 2011-08-09 Lstar Technologies Llc Interrupt arbitration for multiprocessors
US8321614B2 (en) * 2009-04-24 2012-11-27 Empire Technology Development Llc Dynamic scheduling interrupt controller for multiprocessors
US8260996B2 (en) * 2009-04-24 2012-09-04 Empire Technology Development Llc Interrupt optimization for multiprocessors
DE102009030372A1 (de) 2009-06-25 2010-12-30 Schaeffler Technologies Gmbh & Co. Kg Am Kreuzgelenkzapfen befestigte Lagerbüchsendichtung
US8234431B2 (en) * 2009-10-13 2012-07-31 Empire Technology Development Llc Interrupt masking for multi-core processors
CN112784261B (zh) * 2021-01-04 2023-10-27 北京蓝军网安科技发展有限责任公司 用于程序运行的方法及相应的***、计算机设备和介质
US11792135B2 (en) 2022-03-07 2023-10-17 Bank Of America Corporation Automated process scheduling in a computer network
US11922161B2 (en) 2022-03-07 2024-03-05 Bank Of America Corporation Scheduling a pausable automated process in a computer network
US20240054073A1 (en) * 2022-08-11 2024-02-15 Arm Limited Circuitry and Method
CN115858018B (zh) * 2023-02-27 2023-05-16 珠海星云智联科技有限公司 一种嵌入式***的自适应寄存器更新方法、设备及介质

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BE758813A (fr) * 1969-11-28 1971-04-16 Burroughs Corp Structures de programme pour la mise en oeuvre de systemes de traitement d'information, communes a des langages de programme de niveau plus eleve
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Also Published As

Publication number Publication date
US4047161A (en) 1977-09-06
NL7704653A (nl) 1977-11-01
GB1557119A (en) 1979-12-05
DE2718051C3 (de) 1981-11-26
FR2349884B1 (ja) 1980-06-27
DE2718051A1 (de) 1977-11-10
JPS5441458B2 (ja) 1979-12-08
BE852992A (fr) 1977-07-18
ES458323A1 (es) 1978-03-01
AU2474077A (en) 1978-11-09
AU506941B2 (en) 1980-01-31
SE417552B (sv) 1981-03-23
SE7704956L (sv) 1977-10-31
DE2718051B2 (de) 1981-04-09
FR2349884A1 (fr) 1977-11-25
IT1115278B (it) 1986-02-03
BR7702818A (pt) 1978-02-28
JPS52133740A (en) 1977-11-09

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Legal Events

Date Code Title Description
PL Patent ceased