CH319753A - A method of manufacturing an electric semiconductor device - Google Patents
A method of manufacturing an electric semiconductor deviceInfo
- Publication number
- CH319753A CH319753A CH319753DA CH319753A CH 319753 A CH319753 A CH 319753A CH 319753D A CH319753D A CH 319753DA CH 319753 A CH319753 A CH 319753A
- Authority
- CH
- Switzerland
- Prior art keywords
- manufacturing
- semiconductor device
- electric semiconductor
- electric
- semiconductor
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Weting (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US319753XA | 1952-10-20 | 1952-10-20 |
Publications (1)
Publication Number | Publication Date |
---|---|
CH319753A true CH319753A (en) | 1957-02-28 |
Family
ID=21862427
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CH319753D CH319753A (en) | 1952-10-20 | 1953-09-18 | A method of manufacturing an electric semiconductor device |
Country Status (5)
Country | Link |
---|---|
BE (1) | BE523638A (en) |
CH (1) | CH319753A (en) |
FR (1) | FR1088371A (en) |
GB (1) | GB735986A (en) |
NL (1) | NL182156B (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1093483B (en) * | 1958-06-04 | 1960-11-24 | Telefunken Gmbh | Method for producing semiconductor arrangements with two pn junctions, in particular silicon transistors, by fusing two semiconductor crystals |
DE1112585B (en) * | 1958-01-14 | 1961-08-10 | Philips Nv | Method for manufacturing semiconductor devices |
DE1133833B (en) * | 1958-12-24 | 1962-07-26 | Philco Corp | Hermetically sealed encapsulated semiconductor arrangement |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
BE532794A (en) * | 1953-10-26 | |||
NL110588C (en) * | 1955-03-10 | |||
NL278654A (en) * | 1961-06-08 |
-
0
- BE BE523638D patent/BE523638A/xx unknown
- NL NLAANVRAGE7810304,A patent/NL182156B/en unknown
-
1953
- 1953-08-29 FR FR1088371D patent/FR1088371A/en not_active Expired
- 1953-09-18 CH CH319753D patent/CH319753A/en unknown
- 1953-09-23 GB GB26233/53A patent/GB735986A/en not_active Expired
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1112585B (en) * | 1958-01-14 | 1961-08-10 | Philips Nv | Method for manufacturing semiconductor devices |
DE1093483B (en) * | 1958-06-04 | 1960-11-24 | Telefunken Gmbh | Method for producing semiconductor arrangements with two pn junctions, in particular silicon transistors, by fusing two semiconductor crystals |
DE1133833B (en) * | 1958-12-24 | 1962-07-26 | Philco Corp | Hermetically sealed encapsulated semiconductor arrangement |
Also Published As
Publication number | Publication date |
---|---|
FR1088371A (en) | 1955-03-07 |
NL182156B (en) | |
BE523638A (en) | |
GB735986A (en) | 1955-08-31 |
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