CA2682092A1 - And-type one time programmable memory cell - Google Patents
And-type one time programmable memory cell Download PDFInfo
- Publication number
- CA2682092A1 CA2682092A1 CA 2682092 CA2682092A CA2682092A1 CA 2682092 A1 CA2682092 A1 CA 2682092A1 CA 2682092 CA2682092 CA 2682092 CA 2682092 A CA2682092 A CA 2682092A CA 2682092 A1 CA2682092 A1 CA 2682092A1
- Authority
- CA
- Canada
- Prior art keywords
- memory cell
- voltage level
- channel region
- fuse
- otp memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
Abstract
An AND-type anti-fuse memory cell, and a memory array consisting of AND-type anti-fuse memory cells. Chains of AND type anti-fuse cells are connected in series wit h each other, and with a bitline contact, in order to minimize the area occupied by the memory array. Each AND type anti-fuse cell includes an access transistor serially connectable t o the bitline or the access transistors of other AND type anti-fuse cells, and an anti-fuse devic e. The channel region of the access transistor is connected to the channel region of the an ti- fuse device, and both channel regions are covered by the same wordline. The wordline is drive n to a programming voltage level for programming the anti-fuse device, or to a read voltage level for reading the anti-fuse device.
Claims (28)
1. An anti-fuse memory cell comprising:
an access transistor having a first channel region having a first channel length dimension, and adjacent to a diffusion region;
an anti-fuse device having a second channel region having a second channel length dimension perpendicular to the first channel length dimension, and connected to the first channel region; and a wordline overlying the first channel region and the second channel region.
an access transistor having a first channel region having a first channel length dimension, and adjacent to a diffusion region;
an anti-fuse device having a second channel region having a second channel length dimension perpendicular to the first channel length dimension, and connected to the first channel region; and a wordline overlying the first channel region and the second channel region.
2. The anti-fuse memory cell of claim 1, wherein the diffusion region is connected to one of a bitline and another access transistor corresponding to an adjacent anti-fuse memory cell.
3. The anti-fuse memory cell of claim 1, wherein the access transistor includes a thick gate oxide between the wordline and the first channel region.
4. The anti-fuse memory cell of claim 3, wherein the anti-fuse device has a variable thickness gate oxide, and a thick portion of the variable thickness gate oxide is adjacent to the thick gate oxide of the access transistor.
5. The anti-fuse memory cell of claim 4, wherein the thick portion of the variable thickness gate oxide has a thickness substantially identical to the thick gate oxide.
6. The anti-fuse memory cell of claim 1, wherein the wordline extends in a first direction, and the first channel length of the first channel region extends perpendicular to the wordline.
7. The anti-fuse memory cell of claim 6, wherein the second channel length of the second channel region extends parallel to the wordline and has a width extending perpendicular to the wordline.
8. The anti-fuse memory cell of claim 7, wherein the width of the second channel region is less than the length of the first channel region.
9. The anti-fuse memory cell of claim 8, wherein field oxide isolates the second channel region from another second channel region corresponding to the adjacent anti-fuse memory cell.
10. A memory array comprising:
a plurality of memory chains connected in parallel to a bitline, each of the memory chains including at least two one time programmable memory cells connected in series with a bitline contact corresponding to the bitline; and, wordlines coupled to the at least two one time programmable memory cells, the wordlines being drivable during a memory operation.
a plurality of memory chains connected in parallel to a bitline, each of the memory chains including at least two one time programmable memory cells connected in series with a bitline contact corresponding to the bitline; and, wordlines coupled to the at least two one time programmable memory cells, the wordlines being drivable during a memory operation.
11. The one time programmable memory array of claim 10, wherein the memory operation includes one of a read operation and a program operation.
12. The one time programmable memory array of claim 10, wherein each of the at least two one time programmable memory cells includes an access transistor having a first channel region adjacent to a diffusion region;
an anti-fuse device having a second channel region connected to the first channel region, the first channel region and the second channel region underlying one of the wordlines.
an anti-fuse device having a second channel region connected to the first channel region, the first channel region and the second channel region underlying one of the wordlines.
13. The anti-fuse memory cell of claim 12, wherein the wordlines extend in a first direction, and the first channel region has a length extending perpendicular to the wordlines.
14. The anti-fuse memory cell of claim 13, wherein the second channel region has a length extending parallel to the wordlines and a width extending perpendicular to the wordlines.
15. A method for executing a memory operation on series connected one time programmable memory cells, comprising:
a) biasing a bitline contact connected to the series connected one time programmable (OTP) memory cells to a voltage level;
b) coupling the voltage level to a selected OTP memory cell of the series connected OTP memory cells; and c) driving a wordline connected to a selected OTP memory cell to a predetermined voltage level.
a) biasing a bitline contact connected to the series connected one time programmable (OTP) memory cells to a voltage level;
b) coupling the voltage level to a selected OTP memory cell of the series connected OTP memory cells; and c) driving a wordline connected to a selected OTP memory cell to a predetermined voltage level.
16. The method of claim 15, wherein coupling includes turning on intermediate OTP memory cells connected between the selected OTP memory cell and the bitline contact.
17. The method of claim 16, further including turning off any tail OTP memory cells connected between the selected OTP memory cell and a last OTP memory cell positioned most distant from the bitline contact.
18. The method of claim 16, wherein turning on includes driving wordlines connected to the intermediate OTP memory cells to a pass voltage level effective for passing the voltage level to the selected OTP memory cell.
19. The method of claim 18, wherein the memory operation includes a programming operation.
20. The method of claim 19, wherein the series connected OTP memory cells are programmed sequentially from the selected OTP memory cell to a first OTP
memory cell adjacent to the bitline contact.
memory cell adjacent to the bitline contact.
21. The method of claim 20, wherein the selected OTP memory cell is a last OTP
memory cell most distant from the bitline.
memory cell most distant from the bitline.
22. The method of claim 19, wherein the predetermined voltage level is a programming voltage level, and the voltage level of the bitline contact can be an inhibit voltage to prevent programming of the selected OTP memory cell or an enable voltage to facilitate programming of the selected OTP memory cell.
23. The method of claim 22, wherein the pass voltage level is equal to or greater than both the inhibit voltage and the enable voltage, and less than the programming voltage level.
24. The method of claim 22, wherein the pass voltage level is maintained while the enable voltage is applied to the selected OTP memory cell.
25. The method of claim 22, wherein the pass voltage level is greater than a threshold voltage of an access transistor of the intermediate OTP memory cells and less than the programming voltage level.
26. The method of claim 18, wherein the memory operation includes a read operation.
27. The method of claim 18, wherein the predetermined voltage level is a read voltage level, and the voltage level of the bitline contact is precharged to a first voltage level corresponding to a first logic state.
28. The method of claim 27, wherein the pass voltage level is less than the read voltage level and less than a threshold voltage of a programmed memory cell.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA2682092A CA2682092C (en) | 2009-10-30 | 2009-10-30 | And-type one time programmable memory cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA2682092A CA2682092C (en) | 2009-10-30 | 2009-10-30 | And-type one time programmable memory cell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2682092A1 true CA2682092A1 (en) | 2010-01-05 |
| CA2682092C CA2682092C (en) | 2010-11-02 |
Family
ID=41508489
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2682092A Active CA2682092C (en) | 2009-10-30 | 2009-10-30 | And-type one time programmable memory cell |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA2682092C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015149182A1 (en) * | 2014-04-03 | 2015-10-08 | Sidense Corporation | Anti-fuse memory cell |
| CN115910990A (en) * | 2023-02-23 | 2023-04-04 | 长鑫存储技术有限公司 | Anti-fuse structure and preparation method thereof |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9123572B2 (en) | 2004-05-06 | 2015-09-01 | Sidense Corporation | Anti-fuse memory cell |
| CA2952941C (en) * | 2016-01-08 | 2018-12-11 | Sidense Corp. | Puf value generation using an anti-fuse memory array |
-
2009
- 2009-10-30 CA CA2682092A patent/CA2682092C/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015149182A1 (en) * | 2014-04-03 | 2015-10-08 | Sidense Corporation | Anti-fuse memory cell |
| CN115910990A (en) * | 2023-02-23 | 2023-04-04 | 长鑫存储技术有限公司 | Anti-fuse structure and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CA2682092C (en) | 2010-11-02 |
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| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request |