CA2392445A1 - Couche de silicium tres sensible a l'oxygene et procede d'obtention de cette couche - Google Patents

Couche de silicium tres sensible a l'oxygene et procede d'obtention de cette couche Download PDF

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Publication number
CA2392445A1
CA2392445A1 CA002392445A CA2392445A CA2392445A1 CA 2392445 A1 CA2392445 A1 CA 2392445A1 CA 002392445 A CA002392445 A CA 002392445A CA 2392445 A CA2392445 A CA 2392445A CA 2392445 A1 CA2392445 A1 CA 2392445A1
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CA
Canada
Prior art keywords
oxygen
silicon layer
highly sensitive
obtaining same
layer highly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002392445A
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English (en)
Other versions
CA2392445C (fr
Inventor
Fabrice Amy
Christian Brylinski
Gerald Dujardin
Hanna Enriquez
Andrew Mayne
Patrick Soukiassian
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Individual
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Publication date
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Publication of CA2392445A1 publication Critical patent/CA2392445A1/fr
Application granted granted Critical
Publication of CA2392445C publication Critical patent/CA2392445C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02609—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048—Making electrodes
    • H01L21/049—Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Silicon Compounds (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Carbon And Carbon Compounds (AREA)

Abstract

Cette couche (2), formée sur un substrat (4) par exemple en SiC, a une structure de surface 4×3. Pour l'obtenir, on dépose de façon sensiblement uniforme du silicium sur une surface du substrat.
L'invention s'applique par exemple en microélec-tronique.
CA002392445A 1999-11-25 2000-11-27 Couche de silicium tres sensible a l'oxygene et procede d'obtention de cette couche Expired - Fee Related CA2392445C (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR99/14846 1999-11-25
FR9914846A FR2801723B1 (fr) 1999-11-25 1999-11-25 Couche de silicium tres sensible a l'oxygene et procede d'obtention de cette couche
PCT/FR2000/003304 WO2001039257A2 (fr) 1999-11-25 2000-11-27 Couche de silicium tres sensible a l'oxygene et procede d'obtention de cette couche

Publications (2)

Publication Number Publication Date
CA2392445A1 true CA2392445A1 (fr) 2001-05-31
CA2392445C CA2392445C (fr) 2009-06-02

Family

ID=9552537

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002392445A Expired - Fee Related CA2392445C (fr) 1999-11-25 2000-11-27 Couche de silicium tres sensible a l'oxygene et procede d'obtention de cette couche

Country Status (6)

Country Link
US (1) US6667102B1 (fr)
EP (1) EP1232521A2 (fr)
JP (1) JP4880156B2 (fr)
CA (1) CA2392445C (fr)
FR (1) FR2801723B1 (fr)
WO (1) WO2001039257A2 (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2823770B1 (fr) 2001-04-19 2004-05-21 Commissariat Energie Atomique Procede de traitement de la surface d'un materiau semiconducteur, utilisant notamment l'hydrogene, et surface obtenue par ce procede
FR2823739B1 (fr) * 2001-04-19 2003-05-16 Commissariat Energie Atomique Procede de fabrication de nanostructures unidimensionnelles et nanostructures obtenues par ce procede
JP4029595B2 (ja) * 2001-10-15 2008-01-09 株式会社デンソー ＳｉＣ半導体装置の製造方法
FR2841892B1 (fr) * 2002-07-05 2005-05-06 Commissariat Energie Atomique Nano-objets metalliques, formes sur des surfaces de carbure de silicium, et procede de fabrication de ces nano-objets
FR2871936B1 (fr) * 2004-06-21 2006-10-06 Commissariat Energie Atomique Procede de metallisation de la surface prealablement passivee d'un materiau semi conducteur et materiau obtenu par ce procede
JP2006216918A (ja) * 2005-02-07 2006-08-17 Kyoto Univ 半導体素子の製造方法
WO2007003576A1 (fr) * 2005-06-30 2007-01-11 Commissariat A L'energie Atomique Nanostructures a resistance differentielle negative et leur procede de fabrication
FR2888398B1 (fr) * 2005-07-05 2007-12-21 Commissariat Energie Atomique Couche de silicium tres sensible a l'oxygene et procede d'obtention de cette couche
FR2888399B1 (fr) * 2005-07-05 2008-03-14 Commissariat Energie Atomique Substrat, notamment en carbure de silicium, recouvert par une couche mince de nitrure de silicium stoechiometrique, pour la fabrication de composants electroniques, et procede d'obtention d'une telle couche
JP5141227B2 (ja) * 2007-12-12 2013-02-13 住友電気工業株式会社 半導体装置の製造方法
GB2483702A (en) * 2010-09-17 2012-03-21 Ge Aviat Systems Ltd Method for the manufacture of a Silicon Carbide, Silicon Oxide interface having reduced interfacial carbon gettering
JP2013008894A (ja) * 2011-06-27 2013-01-10 Saitama Univ 炭化珪素半導体を用いたｍｏｓ構造およびその酸化膜形成方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6066866A (ja) * 1983-09-24 1985-04-17 Sharp Corp 炭化珪素ｍｏｓ構造の製造方法
US5459107A (en) * 1992-06-05 1995-10-17 Cree Research, Inc. Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures
JPH07172997A (ja) * 1993-12-16 1995-07-11 Matsushita Electric Ind Co Ltd 炭化珪素薄膜の製造方法及び製造装置
EP0845803A4 (fr) * 1996-04-18 2002-03-27 Matsushita Electric Ind Co Ltd ELEMENT EN SiC ET SON PROCEDE DE PRODUCTION
FR2757183B1 (fr) 1996-12-16 1999-02-05 Commissariat Energie Atomique Fils atomiques de grande longueur et de grande stabilite, procede de fabrication de ces fils, application en nano-electronique
JP3143670B2 (ja) * 1997-08-13 2001-03-07 工業技術院長 酸化薄膜形成方法

Also Published As

Publication number Publication date
CA2392445C (fr) 2009-06-02
FR2801723B1 (fr) 2003-09-05
JP2003515517A (ja) 2003-05-07
WO2001039257A2 (fr) 2001-05-31
WO2001039257A3 (fr) 2001-12-13
US6667102B1 (en) 2003-12-23
EP1232521A2 (fr) 2002-08-21
FR2801723A1 (fr) 2001-06-01
JP4880156B2 (ja) 2012-02-22

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Effective date: 20141127