CA1328929C - Serial data interface - Google Patents
Serial data interfaceInfo
- Publication number
- CA1328929C CA1328929C CA000609662A CA609662A CA1328929C CA 1328929 C CA1328929 C CA 1328929C CA 000609662 A CA000609662 A CA 000609662A CA 609662 A CA609662 A CA 609662A CA 1328929 C CA1328929 C CA 1328929C
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- Canada
- Prior art keywords
- data
- circuit
- line
- storage cells
- reset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
- G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
- Communication Control (AREA)
- Arrangements For Transmission Of Measured Signals (AREA)
- Circuits Of Receivers In General (AREA)
- Ultra Sonic Daignosis Equipment (AREA)
- Vehicle Body Suspensions (AREA)
- Radar Systems Or Details Thereof (AREA)
- Selective Calling Equipment (AREA)
- Dram (AREA)
- Bus Control (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
Abstract of the Disclosure An interface circuit, for providing data from a data bus to one of a plurality of peripheral circuits coupled to said data bus, examines the bit length of respective datawords provided to the data bus. Only if the bit length of a particular dataword matches a bit length programmed into the interface, will the dataword be coupled to the peripheral circuit. Provision is also made to detect minimal address codes which may be appended to the datawords.
Description
This inventlon relates to a serial data interface for the connection of a known data bus to a peripheral circuit, wherein a plurality of peripheral circuits are connected to a corresponding plurality of data interfaces and the data bus includes a data llne, an enable llne and a clock pulse line.
Backqround of the Invention Serial data interface clrcuits are used to connect peripheral circuits, which receive or transmit data via a data bus, to said data bus. A data transmisslon by means of a bi-directional data bus i~ described in the D~-OS 34 04 721. The serial data interface circuits must evaluate the data flow running through the data bus using characteristics which allow recognition of the allocation to the specific peripheral circuit connected.
There are at least two general types of bus/interface systems. In the firæt type of system the interface circuit is designed to pass information from a common bus to its corresponding peripheral circuit only after xecognizing a particular address signal applied to the bus. In the second type of system the interface circuit is designed to pass information to its corresponding peripheral circuit according to a predetermined priority of a transmitted sequence of lnformation packets. In the first system the bus structure is burdened with address signals, and the amount of information that may be conveyed on the bus is reduced due to the time required for address identification. In the second type of a system, in general a particular interface cannot be accessed rapidly since the bus~interface system must step through the appropriate priority sequence.
It is an ob~ect of this ~nvention to provide an interface system having rapid data access and capable of greater information transfer.
Summar~ of the Invention The present invention is characterised by: a data store connected to the data line for the surceæsive storage of data words of equal or different word lengths transmitted over the data line; a comparison circuit, which detects addresses for peripheral circuits that are possibly present in the data words and compares ~2C
1~2~929 them with the addres~ of the currently connected peripheral circuit, connected to the data store; a control circuit, which : compares the word length~ of the data words with a predefined word length and then, taking into account the slgnals transmitted on the enable line, only allows a further transfer of the data words to the connected peripheral circuit if the two word length~ are equal, connected to the comparison circuit an internal clock pulse generator, which supplies the data store, the comparison : circuit and the control circuit with clock pulse slgnals, connected to the enable llne and to the clock pulse line; an internal set/reset circuit connected to the enable line and to the clock pulse line, whose outputs are connected to set and/or reset - inputs of the data store, the comparison circuit and the control circuit and emits to these outputs corresponding set and/or re~et : commands which are generated either by an external reset signal or by means of a combination of signals transmitted on the enable line and on the clock pulse line.
v~ Brief Descri~tion of the Drawinas .~ FIGURE 1 is a block schematic diagram of a serial data ~: 20 interface according to the invention;
FIGURE 2 is a general circuit diagram of a particular serial data interface for a dataword length of 24 bits;
FIGURE 3 is a detailed schematic diagram of a portion of the FIGURE 2 circuit representing a setting/resetting circuit with : a clock pulse generator;
: FIGURE 4 is a signal diagram useful in understanding the operation of the circuit represented in FIGURE 3;
FIGURE 5 is a detailed schematic drawing illustrating the data memory of the FIGURE 2 circuit;
; 30 FIGURE 6 is a detailed schematic drawing illustrating the comparator circuit of the FIGURE 2 circuit;
FIGURE 7 iæ a timing diagram useful in understanding the circuit represented in FIGURE 6;
FIGURE 8 is a detailed schematic drawing illustrating a control circuit of the FIGURE 2 circuit;
FIGURE 9 is a timing diagram useful in understanding the ~3' .
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operation of the control clrcult represented ln FIGURE 8; and FIGURE 10 is a flowchart of the circult represented in FIGURE 8.
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132~929 `3 27779-4 General DescrlPtlon In the system of the lnventlon the data bus lncludes three conductors, a data llne, an ena~le llne and a clock llne.
An lnterface clrcult lS coupled between the data bus and a per~
lpheral clrcult to accept lnformatlon from the data llne and `~`transfer lt to the perlpheral clrcult. The partlcular informatlon present on the data llne is evaluated to determlne lf lt pertalns to the particular perlpheral clrcult.
The evaluatlon of the datawords ls performed durlng a ~; 10 read cycle. Thls read cycle ls predetermined by a certain loglcal ., state of the enable llne. The number of clock pulses transmltted durlng the read cycle vla a clock pulse llne corresponds to the ;length of the dataword. Durlng each pulse of the clock slgnal one blt of the data present at the data llne ls wrltten lnto a data memory. By means of a comparator clrcult located at the output of the data memory the length of the dataword ls checked. In cases of devlatlons of the length of the dataword from the length desir-ed for the perlpheral clrcult, a followlng control clrcult sup-:
presses the transfer of the stored data to the perlpheral clrcult.
If the length of the dataword ls correct, elther a transfer ln-structlon ls generated or, lf datawords of the determlned length can be allocated amblguously, an addltional check of the address blts present ln the dataword ls performed. If the address ls correct, a transfer instructlon ls generated whlch lnltlates a transfer of the data lntermedlately stored ln the data memory to the perlpheral clrcult. In the other case the transfer ls sup-~pressed.
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1 32~929 Through slmultaneous evaluation of the state of the enable llne and the clock pulses at the clock pulse line, at the beglnnlng of a data transmlsslon, the data memory, the comparator circult and the control clrcult are set to a glven wait state, starting from whlch a completely new check of the transmltted datawords is always posslble. By swltchlng over the enable llne to a wrlte mode the serlal lnterface can be swltched over to output data to the data bus whereby, here, a presettlng to a certain length of the data to be release~ to the data bus ls posslble at the same time.
Detalled DescriPtlon FIGURE 1 shows a block schematic dlagram of the serial data lnterface 1. Thls lnterface establlshes a connection between a perlpheral clrcuit 2 and a data bus 3. The serlal data inter-face 1 comprlses a data memory 4, a comparator clrcult 5, a con-trol clrcult 6, a settlngtresettlng clrcult 7 and an lnternal clock pulse generator 8. The data bus 3 comprlses three llnes, one data llne 9, one enable llne 10 and one clock pulse llne 11.
In additlon, there ls a resettlng llne 12.
The interface 1 is coupled to the perlpheral clrcult vla a parallel data output 13, a serlal data lnput and output connec-` tlon 14, an address output 15, a counter output 16 and control outputs 17-19.
The complete clrcult of the serlal data lnterface 1 can be seen ln FIGURE 2. Here respectlve parts of the FIGURE 1 cir-cuit are shown ln separate blocks labeled wlth the same reference numbers used ln FIGURE 1. The circult connectlons shown ln FIGURE
1 are also shown and indlcated wlth llke reference numbers.
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1328~29 In the circult shown ln FIGURE 2, data is inpUt to the data memory 4 vla the data line 9. A comparator clrcult 5 ls coupled to a serlal output of the data memory. A control clrcult 6 iS coupled to an outpUt of the comparator 5. An internal set-ting/resettlng circult 7 has lnput connectlons coupled to the enable line 10 and the clock pulse line 11. Output slgnals gener-ated by the lnternal settlng/resettlng clrcult 7 are couple~ to settlng and resetting lnput connectlons of the data memory 4, the comparator clrcult 5 and the control clrcult 6. A clock pulse generator 8 has lnput connections coupled to the enable llne lo and to the clock pulse line 11. Output slgnals from the clock pulse generator 8 are coupled to the clock lnput connections of the data memory 4, the comparator clrcult 5 and the control clr-cult 6. For detailed lllustratlon of the slngular parts and the overall functlon of the serlal data lnterface reference ls made to the followlng flgures.
Refer to FIGURES 3 and 4 whlch respectlvely lllustrate the settlng/resettlng clrcult 7, plus the lnternal clock pulse generator 8, and waveform of slgnals applled to and derlved from these circult elements. The clock pulse generator 8 conslsts of an excluslve NOR clrcult 21 coupled ln cascade wlth an lnverter clrcult, the comblnatlon of whlCh performs an excluslve OR func-tlon. The clock signal on clock llne 11 and the enable slgnal on llne 10 are coupled to respectlve flrst and second lnput termlnals of the excluslve NOR clrcult 21. If the enable slgnal ls low, the output slgnal CNTCLK provlded by the lnverter 19 is ln phase wlth the clock signal. Conversely, lf the enable slgnal ls hlgh, the output slgnal CNTCLK ls antlphase to the clock slgnal.
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The remalnlng elements ln FIGURE 3 comprlse the setting-/resettlng circultry 7. The clock signal an~ an external reset slgnal EXTRES are ANDED in an AND gate 202, the output of whlch is coupled to a reset lnput terminal of a "D-type" flip-flop 200.
The enable slgnal ls lnverted vla an lnverter 201 and applied to a clock lnput termlnal of the flip-flop 200. The Q output signal from the fllp-flop 200 is ANDED wlth the slgnal EXTRES ln an AND
.
circuit conslsting of the cascade connection of a NAND circult 203 and an lnverter 204. The slgnal from the Q output of the fllp-flop 200 corresponds to a slgnal PRESET and slgnal output from thelnverter corresponds to an lnternal RESET slgnal. From the wave-forms of FIGURE 4 lt may be seen that, to lnltlate an interf~ce clrcult, a negatlve pulse ls applled on the slgnal EXTRES whlch places the flip-flop 200 in a defined state. Subsequent set and reset lnstructlons PRESET, RESET generated by combination of the slgnal enable and clock pulse signals CLO~K are provlded to fur-ther parts of the serlal data lnterface clrcult. As can be seen from the waveform dlagram, a change of state of the set and reset slgnals PRESET, RESET ls generated durlng a flrst pulse. For sub-sequent clock pulses the states are no longer sub~ect to change.In the wrlte cycle, too, whlch ls assumed by swltchlng the state of the signal enable, no new change of the set and reset slgnal occurs.
In FIGURE 5 the data memory 4 ls shown. Thls conslsts of a shift reglster wlth memory cells 25, whereby the number n of the memory cells 25 corresponds to the number of blts ln the data-word whlch ls allocated to the perlpheral clrcult 2. The complete . dataword can be made elther excluslvely of these data blts or, lf `: ~
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address blt~ are also requlred, of the data blts and the address bits. The data llne 9, whlch carrles slgnals called DATA, 15 connected to a serlal input 22 of the data memory, and output ; data, DATAOUTI are present at a parallel data output 13. Vla a clock pulse input 23 the clock pulse slgnals CNTCLK are applled to the memory stages. For each pulse of the slgnal CNTCLK a bit present at the data lnput 22 ls shlfted rlghtward through the reglster by one memory cell 25. Vle a reset lnput connectlon 24 the slgnal RESET ls applied by whlch the speciflc memory cells 25 are condltloned to exhlbit a given default state. In partlcular, the state of the flrst memory cell 25 ls swltched to the set or loglcal 1 state and the remalnlng memory cells 25 are swltched to reset or logical 0 state.
As soon as a data flow ls wrltten lnto the data memory 4, the blt generated by settlng the flrst memory cell 25 to a loglc 1 as the leadlng blt, moves through the data memory 4 ln ~, front of the other blts of the dataword. The leading blt, ln case of elther a correct length data word or a dataword havlng a length greater than the correct length, appears as the flrst bit ln the comparator clrcult 5 and can be evaluated as BIT 24 for checklng whether the dataword has the correct length for the allocation to the perlpheral clrcult 2 (e.g., for n = 20). The shift reglster of the data memory 4 ls provlded wlth parallel output connections -at each register stage for convertlng the serlally wrltten data-~, word lnto a parallel bit output dataword. In the wrlte cycle, ,~
l.e., when data is coupled from the perlpheral clrcult 2 to the data bus 3, the data are read out ln a serlal format.
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The comparator circult 5 ls shown ln FIGURE 6. The comparator circult comprlses a shlft reglster made from memory cells 261 to 264 lnto whlCh the data wrltten ln the data memory 4 are transferred as data(N). If the data word does not contaln ~;~ address blts, a slngle memory cell, e.g., 264, ls sufflclent to check the leadlng blt provlded by the serlal output of the data memory 4. If, on the other hand, further a~dress bits are pre-sent, further memory cells (e.g., 261-263) are requlred, the total number of memory cells correspondlng to the number m of the ` 10 address blts. If, as presumed ln the exemplary lmplementatlon, four address blts are precedlng the data blts of the datawords, four memory cells 261 to 264 are requlred ln the shlft reglster of the comparator clrcult 5.
A tlming diagram for the comparator clrcuit 5 ls shown ln FIGURES 7 or 9. Thls dlagram lllustrates that at the beglnnlng of a read cycle, ln whlch data are wrltten from the data bus 3 lnto the data memory 4 and from there are fed to the comparator clrcult as DATA (N), the state of the slgnal enable ls a loglcal 0. It ls assumed that ln a complete dataword length of 24 blts (4 address blts, 20 data blts) for which the clrcult ls designed, a - dataword of equal length ls transmltted through the data bus 3.
Shown in the tlmlng dlagrams are the last of the 24 pulses through whlch thls dataword is wrltten lnto the memory cells 261 to 264 of the comparator clrcult 5. On the twenty-thlrd pulse of the slynal : ,, 1 CNTCLK the leadlng bit is shifted to the last memory cell 264 and " ~ r.
/ appears as BIT 24, and the three memory cells 261-263 contain the `; address blts. The fourth address bit ls present at the data lnput of memory cell 261. Now, by means of a comparator circult the , .
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matching between a dataword address and the address of the per-lpheral clrcuit 2 ls checked. The exemplary comparator loglc lncludes an excluslve NOR clrcuit 2~1 and an AND gate 272. The clrcult 271 lncludes a plurality of parallel exclusive NOR gates each havlng respective flrst lnput termlnals coupled to recelve respectlve address bits and h~vlng respectlve second lnput terml-nals for applylng comparlson address blts. The comparlson address bits may be provlded by approprlately hard wlrlng the lnput terml-nals to loglc 1 and loglc O potentlals, or they may ~e provlded by the respectlve perlpheral clrcult (as lndicated in FIGURE 6 by the connectlon IC=ADRESSE). The output slgnals from the respectlve exclusive NOR gates are coupled to respectlve lnput termlnals of the AND gate 272 whlch provldes a loglc one slgnal when all of the excluslve NOR gates lndlcate address matches. Concurrent wlth the leadlng bit appearlng at the output of the memory cell 264, the comparator loglc provldes a recognitlon slgnal CAV if the address-es match.
The comparator clrcult has an addltlonal functlon whlch ; is to tlme out a wrlte cycle durlng whlch data ls transferred from a perlpheral circuit to the data llne 9. Responslve to slgnals WRITE and LATCH provlded by the control clrcult 6, the memory cells 261-264 are reset to predetermlned states and the clrcultry :~ ls condltloned to operate as a four bit counter whlch counts ., ; pulses of the slgnal CNTCLK. After a certain counter state or value ls reached, a slgnal AVN ls generated, whlch slgnal ls coupled to the control clrcult to lndlcate completlon of a wrlte cycle. In the tlm1ng dlagram of FIGURE 7 the wrlte cycle starts :-'.
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9a 27779-4 wlth the oGcurrence of the posltlve transltlon o~ the slgnal WRITE
and termlnates slxteen clock pulses thereafter.
FIGURE 8 lllustrates the control clrcult 6. The con-trol clrcult lncludes several memory cells (fllp-flops) ~80-2~2, coupled ln the form o~ a shlft reglster by the loglc elements 29-31. In operatlon the memory cell 280 ls preset to a loglcal "1"
state by the slgnal PRESET generated by the settlng~resettlng clrcult 7, and the memory cells 281 and 282 are preset to a logl-cal "0" state by the slgnal R~SET. If the current dataword has the predetermlned length, the loglcal 1 state exhlblted by the memory cell 280 is transferred to the memory cell 281. If the dataword ls not of the predetermlned length such transfer ls not accompllshed. But even lf the dataword ls of proper length, - transferal of the loglc state ln memory cell 280 ls further conditioned on the state of the slgnal CAV lndlcatlng that the address blts match the peripheral address ~lf lncluded). If the slgnal CAV exhlblts a loglcal "1" state, transfer ls accompllshed.
As may be seen from FIGURE 9 on the flrst positlve transitlon of the slgnal CNTCLK after the slgnals CAV, BIT 24 and Ql have all 20 attalned a loglcal "1" state, a loglcal "1" state ls loaded ln memory cell 281 and exhlblted at lts output Q2. Then responslve to the slgnal enable the loglcal "1" state Q2 from memory cell 281 - ls provlded as the slgnal LATCH for one-half period of the slgnal CNTCLK. The slgnal LATCH, besides controlling the comparator circult 6, ls used to latch or transfer the dataword present on the parallel connectlon 13 lnto the perlpheral clrcult 2.
When memory cell 281 exhlblts a loglcal 1 state, the memory cell 282 ls set to the same state. Memory cell 282 ,:
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9b 27779-4 generates a slgnal WRITE whlch ls a loglcal zero durlng readlng or loadlng of a dataword and ls a logical 1 for a predetermined perlod after recognltlon of a dataword. As prevlously lndlcated the wrlte slgnal conditions the circuitry 5 to operate as a coun-ter and count out the wrlte cycle. At the termlnatlon of a wrlte cycle whlch ls lndicated ~y a negatlve golng pulse ln the slgnal AVN, the memory cell 282 ls condltloned to the loglcal "0" state placlng the clrcuit 6 ln the walt state. The write cycle can be lnterrupted lf the state of the slgnal enable ls changed, placlng the circultry ln a read cycle. In thls lnstance the memory cells 280-282 are reset to thelr default states.
. ., The operatlon of the FIGURE 6 clrcultry ls also lndlca-ted ln the flowchart lllustrated ln FIGURE lO.
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Backqround of the Invention Serial data interface clrcuits are used to connect peripheral circuits, which receive or transmit data via a data bus, to said data bus. A data transmisslon by means of a bi-directional data bus i~ described in the D~-OS 34 04 721. The serial data interface circuits must evaluate the data flow running through the data bus using characteristics which allow recognition of the allocation to the specific peripheral circuit connected.
There are at least two general types of bus/interface systems. In the firæt type of system the interface circuit is designed to pass information from a common bus to its corresponding peripheral circuit only after xecognizing a particular address signal applied to the bus. In the second type of system the interface circuit is designed to pass information to its corresponding peripheral circuit according to a predetermined priority of a transmitted sequence of lnformation packets. In the first system the bus structure is burdened with address signals, and the amount of information that may be conveyed on the bus is reduced due to the time required for address identification. In the second type of a system, in general a particular interface cannot be accessed rapidly since the bus~interface system must step through the appropriate priority sequence.
It is an ob~ect of this ~nvention to provide an interface system having rapid data access and capable of greater information transfer.
Summar~ of the Invention The present invention is characterised by: a data store connected to the data line for the surceæsive storage of data words of equal or different word lengths transmitted over the data line; a comparison circuit, which detects addresses for peripheral circuits that are possibly present in the data words and compares ~2C
1~2~929 them with the addres~ of the currently connected peripheral circuit, connected to the data store; a control circuit, which : compares the word length~ of the data words with a predefined word length and then, taking into account the slgnals transmitted on the enable line, only allows a further transfer of the data words to the connected peripheral circuit if the two word length~ are equal, connected to the comparison circuit an internal clock pulse generator, which supplies the data store, the comparison : circuit and the control circuit with clock pulse slgnals, connected to the enable llne and to the clock pulse line; an internal set/reset circuit connected to the enable line and to the clock pulse line, whose outputs are connected to set and/or reset - inputs of the data store, the comparison circuit and the control circuit and emits to these outputs corresponding set and/or re~et : commands which are generated either by an external reset signal or by means of a combination of signals transmitted on the enable line and on the clock pulse line.
v~ Brief Descri~tion of the Drawinas .~ FIGURE 1 is a block schematic diagram of a serial data ~: 20 interface according to the invention;
FIGURE 2 is a general circuit diagram of a particular serial data interface for a dataword length of 24 bits;
FIGURE 3 is a detailed schematic diagram of a portion of the FIGURE 2 circuit representing a setting/resetting circuit with : a clock pulse generator;
: FIGURE 4 is a signal diagram useful in understanding the operation of the circuit represented in FIGURE 3;
FIGURE 5 is a detailed schematic drawing illustrating the data memory of the FIGURE 2 circuit;
; 30 FIGURE 6 is a detailed schematic drawing illustrating the comparator circuit of the FIGURE 2 circuit;
FIGURE 7 iæ a timing diagram useful in understanding the circuit represented in FIGURE 6;
FIGURE 8 is a detailed schematic drawing illustrating a control circuit of the FIGURE 2 circuit;
FIGURE 9 is a timing diagram useful in understanding the ~3' .
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operation of the control clrcult represented ln FIGURE 8; and FIGURE 10 is a flowchart of the circult represented in FIGURE 8.
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132~929 `3 27779-4 General DescrlPtlon In the system of the lnventlon the data bus lncludes three conductors, a data llne, an ena~le llne and a clock llne.
An lnterface clrcult lS coupled between the data bus and a per~
lpheral clrcult to accept lnformatlon from the data llne and `~`transfer lt to the perlpheral clrcult. The partlcular informatlon present on the data llne is evaluated to determlne lf lt pertalns to the particular perlpheral clrcult.
The evaluatlon of the datawords ls performed durlng a ~; 10 read cycle. Thls read cycle ls predetermined by a certain loglcal ., state of the enable llne. The number of clock pulses transmltted durlng the read cycle vla a clock pulse llne corresponds to the ;length of the dataword. Durlng each pulse of the clock slgnal one blt of the data present at the data llne ls wrltten lnto a data memory. By means of a comparator clrcult located at the output of the data memory the length of the dataword ls checked. In cases of devlatlons of the length of the dataword from the length desir-ed for the perlpheral clrcult, a followlng control clrcult sup-:
presses the transfer of the stored data to the perlpheral clrcult.
If the length of the dataword ls correct, elther a transfer ln-structlon ls generated or, lf datawords of the determlned length can be allocated amblguously, an addltional check of the address blts present ln the dataword ls performed. If the address ls correct, a transfer instructlon ls generated whlch lnltlates a transfer of the data lntermedlately stored ln the data memory to the perlpheral clrcult. In the other case the transfer ls sup-~pressed.
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1 32~929 Through slmultaneous evaluation of the state of the enable llne and the clock pulses at the clock pulse line, at the beglnnlng of a data transmlsslon, the data memory, the comparator circult and the control clrcult are set to a glven wait state, starting from whlch a completely new check of the transmltted datawords is always posslble. By swltchlng over the enable llne to a wrlte mode the serlal lnterface can be swltched over to output data to the data bus whereby, here, a presettlng to a certain length of the data to be release~ to the data bus ls posslble at the same time.
Detalled DescriPtlon FIGURE 1 shows a block schematic dlagram of the serial data lnterface 1. Thls lnterface establlshes a connection between a perlpheral clrcuit 2 and a data bus 3. The serlal data inter-face 1 comprlses a data memory 4, a comparator clrcult 5, a con-trol clrcult 6, a settlngtresettlng clrcult 7 and an lnternal clock pulse generator 8. The data bus 3 comprlses three llnes, one data llne 9, one enable llne 10 and one clock pulse llne 11.
In additlon, there ls a resettlng llne 12.
The interface 1 is coupled to the perlpheral clrcult vla a parallel data output 13, a serlal data lnput and output connec-` tlon 14, an address output 15, a counter output 16 and control outputs 17-19.
The complete clrcult of the serlal data lnterface 1 can be seen ln FIGURE 2. Here respectlve parts of the FIGURE 1 cir-cuit are shown ln separate blocks labeled wlth the same reference numbers used ln FIGURE 1. The circult connectlons shown ln FIGURE
1 are also shown and indlcated wlth llke reference numbers.
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1328~29 In the circult shown ln FIGURE 2, data is inpUt to the data memory 4 vla the data line 9. A comparator clrcult 5 ls coupled to a serlal output of the data memory. A control clrcult 6 iS coupled to an outpUt of the comparator 5. An internal set-ting/resettlng circult 7 has lnput connectlons coupled to the enable line 10 and the clock pulse line 11. Output slgnals gener-ated by the lnternal settlng/resettlng clrcult 7 are couple~ to settlng and resetting lnput connectlons of the data memory 4, the comparator clrcult 5 and the control clrcult 6. A clock pulse generator 8 has lnput connections coupled to the enable llne lo and to the clock pulse line 11. Output slgnals from the clock pulse generator 8 are coupled to the clock lnput connections of the data memory 4, the comparator clrcult 5 and the control clr-cult 6. For detailed lllustratlon of the slngular parts and the overall functlon of the serlal data lnterface reference ls made to the followlng flgures.
Refer to FIGURES 3 and 4 whlch respectlvely lllustrate the settlng/resettlng clrcult 7, plus the lnternal clock pulse generator 8, and waveform of slgnals applled to and derlved from these circult elements. The clock pulse generator 8 conslsts of an excluslve NOR clrcult 21 coupled ln cascade wlth an lnverter clrcult, the comblnatlon of whlCh performs an excluslve OR func-tlon. The clock signal on clock llne 11 and the enable slgnal on llne 10 are coupled to respectlve flrst and second lnput termlnals of the excluslve NOR clrcult 21. If the enable slgnal ls low, the output slgnal CNTCLK provlded by the lnverter 19 is ln phase wlth the clock signal. Conversely, lf the enable slgnal ls hlgh, the output slgnal CNTCLK ls antlphase to the clock slgnal.
~, r~
....
:
' .
The remalnlng elements ln FIGURE 3 comprlse the setting-/resettlng circultry 7. The clock signal an~ an external reset slgnal EXTRES are ANDED in an AND gate 202, the output of whlch is coupled to a reset lnput terminal of a "D-type" flip-flop 200.
The enable slgnal ls lnverted vla an lnverter 201 and applied to a clock lnput termlnal of the flip-flop 200. The Q output signal from the fllp-flop 200 is ANDED wlth the slgnal EXTRES ln an AND
.
circuit conslsting of the cascade connection of a NAND circult 203 and an lnverter 204. The slgnal from the Q output of the fllp-flop 200 corresponds to a slgnal PRESET and slgnal output from thelnverter corresponds to an lnternal RESET slgnal. From the wave-forms of FIGURE 4 lt may be seen that, to lnltlate an interf~ce clrcult, a negatlve pulse ls applled on the slgnal EXTRES whlch places the flip-flop 200 in a defined state. Subsequent set and reset lnstructlons PRESET, RESET generated by combination of the slgnal enable and clock pulse signals CLO~K are provlded to fur-ther parts of the serlal data lnterface clrcult. As can be seen from the waveform dlagram, a change of state of the set and reset slgnals PRESET, RESET ls generated durlng a flrst pulse. For sub-sequent clock pulses the states are no longer sub~ect to change.In the wrlte cycle, too, whlch ls assumed by swltchlng the state of the signal enable, no new change of the set and reset slgnal occurs.
In FIGURE 5 the data memory 4 ls shown. Thls conslsts of a shift reglster wlth memory cells 25, whereby the number n of the memory cells 25 corresponds to the number of blts ln the data-word whlch ls allocated to the perlpheral clrcult 2. The complete . dataword can be made elther excluslvely of these data blts or, lf `: ~
~' :
: : ~
address blt~ are also requlred, of the data blts and the address bits. The data llne 9, whlch carrles slgnals called DATA, 15 connected to a serlal input 22 of the data memory, and output ; data, DATAOUTI are present at a parallel data output 13. Vla a clock pulse input 23 the clock pulse slgnals CNTCLK are applled to the memory stages. For each pulse of the slgnal CNTCLK a bit present at the data lnput 22 ls shlfted rlghtward through the reglster by one memory cell 25. Vle a reset lnput connectlon 24 the slgnal RESET ls applied by whlch the speciflc memory cells 25 are condltloned to exhlbit a given default state. In partlcular, the state of the flrst memory cell 25 ls swltched to the set or loglcal 1 state and the remalnlng memory cells 25 are swltched to reset or logical 0 state.
As soon as a data flow ls wrltten lnto the data memory 4, the blt generated by settlng the flrst memory cell 25 to a loglc 1 as the leadlng blt, moves through the data memory 4 ln ~, front of the other blts of the dataword. The leading blt, ln case of elther a correct length data word or a dataword havlng a length greater than the correct length, appears as the flrst bit ln the comparator clrcult 5 and can be evaluated as BIT 24 for checklng whether the dataword has the correct length for the allocation to the perlpheral clrcult 2 (e.g., for n = 20). The shift reglster of the data memory 4 ls provlded wlth parallel output connections -at each register stage for convertlng the serlally wrltten data-~, word lnto a parallel bit output dataword. In the wrlte cycle, ,~
l.e., when data is coupled from the perlpheral clrcult 2 to the data bus 3, the data are read out ln a serlal format.
~ .~
,,~
~"
. . .
. .~ .
",,: , :
' ~
:; -.
132892~
The comparator circult 5 ls shown ln FIGURE 6. The comparator circult comprlses a shlft reglster made from memory cells 261 to 264 lnto whlCh the data wrltten ln the data memory 4 are transferred as data(N). If the data word does not contaln ~;~ address blts, a slngle memory cell, e.g., 264, ls sufflclent to check the leadlng blt provlded by the serlal output of the data memory 4. If, on the other hand, further a~dress bits are pre-sent, further memory cells (e.g., 261-263) are requlred, the total number of memory cells correspondlng to the number m of the ` 10 address blts. If, as presumed ln the exemplary lmplementatlon, four address blts are precedlng the data blts of the datawords, four memory cells 261 to 264 are requlred ln the shlft reglster of the comparator clrcult 5.
A tlming diagram for the comparator clrcuit 5 ls shown ln FIGURES 7 or 9. Thls dlagram lllustrates that at the beglnnlng of a read cycle, ln whlch data are wrltten from the data bus 3 lnto the data memory 4 and from there are fed to the comparator clrcult as DATA (N), the state of the slgnal enable ls a loglcal 0. It ls assumed that ln a complete dataword length of 24 blts (4 address blts, 20 data blts) for which the clrcult ls designed, a - dataword of equal length ls transmltted through the data bus 3.
Shown in the tlmlng dlagrams are the last of the 24 pulses through whlch thls dataword is wrltten lnto the memory cells 261 to 264 of the comparator clrcult 5. On the twenty-thlrd pulse of the slynal : ,, 1 CNTCLK the leadlng bit is shifted to the last memory cell 264 and " ~ r.
/ appears as BIT 24, and the three memory cells 261-263 contain the `; address blts. The fourth address bit ls present at the data lnput of memory cell 261. Now, by means of a comparator circult the , .
; .~
,'' :,...... ... ~ ' -,~
::. .
matching between a dataword address and the address of the per-lpheral clrcuit 2 ls checked. The exemplary comparator loglc lncludes an excluslve NOR clrcuit 2~1 and an AND gate 272. The clrcult 271 lncludes a plurality of parallel exclusive NOR gates each havlng respective flrst lnput termlnals coupled to recelve respectlve address bits and h~vlng respectlve second lnput terml-nals for applylng comparlson address blts. The comparlson address bits may be provlded by approprlately hard wlrlng the lnput terml-nals to loglc 1 and loglc O potentlals, or they may ~e provlded by the respectlve perlpheral clrcult (as lndicated in FIGURE 6 by the connectlon IC=ADRESSE). The output slgnals from the respectlve exclusive NOR gates are coupled to respectlve lnput termlnals of the AND gate 272 whlch provldes a loglc one slgnal when all of the excluslve NOR gates lndlcate address matches. Concurrent wlth the leadlng bit appearlng at the output of the memory cell 264, the comparator loglc provldes a recognitlon slgnal CAV if the address-es match.
The comparator clrcult has an addltlonal functlon whlch ; is to tlme out a wrlte cycle durlng whlch data ls transferred from a perlpheral circuit to the data llne 9. Responslve to slgnals WRITE and LATCH provlded by the control clrcult 6, the memory cells 261-264 are reset to predetermlned states and the clrcultry :~ ls condltloned to operate as a four bit counter whlch counts ., ; pulses of the slgnal CNTCLK. After a certain counter state or value ls reached, a slgnal AVN ls generated, whlch slgnal ls coupled to the control clrcult to lndlcate completlon of a wrlte cycle. In the tlm1ng dlagram of FIGURE 7 the wrlte cycle starts :-'.
. .
...
~."
'' .
~ .
9a 27779-4 wlth the oGcurrence of the posltlve transltlon o~ the slgnal WRITE
and termlnates slxteen clock pulses thereafter.
FIGURE 8 lllustrates the control clrcult 6. The con-trol clrcult lncludes several memory cells (fllp-flops) ~80-2~2, coupled ln the form o~ a shlft reglster by the loglc elements 29-31. In operatlon the memory cell 280 ls preset to a loglcal "1"
state by the slgnal PRESET generated by the settlng~resettlng clrcult 7, and the memory cells 281 and 282 are preset to a logl-cal "0" state by the slgnal R~SET. If the current dataword has the predetermlned length, the loglcal 1 state exhlblted by the memory cell 280 is transferred to the memory cell 281. If the dataword ls not of the predetermlned length such transfer ls not accompllshed. But even lf the dataword ls of proper length, - transferal of the loglc state ln memory cell 280 ls further conditioned on the state of the slgnal CAV lndlcatlng that the address blts match the peripheral address ~lf lncluded). If the slgnal CAV exhlblts a loglcal "1" state, transfer ls accompllshed.
As may be seen from FIGURE 9 on the flrst positlve transitlon of the slgnal CNTCLK after the slgnals CAV, BIT 24 and Ql have all 20 attalned a loglcal "1" state, a loglcal "1" state ls loaded ln memory cell 281 and exhlblted at lts output Q2. Then responslve to the slgnal enable the loglcal "1" state Q2 from memory cell 281 - ls provlded as the slgnal LATCH for one-half period of the slgnal CNTCLK. The slgnal LATCH, besides controlling the comparator circult 6, ls used to latch or transfer the dataword present on the parallel connectlon 13 lnto the perlpheral clrcult 2.
When memory cell 281 exhlblts a loglcal 1 state, the memory cell 282 ls set to the same state. Memory cell 282 ,:
. . ~.,, ,:, .,~, ;' :
,. : .
.. :
~ ~ .
132~2~
9b 27779-4 generates a slgnal WRITE whlch ls a loglcal zero durlng readlng or loadlng of a dataword and ls a logical 1 for a predetermined perlod after recognltlon of a dataword. As prevlously lndlcated the wrlte slgnal conditions the circuitry 5 to operate as a coun-ter and count out the wrlte cycle. At the termlnatlon of a wrlte cycle whlch ls lndicated ~y a negatlve golng pulse ln the slgnal AVN, the memory cell 282 ls condltloned to the loglcal "0" state placlng the clrcuit 6 ln the walt state. The write cycle can be lnterrupted lf the state of the slgnal enable ls changed, placlng the circultry ln a read cycle. In thls lnstance the memory cells 280-282 are reset to thelr default states.
. ., The operatlon of the FIGURE 6 clrcultry ls also lndlca-ted ln the flowchart lllustrated ln FIGURE lO.
: `
'~,', :
.~.
,;
, .
~ ~ .
~,. ..
,
Claims (7)
1. A serial data interface for the connection of a known data bus to a peripheral circuit, wherein a plurality of peripheral circuits are connected to a corresponding plurality of data interfaces and the data bus includes a data line, an enable line and a clock pulse line, characterised by:
- a data store connected to the data line for the successive storage of data words of equal or different word lengths transmitted over the data line;
- a comparison circuit, which detects addresses for peripheral circuits that are possibly present in the data words and compares them with the address of the currently connected peripheral circuit, connected to the data store;
- a control circuit, which compares the word lengths of the data words with a predefined word length and then, taking into account the signals transmitted on the enable line, only allows a further transfer of the data words to the connected peripheral circuit if the two word lengths are equal, connected to the comparison circuit;
- an internal clock pulse generator, which supplies the data store, the comparison circuit and the control circuit with clock pulse signals, connected to the enable line and to the clock pulse line;
- an internal set/reset circuit connected to the enable line and to the clock pulse line, whose outputs are connected to set and/or reset inputs of the data store, the comparison circuit and the control circuit and emits to these outputs corresponding set and/or reset commands which are generated either by an external reset signal or by means of a combination of signals transmitted on the enable line and on the clock pulse line.
- a data store connected to the data line for the successive storage of data words of equal or different word lengths transmitted over the data line;
- a comparison circuit, which detects addresses for peripheral circuits that are possibly present in the data words and compares them with the address of the currently connected peripheral circuit, connected to the data store;
- a control circuit, which compares the word lengths of the data words with a predefined word length and then, taking into account the signals transmitted on the enable line, only allows a further transfer of the data words to the connected peripheral circuit if the two word lengths are equal, connected to the comparison circuit;
- an internal clock pulse generator, which supplies the data store, the comparison circuit and the control circuit with clock pulse signals, connected to the enable line and to the clock pulse line;
- an internal set/reset circuit connected to the enable line and to the clock pulse line, whose outputs are connected to set and/or reset inputs of the data store, the comparison circuit and the control circuit and emits to these outputs corresponding set and/or reset commands which are generated either by an external reset signal or by means of a combination of signals transmitted on the enable line and on the clock pulse line.
2. A data interface in accordance with claim 1, characterised in that, the data store comprises a shift register having n storage cells wherein the number n corresponds to the number of the bits of the data word associated with the peripheral circuit.
3. A data interface in accordance with claim 2, characterised in that the data store can be placed by the set/reset circuit into a state in which the first storage cell as seen from the input is a logical 1 and the remaining storage cells are logical 0 or vice versa.
4. A data interface in accordance with claim 2 or 3, characterised in that the last storage cells of the data store as seen from the input are components of the comparison circuit, wherein the comparison circuit also comprises a comparison logic to which the outputs of the last storage cells on the one hand and outputs of a module containing the address of the peripheral circuit on the other hand are connected.
5. A data interface in accordance with claim 2 or 3, characterised in that the control circuit is formed as a shift register having a plurality of storage cells, wherein the storage cells are connected to each other via logical combinatorial elements, that outputs of the comparison circuit and of the set/reset circuit are connected to the inputs of the combinatorial logic elements and that a store transfer signal LATCH and a write/read signal WRITE are derivable at outputs of the control circuit.
6. A data interface in accordance with claim 5, characterised in that the control circuit is settable by the set/reset circuit into a state in which the first storage cell as seen from the input is a logical 1 and the remaining storage cells are logical 0 or vice versa.
7. A data interface in accordance with claim 5 or 6, characterised in that the output carrying the write/read signal WRITE of the control circuit is connected to a control logic of the comparison circuit by means of which the storage cells of the comparison circuit in the writing mode can be connected up as a counter and that a counter output is connected to one of the combinatorial logic elements between the storage cells of the control circuit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE3829454A DE3829454A1 (en) | 1988-08-31 | 1988-08-31 | SERIAL DATA INTERFACE |
| DEP3829454.0 | 1988-08-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1328929C true CA1328929C (en) | 1994-04-26 |
Family
ID=6361925
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000609662A Expired - Fee Related CA1328929C (en) | 1988-08-31 | 1989-08-29 | Serial data interface |
Country Status (12)
| Country | Link |
|---|---|
| EP (2) | EP0356873B1 (en) |
| JP (1) | JPH03501072A (en) |
| KR (1) | KR900702459A (en) |
| AT (1) | ATE96557T1 (en) |
| CA (1) | CA1328929C (en) |
| DE (2) | DE3829454A1 (en) |
| ES (1) | ES2047072T3 (en) |
| FI (1) | FI902153A0 (en) |
| HK (1) | HK9596A (en) |
| MY (1) | MY105090A (en) |
| TR (1) | TR24012A (en) |
| WO (1) | WO1990002377A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5278243A (en) * | 1992-01-14 | 1994-01-11 | Soane Technologies, Inc. | High impact resistant macromolecular networks |
| DE4107052B4 (en) * | 1991-03-06 | 2005-09-29 | Robert Bosch Gmbh | Device for the application of control devices, in particular ignition and / or injection control devices for motor vehicles |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3139421A1 (en) * | 1981-10-03 | 1983-04-21 | Nsm-Apparatebau Gmbh & Co Kg, 6530 Bingen | Serial output circuit |
| DE3404721C2 (en) * | 1984-02-10 | 1991-07-25 | Deutsche Thomson-Brandt Gmbh, 7730 Villingen-Schwenningen | Circuit arrangement for the transmission of data |
| DE3534216A1 (en) * | 1985-09-25 | 1987-04-02 | Bayerische Motoren Werke Ag | DATA BUS SYSTEM FOR VEHICLES |
| FR2591772B1 (en) * | 1985-12-18 | 1989-09-29 | Cugnez Jean Louis | SYSTEM FOR CONNECTING A PERIPHERAL TO MULTIPLE COMPUTERS |
| DE3603751A1 (en) * | 1986-02-06 | 1987-08-13 | Siemens Ag | INFORMATION TRANSFER SYSTEM FOR THE TRANSFER OF BINARY INFORMATION |
-
1988
- 1988-08-31 DE DE3829454A patent/DE3829454A1/en not_active Withdrawn
-
1989
- 1989-08-15 MY MYPI89001114A patent/MY105090A/en unknown
- 1989-08-22 WO PCT/EP1989/000984 patent/WO1990002377A1/en not_active Application Discontinuation
- 1989-08-22 EP EP89115427A patent/EP0356873B1/en not_active Expired - Lifetime
- 1989-08-22 AT AT89115427T patent/ATE96557T1/en not_active IP Right Cessation
- 1989-08-22 DE DE89115427T patent/DE58906010D1/en not_active Expired - Fee Related
- 1989-08-22 JP JP1509425A patent/JPH03501072A/en active Pending
- 1989-08-22 ES ES89115427T patent/ES2047072T3/en not_active Expired - Lifetime
- 1989-08-22 EP EP89909759A patent/EP0404870A1/en active Pending
- 1989-08-25 TR TR89/0799A patent/TR24012A/en unknown
- 1989-08-29 CA CA000609662A patent/CA1328929C/en not_active Expired - Fee Related
-
1990
- 1990-04-27 FI FI902153A patent/FI902153A0/en not_active IP Right Cessation
- 1990-04-30 KR KR1019900700888A patent/KR900702459A/en not_active Application Discontinuation
-
1996
- 1996-01-18 HK HK9596A patent/HK9596A/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| ATE96557T1 (en) | 1993-11-15 |
| KR900702459A (en) | 1990-12-07 |
| TR24012A (en) | 1991-01-28 |
| ES2047072T3 (en) | 1994-02-16 |
| WO1990002377A1 (en) | 1990-03-08 |
| HK9596A (en) | 1996-01-26 |
| EP0404870A1 (en) | 1991-01-02 |
| DE3829454A1 (en) | 1990-03-01 |
| JPH03501072A (en) | 1991-03-07 |
| EP0356873A1 (en) | 1990-03-07 |
| MY105090A (en) | 1994-08-30 |
| FI902153A0 (en) | 1990-04-27 |
| EP0356873B1 (en) | 1993-10-27 |
| DE58906010D1 (en) | 1993-12-02 |
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