CA1265222A - Circuit and method for monitoring the quality of data in a data stream - Google Patents
Circuit and method for monitoring the quality of data in a data streamInfo
- Publication number
- CA1265222A CA1265222A CA000535582A CA535582A CA1265222A CA 1265222 A CA1265222 A CA 1265222A CA 000535582 A CA000535582 A CA 000535582A CA 535582 A CA535582 A CA 535582A CA 1265222 A CA1265222 A CA 1265222A
- Authority
- CA
- Canada
- Prior art keywords
- counter means
- counter
- count
- circuit
- predetermined
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/24—Testing correct operation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
CIRCUIT AND METHOD FOR MONITORING THE QUALITY
OF DATA IN A DATA STREAM
Abstract of the Disclosure The invention provides a circuit for monitoring predetermined performance criteria of a transmission link by measuring a predetermined ratio of events in a data stream.
A first counter having a predetermined maximum count is responsive to each of periodic predetermined occurrences in the data stream and a clock pulse for also increasing its count by one. A second counter having a predetermined maximum count is responsive to each error of predetermined type in the data stream and a clock pulse for increasing its count by one. The overflow output of the first counter is connected to the clear input of the second counter and the overflow output of the second counter is connected to the clear input of the first counter. A signal appearing at the overflow output of the second counter indicates that the predetermined ratio of events in the data stream has not been met. The circuit also provides turn-on, turn-off hysteresis.
- i -
OF DATA IN A DATA STREAM
Abstract of the Disclosure The invention provides a circuit for monitoring predetermined performance criteria of a transmission link by measuring a predetermined ratio of events in a data stream.
A first counter having a predetermined maximum count is responsive to each of periodic predetermined occurrences in the data stream and a clock pulse for also increasing its count by one. A second counter having a predetermined maximum count is responsive to each error of predetermined type in the data stream and a clock pulse for increasing its count by one. The overflow output of the first counter is connected to the clear input of the second counter and the overflow output of the second counter is connected to the clear input of the first counter. A signal appearing at the overflow output of the second counter indicates that the predetermined ratio of events in the data stream has not been met. The circuit also provides turn-on, turn-off hysteresis.
- i -
Description
~5~2~
CIRCUIT AND MET~OD FOR MONITORING THE QUALITY
OF DATA IN A DATA ST~EAM
Back~r u_d of the Invention The invention relates generally to a circuit for monitoring the relationship between a pair of signals and more particularly to a fully digital circuit for monitoring performance criteria of a digital data transmission link.
Brief Description of ,the Prior Art One prior art method of improving the quality of a data transmission link has been through the use of automatic gain control in the receiversO Corrective measures are taken when the gain control feedback signal exceeds certain limits.
While this method can detect a weak or faded signal, signal distortion due to noise is not identified and may go undetected.
Another method employs the transmission of a known pattern of data as a means for chec~cing the received data for accuracy. Of course, the drawback to this technique is that normal transmissions on the link being checked must be interrupted for transmission of the known pattern.
It ~s there~ore desirable to provide a circuit ~or the measurement of receive data ~uality that may be connected on-line with the data link. X'he output oE such a circuit may then be used to raise an alarm flag and corrective action such as commutatlon of the link, retransmission request of the data or simply non-reception of garbled data may be taken.
~ typical circuit and method of monitoring a digital transmission link is described in United States patent number 4,363,123. In that circuit, an error counter is incremented once per a predetermined period if at least one error is detected during the period and is decremented for each error-free period. While this circuit is effective in the control of re-synchronization requests, it does not count the number of errors, nor does it provide an indicatlon of data quality.
Another type of circuit adapted to the monitoring of a digital transmission link is examplified by United ~6~i22~:
States patent number 4,291,~03. This type of circuit comprises a single shot monostable circuit and/or timing generators, a counter circuit and various logic gates including comparators and even a relay.
As effective as these circuits may be for their intended use, they suffer from a number of deficiencies.
Since the circuits are driven by a source of error pulses only they are incapable of providing a continuous data quality indicator. They also tend to be relatively expensiva and require analog type components (e.g. capacitors) which make the total integration of the circuit difficult.
Summary of the Invention With the proliferation of digital systems such as ISDN (Integrated Services Digital Network) it is becoming imperative that any circuit used in those systems be economical and fully digital.
It is therefore an object of the invention to provide a cirauit for monitoring the performance of digital data transmission which is simple, economical and fully digital so that ~t ma~ be conveniently integrated.
~ n a~cordanc~ wlth the invention, there is provided an event ratio detector clrcuit comprising a first counter havin~ a predetermined maximum count anA being responsiv~ to each event of a first se~uence of events for increasing its count by one, and a second counter having a predetermlned maximum count and being responsive to each event of a second sequence of events for increasing its count by one. The overflow output o~ the first counter is connected to the clear input of the second counter and the overflow output of the se~cond counter is connected to the clear input of the first counter. A signal appearing at the overflow output of the second counter means indicates that the ratio of second events to first events as predetermined by the respective maximum counts of the second and first counters has been exceeded.
The circuit of the invention may be used as a performance monitor in a data receiver circuit adapted to receive a digital data stream on a transmission link wherein the receiver circuit comprises a signal generator adapted to provide a periodic bit corresponding to each one of predetermined occurrences in the data stream, an error detector circuit adapted to provide an error bit corresponding to each error of a predetermined type detected in the received data and a source of clock pulses synchronized to the bits of the data stream. The monitoring circuit comprises a first counter means having a predetermined maximum count and which is responsive to each of the periodic bits and a clock pulse for increasing its count by one. It further comprises a second counter means having a predetermined maximum count and which is responsive to each error bit and a clock pulse for increasing its count by one. The overflow output o the first counter means is connected to the clear input of the second counter means and the overflow output oE the second counter means is connected to the clear input of the first counter means. A signal appearing at the over~low output of the second counter means represents a data ~uality indication to the data receiver circuit.
F~om another aspact, the invention provides a method for measuring a p~edetermined ratio of events in a data stream and thus determine :if the predetermined performance crlteria O:e a transmission link are met.
~5 The circuit of the invention runs continuously to provide a data ~uality indication and provides turn-on, turn-off hysteresis. That is, an alarm flag is raised as soon as an error threshold is reached and is not removed until a predetermined amount of error-free data has been received.
The alarm flag may be used to suspend reception of further data until the monitoring circuit indicates that the received data meets the predetermined criteria of quality or to commutate the data link to an alternate path.
Detailed Description An example embodiment of the invention will now be described in conjunction with the drawings in which:
Figure 1 is a schematic diagram of a circllit in accordance with the invention; and i~65~
Figure 2 i5 a flowchart illustrating the operation of the circuit oE figure 1.
Figure 1 shows an input terminal lo to which may be connected a digital data stream from a transmission link. The data on the link may be parti~ioned using any me~hod compatible with the receiver. Any such data stream may conventionally be partitioned into frames and sub-frames and may contain parity bits as well as error checking codes such as, for example, cyclic redundancy codes (CRCj.
lo A data receiver usually comprises error detector circuitry 11 for providing an error bit corresponding to the detection of a departure from the expected data such as loss of framing, parity or failure of the CRC check. It also usually comprises a clock recovery circuit 12 adapted to provide a clock pulse in synchronism with the receive data, as well as a periodic bit generator 13 adapted to provide a signal corresponding to a predetermined expected ocaurrence in the incoming data ~tream, for example, a framing pulse.
~he monitoring cirauit of the invention makes use of these conventionally available signals to provide a continuous ~uality of data indi~ation. It comprises a periodic bit counter 1~, an error blt counter 15, and AND gates 17 and 18 interconnecte~ as ~hown in ~igure ~. The counter 14 is advanced by onq count at every coincidental occurrence of a periodic bit P~om generator 13 and a clock pulse, and counter 15 is advanced by one count at every coincidental occurrence of a clock pulse and an error signal from the detector 11. The overflow output from counter 14 i5 connected to the clear input of counter 15 and to the reset input of a flip-flop 16 whereas the overflow output of counter 15 is connected to the clear input of counter 14 and to the set input of flip-flop 16. Of course, the maximum count of each of counters 14 and 15 is predetermined depending on the particular application of the monitor circuit. Each of counters 14 and 15 may conveniently be of the conventional type that resets itself on reaching its maximum count.
In operation, the monitor circuit is effective to provide a flag signal on the Q output of the flip-flop 16 `~ whenever the number of errors exceeds a predetermined ratio ~2~s~2 of errors to a predetermined amount of data received. This ratio is predetermined by the respective maximum counts of counters 15 and 14. Of course, the absence of a flag signal indicates that the data received meets the predetermined criteria of operation.
The operation of the monitor circuit is depicted in figure 2. At every occurrence of a signal bit from the generator 13, the counter 14 is incremented and similarly, at every occurrence of a signal bit from the detector 11, the lo counter 15 is incremented. When the counter 14 overflows, it clears counter 15 therehy causing both counters to be set to their minimum count. On the other hand, if counter 15 reaches its maximum count before counter 14, its overflow signal will clear counter l~ and set flip-flop 16 to thereby cause a flag signal to be generated. As long as the error rate. exceeds the predetermined performance criteria of the transmission link, the counter 15 will continue to reach its maximum count befora that o~ counter 14 and the flip-flop 16 will continue to indicate an alarm signal~ rrhQ flip-flop 16 will not be r~set until the per~ormance crikeria has again be~n met as indicated by the counter 1~ reaching its maximum count before c~unter 15 rQaches its maximum count.
Sinae the ~ualit~ o~ transmission on a data link is conventionall~ Qxpressed in errors per n bits (e.g. x errors/10n bits) being kransmitted on the data link the judicious choice of counters will cause the monitor circuit to provide a ~lag signal when the predetermined performance criteria are not met.
As is evident from the above description, the invention provides a simple and economical monitor circuit which runs continuously to provide a data ~uality indication with hysteresis. In fact, the circuit is effective for the detection of any predekermined ratio of events.
CIRCUIT AND MET~OD FOR MONITORING THE QUALITY
OF DATA IN A DATA ST~EAM
Back~r u_d of the Invention The invention relates generally to a circuit for monitoring the relationship between a pair of signals and more particularly to a fully digital circuit for monitoring performance criteria of a digital data transmission link.
Brief Description of ,the Prior Art One prior art method of improving the quality of a data transmission link has been through the use of automatic gain control in the receiversO Corrective measures are taken when the gain control feedback signal exceeds certain limits.
While this method can detect a weak or faded signal, signal distortion due to noise is not identified and may go undetected.
Another method employs the transmission of a known pattern of data as a means for chec~cing the received data for accuracy. Of course, the drawback to this technique is that normal transmissions on the link being checked must be interrupted for transmission of the known pattern.
It ~s there~ore desirable to provide a circuit ~or the measurement of receive data ~uality that may be connected on-line with the data link. X'he output oE such a circuit may then be used to raise an alarm flag and corrective action such as commutatlon of the link, retransmission request of the data or simply non-reception of garbled data may be taken.
~ typical circuit and method of monitoring a digital transmission link is described in United States patent number 4,363,123. In that circuit, an error counter is incremented once per a predetermined period if at least one error is detected during the period and is decremented for each error-free period. While this circuit is effective in the control of re-synchronization requests, it does not count the number of errors, nor does it provide an indicatlon of data quality.
Another type of circuit adapted to the monitoring of a digital transmission link is examplified by United ~6~i22~:
States patent number 4,291,~03. This type of circuit comprises a single shot monostable circuit and/or timing generators, a counter circuit and various logic gates including comparators and even a relay.
As effective as these circuits may be for their intended use, they suffer from a number of deficiencies.
Since the circuits are driven by a source of error pulses only they are incapable of providing a continuous data quality indicator. They also tend to be relatively expensiva and require analog type components (e.g. capacitors) which make the total integration of the circuit difficult.
Summary of the Invention With the proliferation of digital systems such as ISDN (Integrated Services Digital Network) it is becoming imperative that any circuit used in those systems be economical and fully digital.
It is therefore an object of the invention to provide a cirauit for monitoring the performance of digital data transmission which is simple, economical and fully digital so that ~t ma~ be conveniently integrated.
~ n a~cordanc~ wlth the invention, there is provided an event ratio detector clrcuit comprising a first counter havin~ a predetermined maximum count anA being responsiv~ to each event of a first se~uence of events for increasing its count by one, and a second counter having a predetermlned maximum count and being responsive to each event of a second sequence of events for increasing its count by one. The overflow output o~ the first counter is connected to the clear input of the second counter and the overflow output of the se~cond counter is connected to the clear input of the first counter. A signal appearing at the overflow output of the second counter means indicates that the ratio of second events to first events as predetermined by the respective maximum counts of the second and first counters has been exceeded.
The circuit of the invention may be used as a performance monitor in a data receiver circuit adapted to receive a digital data stream on a transmission link wherein the receiver circuit comprises a signal generator adapted to provide a periodic bit corresponding to each one of predetermined occurrences in the data stream, an error detector circuit adapted to provide an error bit corresponding to each error of a predetermined type detected in the received data and a source of clock pulses synchronized to the bits of the data stream. The monitoring circuit comprises a first counter means having a predetermined maximum count and which is responsive to each of the periodic bits and a clock pulse for increasing its count by one. It further comprises a second counter means having a predetermined maximum count and which is responsive to each error bit and a clock pulse for increasing its count by one. The overflow output o the first counter means is connected to the clear input of the second counter means and the overflow output oE the second counter means is connected to the clear input of the first counter means. A signal appearing at the over~low output of the second counter means represents a data ~uality indication to the data receiver circuit.
F~om another aspact, the invention provides a method for measuring a p~edetermined ratio of events in a data stream and thus determine :if the predetermined performance crlteria O:e a transmission link are met.
~5 The circuit of the invention runs continuously to provide a data ~uality indication and provides turn-on, turn-off hysteresis. That is, an alarm flag is raised as soon as an error threshold is reached and is not removed until a predetermined amount of error-free data has been received.
The alarm flag may be used to suspend reception of further data until the monitoring circuit indicates that the received data meets the predetermined criteria of quality or to commutate the data link to an alternate path.
Detailed Description An example embodiment of the invention will now be described in conjunction with the drawings in which:
Figure 1 is a schematic diagram of a circllit in accordance with the invention; and i~65~
Figure 2 i5 a flowchart illustrating the operation of the circuit oE figure 1.
Figure 1 shows an input terminal lo to which may be connected a digital data stream from a transmission link. The data on the link may be parti~ioned using any me~hod compatible with the receiver. Any such data stream may conventionally be partitioned into frames and sub-frames and may contain parity bits as well as error checking codes such as, for example, cyclic redundancy codes (CRCj.
lo A data receiver usually comprises error detector circuitry 11 for providing an error bit corresponding to the detection of a departure from the expected data such as loss of framing, parity or failure of the CRC check. It also usually comprises a clock recovery circuit 12 adapted to provide a clock pulse in synchronism with the receive data, as well as a periodic bit generator 13 adapted to provide a signal corresponding to a predetermined expected ocaurrence in the incoming data ~tream, for example, a framing pulse.
~he monitoring cirauit of the invention makes use of these conventionally available signals to provide a continuous ~uality of data indi~ation. It comprises a periodic bit counter 1~, an error blt counter 15, and AND gates 17 and 18 interconnecte~ as ~hown in ~igure ~. The counter 14 is advanced by onq count at every coincidental occurrence of a periodic bit P~om generator 13 and a clock pulse, and counter 15 is advanced by one count at every coincidental occurrence of a clock pulse and an error signal from the detector 11. The overflow output from counter 14 i5 connected to the clear input of counter 15 and to the reset input of a flip-flop 16 whereas the overflow output of counter 15 is connected to the clear input of counter 14 and to the set input of flip-flop 16. Of course, the maximum count of each of counters 14 and 15 is predetermined depending on the particular application of the monitor circuit. Each of counters 14 and 15 may conveniently be of the conventional type that resets itself on reaching its maximum count.
In operation, the monitor circuit is effective to provide a flag signal on the Q output of the flip-flop 16 `~ whenever the number of errors exceeds a predetermined ratio ~2~s~2 of errors to a predetermined amount of data received. This ratio is predetermined by the respective maximum counts of counters 15 and 14. Of course, the absence of a flag signal indicates that the data received meets the predetermined criteria of operation.
The operation of the monitor circuit is depicted in figure 2. At every occurrence of a signal bit from the generator 13, the counter 14 is incremented and similarly, at every occurrence of a signal bit from the detector 11, the lo counter 15 is incremented. When the counter 14 overflows, it clears counter 15 therehy causing both counters to be set to their minimum count. On the other hand, if counter 15 reaches its maximum count before counter 14, its overflow signal will clear counter l~ and set flip-flop 16 to thereby cause a flag signal to be generated. As long as the error rate. exceeds the predetermined performance criteria of the transmission link, the counter 15 will continue to reach its maximum count befora that o~ counter 14 and the flip-flop 16 will continue to indicate an alarm signal~ rrhQ flip-flop 16 will not be r~set until the per~ormance crikeria has again be~n met as indicated by the counter 1~ reaching its maximum count before c~unter 15 rQaches its maximum count.
Sinae the ~ualit~ o~ transmission on a data link is conventionall~ Qxpressed in errors per n bits (e.g. x errors/10n bits) being kransmitted on the data link the judicious choice of counters will cause the monitor circuit to provide a ~lag signal when the predetermined performance criteria are not met.
As is evident from the above description, the invention provides a simple and economical monitor circuit which runs continuously to provide a data ~uality indication with hysteresis. In fact, the circuit is effective for the detection of any predekermined ratio of events.
Claims (9)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. An event ratio detector circuit comprising a first counter means having a predetermined maximum count and being responsive to each event of a first sequence of events for increasing its count by one, and a second counter means having a predetermined maximum count and being responsive to each event of a second sequence of events for increasing its count by one, the overflow output of the first counter means being connected to the clear input of the second counter means, and the overflow output of the second counter means being connected to the clear input of the first counter means, a signal appearing at the overflow output of the second counter means indicating that the ratio of second events to first events as predetermined by the respective maximum counts of the second and first counter means has been exceeded.
2. A circuit as defined in claim 1 and further comprising a flip-flop having its set input connected to the overflow output of the second counter means and its reset input connected to the overflow output of the first counter means, whereby a signal at the Q output of the flip-flop indicates whether or not said predetermined ratio has been exceeded.
3. In a receiver circuit adapted to receive a digital data stream on a transmission link, the receiver circuit comprising a signal generator adapted to provide a periodic bit corresponding to each one of predetermined occurrences in the data stream, an error detector circuit adapted to provide an error bit corresponding to each error of predetermined type detected in the received data and a source of clock pulses synchronized to the bits of the data stream, a circuit for monitoring the performance of the transmission link comprising:
a first counter means having a predetermined maximum count and being responsive to each of the periodic bits and a clock pulse for increasing its count by one, a second counter means having a predetermined maximum count and being responsive to each error bit and a clock pulse for increasing its count by one, the overflow output of the first counter means being connected to the clear input of the second counter means, and the overflow output of the second counter means being connected to the clear input of the first counter means, a signal appearing at said overflow output of the second counter means representing a flag signal to the receiver circuit.
a first counter means having a predetermined maximum count and being responsive to each of the periodic bits and a clock pulse for increasing its count by one, a second counter means having a predetermined maximum count and being responsive to each error bit and a clock pulse for increasing its count by one, the overflow output of the first counter means being connected to the clear input of the second counter means, and the overflow output of the second counter means being connected to the clear input of the first counter means, a signal appearing at said overflow output of the second counter means representing a flag signal to the receiver circuit.
4. A circuit as defined in claim 3 and further comprising a flip-flop having its set input connected to the overflow output of the second counter means and its reset input connected to the overflow output of the first counter means whereby a signal at the Q output of the flip-flop indicates that the transmission link does not meet its performance criteria.
5. A circuit as defined in claim 4 wherein the predetermined maximum count of the first counter means is substantially greater than that of the second counter means.
6. A method of monitoring the performance of a digital transmission system comprising the steps of:
defining periods during each of which a plurality of errors may occur and for each such period, incrementing the value of a first counter means having a predetermined maximum count, in respect of each period of the first counter means, incrementing the value of a second counter means having a predetermined maximum count by one count if at least one error has occurred therein, resetting the second counter means when the first counter means reaches its maximum count, generating an output signal at the output of the second counter means when it reaches its maximum count, the output signal being effective for resetting the first counter means and being indicative that the performance criteria of the transmission system are not met.
defining periods during each of which a plurality of errors may occur and for each such period, incrementing the value of a first counter means having a predetermined maximum count, in respect of each period of the first counter means, incrementing the value of a second counter means having a predetermined maximum count by one count if at least one error has occurred therein, resetting the second counter means when the first counter means reaches its maximum count, generating an output signal at the output of the second counter means when it reaches its maximum count, the output signal being effective for resetting the first counter means and being indicative that the performance criteria of the transmission system are not met.
7. A method as defined in claim 6 wherein the predetermined maximum count of the first counter means is greater than that of the second counter means.
8. A method as defined in claim 7 and further comprising the step of setting a flag in response to the output signal, whereby an alarm signal may be generated for use by data receiving circuitry.
9. A method as defined in claim 8 and comprising the further step of resetting said flag when the first counter means reaches its predetermined maximum count.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000535582A CA1265222A (en) | 1987-04-24 | 1987-04-24 | Circuit and method for monitoring the quality of data in a data stream |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000535582A CA1265222A (en) | 1987-04-24 | 1987-04-24 | Circuit and method for monitoring the quality of data in a data stream |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1265222A true CA1265222A (en) | 1990-01-30 |
Family
ID=4135504
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000535582A Expired - Fee Related CA1265222A (en) | 1987-04-24 | 1987-04-24 | Circuit and method for monitoring the quality of data in a data stream |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1265222A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0599515A1 (en) * | 1992-11-23 | 1994-06-01 | AT&T Corp. | Error rate monitor |
-
1987
- 1987-04-24 CA CA000535582A patent/CA1265222A/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0599515A1 (en) * | 1992-11-23 | 1994-06-01 | AT&T Corp. | Error rate monitor |
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| MKLA | Lapsed |