CA1259689A - Real-time, localized enhancement of a video image using separable two-dimensional filters - Google Patents

Abstract

REAL-TIME, LOCALIZED ENHANCEMENT OF A VIDEO IMAGE
USING SEPARABLE TWO-DIMENSIONAL FILTERS

ABSTRACT OF THE DISCLOSURE
A video signal producing a raster-scanned image is processed in real time to enhance high frequency characteristics of the image generated by the signal, with the enhancement performed according to a local adaptive process implemented in an apparatus including one or more two-dimensional higher-order filters. Each filter provides a signal corresponding to a statistical measure of the raster image at a point in the image centered in a local area. In each case, the measure is a function of characteristics of the image within the centered area. Each filter is synchronized with the video signal to provide its respective statistical signal substantially in real time and in phase with the input video signal.

Description

1~596~39 REAL-TI~ OCALIZED EN~AO OE MENT OF A VID~O IMAG~
~5I~G SEPARAB~ IWO-DI~E~SIONAL ~ILTERS

BACKGRO~ND OF T~E I~V~NTION
This invention relates to real-time processing of a raster-producing video signal by the use of statistics of the ~ignal that corresponds to a local segment of the raster image~
The quality of display of an image in a video ~ystem can be degraded by extraneous video information in the form ofj for example, shading variations that re~ult from non-uniform illumination of the scene being imaged.
Such background noise of the scene adds a low frequency component to the video sign~ and increases the signal's dynamic range. If the video signal dynamic range exceeds the dynamic range of the display apparatus to which it is fed, low contrast image details can be lost.
One approach to removing the contribution of low-frequency noi e to the dynamic range of video signal in order to permit the display of low contrast local scene . detail~ is to subject the video signal to a conventional local area contrast enhancement procedure that reduces the effect on dynamic range of such noiseO Known procedure~ of this type enhance the contrast in a local area based on statisticc derived ~rom image characteristics in the area.
One example o~ localized adaptive enhancemen~ is found in an article entitled "Local ~daptive Enhancement: A
General Di~cussion In Fast Implementations~ by E. C.
Driscoll Et Al printed in th~ Proceedings o~ the 1983 Machine Processing Of Remotely Sensed Data Symposium. An [DIGIVKPA.K16]

, ~2596~

approach to implementing a local area contrast enhancement algorithm in real time is found in "Real-Time Adaptive Contrast Enhancement," P. M. Narendra Et Al, IEEE
TRANSACTIONS ON PATTERN ANALYSIS AND MACHINE INTE~LIGENCE, 5 VOlr PAMI-3, ~o. 6, November ~981.
In the Narendra apparatus, ~he statistical calculation o~ image area signal is performed by a separable two-dimensional low-pass filter. The filter consists of a conventional first filter section for filtering in the la horizontal direction. The horizontal filter section is in series with a recursive first-vrder filter that filters in the vertical direction. Consequently, a spatial phase delay results between the image produced by the video signal and the signal output by the filter~. As a result, the statistics at a point in the image scene area that is eva~uated by the filter i~ based only on an asymmetric localized area that approaches but does not surround the point. Therefore, the calculated statistic does not account for image scene characteristics for the rest of the localized area around the point.
Therefore, to provide further enhancement of a video image that is proce~sed in a local-area statistical manner, it would be advantageous to calculate the statistics for points in the scene from the variations in more symmetric, localized image areas that contain the points. This would result in calculation of statistical values more representative of image characteristics in the neighborhood of an image point, which, when used in a localized enhancement process, will produce a more desirable image.

DIGIVKPA. K161 12~9~i~9 It is therefore an objective of the present invention to p~ovide an apparatus that performs a real-time, localized enhancement of a video image using image statistics for points in the video image that are derived from local ized areas of the image surrounding the points.
It is a further object of the present invention to provide an improved separable, two-dimensional, hiyher-oraer filter for real-time processing of raster signals without introducing spatial phase delays between the data to be processed and the resulting processed data.
It i8 a still further object of the present invention to provide an improved apparatus performing a local-area contrast enhancement of video images, SUNMARY OF T~ INV~TION
The present invention overcomes the limitations of the prior art local area enhancement apparatus and achieves the stated objectives by provision of a separable two-dlmensional filter having bigher-order, state variable horizontal and vertical filters that cooperate to calculate ~ statistics at a point in a scene image that is based upon ; variations in the scene measured within a scene area containing the point. ~he separa~le filter a~so a~just~ the phase of the resultant 6tatistical signal to substanti ~ 1y align it with the phase of a video signal producing the scene.
; The apparatus of the invention i8 responsive to an input video signal producing a raster-scanned image for ; providing an output video signal with improved image contrast. The apparatu~ includes a processor section that ~DX~IVKPA.K16~

596~39 responds to the input video signal and to one or more signals representative of a statistical value of the input video signal by combinlng tbe input signal and the statistical value signals to produce the improved output video signal.
The processing section ob~ains the statistical value signal from a higher-order filter section that responds to the input video signal by producing a statisti.cal slgnal based upon characteristics in the input signal occurring within a determinable area of the raster produced by the input signal.
Finally, the apparatus includes a phase adjustment section coupled between the processing and filter sections that adjusts the phase of the statistical signal to align it with the phase of the input video signal and provides the phase-adjusted statistical.signal to.the processing section.
According to a broad aspect of the invention there is provided an apparatus for providing, for a time-varying input siynal producing a raster-scanned image, a multidimensionally-filtered output signal, comprising, a first higher-order filter means, responsive to said input

2~ signalr for producing a dimensionally-filtered signal representative of the subjection of said input signal to at least a fir~t filter function having a first filter bandwidth;
means for providing plural value signals, each corresponding to the value of one of a set of state variables;
a second hlgher-order filter means responsive to said value ~iynals and to said dimensionally-filtered siynal for subjecting said dimensionally-filtered signal to a second filter function having a second filter bandwid~h to produce a multidimensionally-, 59~;~39 4a 66128-184 filtered output signal representati.ve of the subjection of said input signal to said first and second filter ~unctions; and means responsive to said first and second filter bandwidths for adjusting the phase of said multidimensionally-filtered output signal to substantially align the output s:ignal spatial phase with the spatial phase of said input signal.
According to another broad aspect of the inven~ion there is provided an apparatus responsive to an input signal representing a raster-scanned image for providing an output signal representing said imag0 with increased contrast characteristics, comprising:
adaptive processor means responsive to said input signal and to a mean value signal indicative of the mean value of said input signal at a point contained in a localized portion of the image represented by said input signal ~or producing a difference signal representative af a dif~erence between said lnput and mean value signals;
signal processing means in said adaptive processor means responsive to said input signal, to said mean value signal, and to a variance signal representing the standard deviation of sald input si~nal over said localized image portion for producing an OUtpllt signal representing said image by increasing the contrast in said image to a selected value; and multidimensional filter means responsive to said input signal and to said difference signal for producing said mean value signal and said variance signal, sald multidimensional filter means including:
horizontal means responsive to said input signal for 5~9 4b performing horizontal low pass filtration within a horizon~al filtration bandwidth of a horiæontal portion of said image and vertical means, responsive to said horizontal low pass filtration for performing vertical low pass flltration within a vertical filtration bandwidth of each of a series of vertical portions of said image taken along said horizonal portlon, said vertical means providing a filter signal representative of said vertical low pass ; filtration, ad~ustment means for selectively adjusting said vertical bandwidth; and field means responsive to said iilter signal for produclng said mean value signal and for aligning the phase o~ said mean value slgnal with the phase of said input signal based upon said adjusting.
According to another broad aspect of the invention there is provided a video processing apparatus for enhancing presentation characteristics of a raster-scanned image signal, comprislng:
processing means responsive to an input signal representativ~
of a raster-scanned image and to a statistical signal representative of a statistical value of said input signal for combining said input signal and said statistical slgnal to produce an output signal representing an enhancement of said raster-scanned image by increasing the contrast in the image;
plural-order filter means responsive to said input signal and to a filter variable signal for producing said statistical siynal durlng a first image raster $ield deflned by said input signal, - said statistical signal produced by two-dimensional filtration of ~5~36~3~
4c said input signal wlthin a horizontal filter bandwldth and a verttcal filter bandwidth, at least one of said filter bandwidths ; being determined by said filter variable signal; and phase adjustment means coupled between said processing means and said plural-order filter means for adjusting the phase of said statistical signal to su~stantlally equal the phase of said input signal by producing said filtex variable signal based upon two-dimensional flltration of a second image raster filed defined by said input signal, said second image raster field corresponding to, but preceding, said first image raster field.
It will become evident ~hen the detailed description of the preferred embodiment is read in light of the below-described drawings ~hat the apparatus of the invention provides objectives and advantages other than ~hose described above.
BRIEF DESCRIPTIO~ OF THE DRA~ING~
- Figure 1 is a block diagram illustrating the apparatus of the invention used to implement a local adaptive contrast enhancement process on an input video signal that produces a raster-scanned video image.
Figure 2 illustrates how the separable two-di~ensional filter of the invention operates across a representative :L2596~

horizontal line o~ video ln the raster produced by the input video sign~ of Figure 1.
~Figure 3A is a schematic diagram illustrating the ;pre~erred hardware implementation of a separable, two-5 dimensional filter used in the apparatus of tbe invention.
Figure 3B is a block diagr2m of digital control logic used to control the operations of the filters exempli~ied by Figure 3A.
~ igure 4 is a timing diagram illustrating the sequential operation of the filter of Figure 3.
Figure 5 illustrates the memory organization of the field storage device of the Figure 3 ~ilter and its manipulation by associated elements.
Fiyure 6 is an illustration of a localized segment of the raster produced by the video signal of Figure 1 that demonstrates how the statistical sign~ produced by the Figure 3 separable filter is aliyned in phase with the input video signal of Figure 1.
:
~20 D~TAI~ED D~SC~IPTION OF ~ PREFERRED EMBODIMB~T
;The apparatus of the invention is illustxated in Figure 1. The input to the apparatus con~ist~ of a standard RS-170 video signal that is produced by a video output device such a~ a vidicon, laser disc, or video cassette recorder. As is known, the RS-170 signal can be fed directly to a standard video monitor with a CR~ screen upon which an electron beam modulated b~ the input Yideo signal will generate a raster-scanned image. The beam is conventionally moved across the ~creen from left to right to trace a horizontal line, with a quick return to the le~t again, and ~rom the top downward in [DIGIVKPA.K16]

.

~L~59~9 sub~equent lines. At the bottom of the screen/ the electron beam will be returned to the top left corner, in a process that is repeated. Conventionally the movement of the beam in the scanned format traces out a rectangular pattern called a raster. The movement of the beam is referred to as raster-scanning.
The viaeo standard followed in the United States provides 525 raster lines displayed at 30 raster ~rames per second, each frame consisting of two interlaced fields o~
262.5 lines, fields being displayed at 60 times a second.
The invention described in this specification utilizes a novel hardware structure for e~lancing, in real time, the quality of images produced when the electron beam is modulated by an input video signal. The term "real timen mean~, for example, that the present invention is able to keep pace with a standard video input signal without loss of signal and to concurrently exhibit live viàeo images in the same fa~hion as a convention~ television set, while also greatl~ enhancing the quality of the displayed image. The applicant's invention employs both digital and analog processing to enhance, for example, the contrast of the displayed image.
Conventional algorithms are known that can be embodied in electronic hardware to process standard video signals in real time. One such algorithm describes a process for local adaptive contra~t control of a video image. Thi8 algorithm is illustrated in ~iyure 1 as eg ~1) (corre~ponding to equation (1)). In equation (1~, Z is a processed output video signal with enhanced contrast resulting from the subjection of an input video signal X to ~DIGIVKPA~K16~

1~96~3 the adaptive algorithm; X is the mean of X at a point contained in a localized area of the video image produced by X; MD is a prede~ermined mean brightness; X is the standard deviation of X within a localized area; D is desired standard deviation; and sets the level of desired background bias in the video image.
'rhe ~ gorithm of equation ~1) can be implemented in hardware by a reasonably skilled analog circuit engineer having experience in the design of video analog processing circuits, given X and X as inputs. In the preferred embodiment, the hardware-implemented algorithm of eguation tl) is embodied in a real time video proce~sor block 10.
Th~ inp~t ~ignal Xin that is provided to the processor block 10 is provided by a video preconditioning block 12 that accepts an i~put video signal from any standard video signal souece and preconditions the signal. Such pre-conditioning can include, for example, a DC restore operation, that imposes a DC reference for digital processing. The pre-cQnditioning can al~o include blanking insertion that consists of inserting an artificial voltage level during the video ~ignal blanking interval, gain control, and termination impedance matching, ~ he preconditioned video signal is fed to the processor block 10 which implements the algorit~l of equation (1) to 2S process intensity variations in the image represented by the video signal in order to sharpen the image contrast and highlight image details. Effectively, the algorithm accomplishe~ thefie objectives by removing unwanted portions of background components from the signal, such as low frequency variation resulting, for example, from non [DIGIVKPA.K16]

~259689 optimum illumination of the scene which is to be disp~ayed.
The algorithm then stretches contrast in local areas of the image to some desired value.
A standard synch stripper and timing circuit 14 senses horizontal and vertical synchronizat.ion components in the input vicieo signal and employs stanc3ard timing and synchronization circuitry to produce a signal VSYNC
representing the vertical synchronization that signals the beginning of a video field. The synch stripper 14 also pr~vides a signal HSYNC, indicating the beginning of a horizontally-swept line. Also provided are a signal A/D CLK
that clocks conversion components and a MASTER CLK signal to clock and synchronize various operation6 in the apparatus of the invention.
The variables necessa ~ to perform the algorithm embodied in the processor block 1~ are all input to the block as voltage signals. The variables X and X ~re derived from a pair of two-dimensional, progr~lmable, low-pass filters 16 and 18 that are described in greater detail below. The other variables D, , ~D~ and A are derived from the outputs of variable DC voltage sources, not shown, that are adjusted by adjustment mechanisms 20, 21, 22, and 23. The voltage sources 20~23 can comprise, ~or example, potentiometers connected to a common DC source.
~5 Both o~ the filter~ 16 and 18 are higher-order f ilters.
That is, they both implement f ilter function~ having an order of two or more.
The processor block 10 provides, as output ~ignals, the pre-conditioned video input signal X and the absolute difierence between X and X to the ~ilter~ 16 and 18, ~ [DIGIYKPA.R16]

~ -~259~89 g respectively. These variables are preferably in the form of voltage signals that are input to the filters. In addition, another variable voltage ~ource, not shown, but adjusted by the adjustment mechanism 24 provides an input signal to S both filters 16 and 18 that determines the bandwidth of the filter in a manner described below. Finally, a conventional single-pole, single-throw switch 25 provides a freeze-frame signal to both of the filters 16 and :l8 that produces an effect described below.
The operation of each of the filters 16 and 18 is illustrated conceptually in Figure 2. As is known, computation of the local weighted mean X and the approximate local weighted standard deviation X can be implemented by low pass filtration of X and the absolute value of X - X, respectively. Sin~e the computation of these statistical value~ is to be performed over a localize~ area, the filtration is two-dimensional. That is, filtration m~st be impl~nented in both the horizontal and the vertical direction over the desired area. TWo dimensional filtration is illustrated in Figure 2 where an input (which can be either X or the absolute value of X - X) is input to a horizontal low-pass filter that filters each line of video produced by the input video signal. In series with the horizontal filter is an array of a n~mber of vertical ~ilters, one indicated by 27, tha~ pexform filtration in the vertical dixection o~ the input signal. Preferably, there is a sufPicient quantity of vertical filters to meet Nyquist ~ampling r ~ uirement 8 on the horizontally-filtered signal.
Each of the vertical filters has an effective bandwidth such that the filter response spans a plurality of scan [DIGIVKPA.K16]

~2596~g lines. Further, the bandwidths of both the horizontal and vertical filters can be adjusted down from these limits e~tablished by sampling requirements to provide larger effective local areas over which the statistical vi~ ues are computed.
Thus, conceptually, each line of the raster image produced by the input video sign~ and filtered by the horizontal filter 26 can be considered to be separated into N con~ecutive vertical filter (VF) segments. Each VF
segment of each line is processed by the respective vertical filter 27 defining the segment. The processing time for each segment is determined by the composite bandwidth of the two filters.
Figure 34 illustrates the preferred structure ~f both Figure 1 filters 16 and 18. The filters 16 and 1~ are controlled by digital control logic 30 illustrated in Figure 3B and including, preferably, a programmable logic array (PLA) that receives the MAS~ER CLK, HSY~C, and VSYNC
signals. In addition, the output of the variable voltage source adj~ted by mechanism 24 is fed in digital form to the logic circuit 30 through a conventional analog-to-digital (A/D) converter 32 that produces a digital signal D
which consists of a code corresponding to the DC signal level provided to the converter's input. The digital control logic 30 produces, among others, the following representative ~ignals that are useful for controlling the operation of the filters: reset ~R); latch ~Ll and L2);
output transfer ~O~ tate-variable transfer ~T)7 address ~Ao - Ai); write ~WR); output select ~OS); and sample ~S/H).

[DIGIVRPA.K16]

~25~39 The filter of Figure 3 includes a higher-order hori~ontal filter section 32 that receives an input signal teither X or the absolute value of X - X). In the preferred embodiment, the horizont~ filter 32 comprises a conventional second-order, active, state-variable filter including an input s~mming amplifier 40, a first integrating amplifier 42, and a second integrating amplifier 43. The bandwidth of each of the integrating amplifiers ~2 and 43 is set by the RC time constant established by the resistance and capacitance coupled to its inverting input port~ Each of the bandwidths can be adjusted by adjustment of a respective one of the digitally-controlled resistors 44 and 450 The digital signal controlling the digital resistors 44 ana 45 is the control signal D. The control signal ~ is taken from the output of the A/D converter 33 and is, therefore, set by the adjustment of the variable voltage source contr~lled by the mechanism 24.
The filter of Figure 3 also includes a vertic~ filter section 44 that processes the filtered output from the horizontal filter 32 available on the signa~ line 46. The vertical filter section 44 includes a second second-order, : low-pass, state-variable filter including a summing :~ amplifier 48 and integrating amplifiers 50 and 5~. The bandwidth of the integrating amplifier 50 is set by the RC
product of the digitally-controlled resistor 53 and the integrating capacito~ 54. ~imilarly, the bandwidth of the in~egrating amplifier 52 is set by the digitally-controlled resis~or 55 and the integrating capacitor 56.
~he filter of Figure 3 also includes a first ~onventional sample and hold ~S/H) circuit 58 connected to [DIGIVKPA.K16~

~L~596~39 sample the voltage on the integrating capacitor 54. A reset ~witch 59 is closed after the operation o~ the S/~ circuit 58 to discharge the integrating capacitor 54. Similarly, a S/~ circuit 60 samples the voltage on the integrating capacitor 56, which is thereafter discharged by closure of a reset switch 61. The sampled voltage values held on the S/H
circuits 58 and 60 are fed separately through a multiplexer 62 to an A/D converter 64. The digitized outp~t from the converter 64 is fed to tbe input data port ~DATA IN) of a field storage device 66. The output port of the field storage dev i ce 66 feeds a pair of digital-to-analog converter~ ~AC) 68 ana 70. The DAC 68 is connected through an injection capacitor 72 to char~e the integrating capacitor 54 to an initial voltage representing one state variable of a secQnd order filter function implemented by the filter section 44. Similarly, the output of the DAC 70 : is fed through an injection capacitor 74 to charge the integrating capacitor 56 to another initial voltage representing another state variable of the second order filter function implemented by the filter section 44.
The state variable voltages on the capacitors 54 and 56 are changed N times durin~ each line of video. This effectively provides the N vertical filters illustrated in Figure 2, since the sampling and storage of the voltages on the capacitors 54 and 56 permits each state variable to be stored and used again to establish a filter function at the cor~e~ponding image point and display time in the line ~ollowing the pre~ent one.
The DATA OUT port of the ~ield storage deYice 66 is also connected to a DAC 76 whose output is fed through a EDIGIVRPA. R161 . .

1~596~39 --13 ~

conventional low-pass reconstruction fllter 77. The output of the low-pass filter 77 is provided as the output of the filter.
In operation, an input signal is fed into the filter of Figure 3 and is processed initially by the horizont~ filter 32 which provides its filtered output on signal line 46 to the vertical filter seckion 44. Then, the N effective vertical filters are successively switched into series with the filter ~ignal by periodically changing the filter state : 10 variables of the vertical filter section 44 by charging the integrating capacitors 54 and 56 to initial states. Thus, the ver~ical filter section is time-division-multiplexed in ~uch a way as to appear as N distinct vertic~ filters.
The ~equence of oEerations necessary to save and restore the state variable vo~tages on the vertical filter ~ection of Figure 3 is illustrated by the waveforms of Figure 4. It will be recalled that the state variables of the vertical filter section 44 are initi~ ized N times for each horizontal line on the image raster to provide N
verti cal ~ il ters that are all seq uenti ~ ly accessed once each horizontal raster line.
~ he effective operating time of any one of the vertic~ filters lvertical filter operation time) is tsweep/N, where t8weep is the time required to sweep one 2S horizontal line of video and N i9 the number of times the vertical filter section 44 has its state variables changed.
During the operation time for a vertical ~ilter, the digital control logic 30 provides a control signal OS to the multiplexer 62 that enables the multiplexer to select the held value output by either of the S/H circuits 58 or 60.

[DIGIVKPA.K16]
;~

~5~36~39 Preferably, when OS is high, the GUtpUt of the S/H circuit is selected; when OS is low, circuit 58 is selected.
When either of the S/~ circuits is selected, the held value is provi~ed to the A/D converter 64, with the converted v~ ue being stored in the field storage device 66 at a storage address, described below, when the WR signal transitions to a low state.
Interlaced with the write operations are read operations that obtain stored state variable voltage v~ ues from the field storage device 66 and provide them through the DAC's 68 and 70 to charge tbe integrating capacitors 54 and 56. A read operation is effected whenever the WR signal is high and an address is provided to the field storage device 66. Each of the DAC's 68 and 70 ha6 an associated latch, not shown, that receives data ~rom the field storage device 66. The signal Ll latches data from the storage device 66 to the latch of DAC 68, while the signal L2 latches data to the DAC 70. ~he addressed state variable data that is staged to the DACIs 68 and 70 through their associated latches i held in the latches until their outputs are made avallable to the DACIs 68 and 70, which permits the charging of the integrating capacitors 54 and 56, and thereby the setting of the state variables o~ the ith vertical filter. The phasing of the latch operations is indicated by an address/latch control ~A/L CNTRh) generated internally by the digital control logic 30~ the signal is illustrated in ~igure 4~ During the rising edge 78, L2 i8 generated, and on the rising edge 79~ Ll is generated.
The s~uence o~ memory operations required of the field storage device 66 in the initialization and sa~pling of the [DIGIVKPA.K16]

9~g ith vertical filter are indica~ed in Figure 4, Pre~erably, first, data is read from the device 66 and latched for the DAC 70 with the edge 78 of the A/~ CNTRL signal. Next, the data held in the S/H circuit 60 is written to storage when the WR signal goes low following the edge 78. ~l idle state follows. Then, data is read into the latch for DAC
68, followed by writing of data to storage from S/H circuit 58. Then, filter output data for DAC 76 is read from the field storage device 66.
Reference to Figure 5 further illustrates the sequence of operations involved in setting and storing sta~e variable voltage values for the vertical filter section 44. A pair of memory sector maps 80 and 82 signify respective sectors of addressable memory space in the field storage device 66.
The memory map 8~ constitutes N sequentially-addressable : storage locations, each for the storage of a state variable voltage value provided to the integratin~ capacitor 54, The memory map 82 has a two-dimensional 256XN matrix of addressable locations, each storing a state variable voltage value for the integrating capacitor 56. It should be evident that each horizontal address supplied to the matrix memory map 82 and to the unidimensional memory map 80 : corresponds to one of the vertical filters (VF). Each vertical address provided to access the memory map 82 ::25 corresponds to one of 256 video lines which, as known, are sufficient to form the active portion of a raster field.
Thus if, for example, the filter of Figure 3 i8 ~ processing an image point contained in an image portion ::corresponding to the third vertical filter sector o~ line 3, it will have been initially configured by charging the .[DIGIVKPA.K16]
.:~

~5~ 39 capacitor 54 to a voltage corresponding to the state variable v ~ ue stored at address YF3 in the memory sector 80 and the capacitor 56 to a voltage value s~ored at the memory location addressed by the combination of vertical address 2 and horizontal address VF3 in memory sector 82. Moreover, while the vertical filter section 44 is operating with these initial state variable values indicated by a P in Figure 5, the processed state variable samples from its previous config~ration (VF2) will be w~itten into the respective memory spaces indicated by WR, while the state variables stored in the subsequent adjacent memory spaces corresponding to VF4 (indicated by RD in Figure 5) will be provided to the latches associated with the DAC's 68 and 70D
Returning to Figure 4, the seg~ence of resetting and sampling operations necessa~ to sample and clear the integrating capacitors 54 and 56 are illustrated.
Immediat~y prior to the beginning of the operation time for the jth vertical filter, a reset R signal is provided to operate the reset switches 59 and 61, discharging the capacitors 54 and 56. At the same time, the DAC's 68 and 70 are held at a reset value. Following the reset period indicated in the R signal waveform of ~igure 4, the switches 59 and 61 are opene~ when the R siqnal is ri~ing at edge 83.
Next, tbe first falling edge 84 of a transfer ~ signal 2S permits the state variable volta~e values h~ d in their associated latchefi to be transferred to the DAC's 68 and 70.
This permits the state variable voltages to be applied to the capacitors 54 a~d 56 and causès the filter section 44 to begin operation as the ith vertical filter. This is [DIGIVKPA~K16]

~2596~39 indicated by the section of the tran~fer T waveform labelled ~filter operation".
Toward the end of the jth filter operation period, the state variable voltage values in the capacitors 54 and 56 will be sampled and held in the S/H circuit~ 58 and 60, respectively. This occurs when the sample S waveform as~umes the low state ~ollowing signal transition 860 Referring once again to Figure 3, it can be appreciated that the jth state variable voltage on the integrating capacitor 56 also represents the output of the jth vertical fi-ter. ~owever, as is known, both the horizontal and vertical filter sections introduce respective pha~e delays into the output signal available on the capacitor 56 that impose a phase difference between the input signal being processed and the resultant processed output. The delay can be understood conceptually with reference to Fi~ure 6.
Fiyure 6 illustrate~ a magnified portion of a field of video prod~ced by the processed video output ~ignal Z of Figure 1. Reference numeral 87 marks an image element o~ a line corresponding to the present state of the input video signal X. A composite delay, indicated by reference numeral 88, i~ introduced ~y the filter sections 32 and 44, and includes a horizontal pha5e component ~ OH) and a vertical phase component ( OV)-In the apparatus of the invention the horizontal phase delay is treated as a coar~e measure corresponding to a nwmber of VF operating periods and a fine portion corresponding to a time that i8 less than one of the VF
; operating periods. ~he vertical delay is treated as a number o~ ~can lines in a field. In order to reregi~ter a l~IGIVKPA.~16 :

1.~5~689 proces~ed output (X or X) to be spatial~y in phase with the input video ~ignal, the processed output is not provided ~o the re~ time video proces60r 10 until the following field Thus, if, after supplying the jth ~tate variable voltage~ on the vertical ~ilter section 44, the vertical address i8 offset by a number of lines corresponding to the vertic~
delay, while the horizontal addres~ is offset by a number of VF segments corresponding to the coarse portion of the horizontal delay, a value will be obtained from the memory storage sector 82 that is out of phase with respect to the presant input signal only by the value of the fine portion of the horizontal delay. This fine horizontal delay portion can be used to offset the provi~ion of the filter output by an amount required to bring the output sign~ sub~tantially into phase with the input signal. This is illustrated by the OUTPUT TRANSFER (OT) waveform of Figure 4 where the filter output i~ provided to the DAC 76 after the Yertical and horizontal offsets have been made to the respective addre~ses of the memory sector 82 to obtain the correct filter output. The n~w filter output i~ provided to the DAC
76 on the po~itive edge 90 of the OUTPUT TRANSFER signal, which is adjusted by the digital control logic 3~ to off6et the filter output by an amount to compensate for the fine portion of the horizontal delay.
The structure of the apparatu~ of the invention tbat per~orm~ tha phase adjustment of the output provided by the Figure 3 filter i~ illus,trated in Figure 5. The digital control logic 30 can include programmable and memory circuit~ that permit implementation of a vertical lookup table (VLU~) and a horizontal lookup table ~HLUT) that [DIGIVRPA.K16]

~S9~9 respond to the adjustment signal D provided to tbe digitally-controlled resistors 44, 45, 53, and 55. The range of digital values over which the signal D can be adjusted constitutes an address signal input to the two 5 lookup tables. Since the adjustment signal D establishes the complex impedance o~ the horizont~ and vertical filter sections, it can be transformed into a value of phase delay for any impedance setting it establishes. Thus, the lookup table~ store, at each addressable location, the number of lines or VF sectors corresponding to the vertical and horizontal phase delays resulting from the value of the adjustment ~ignal D defining the address for that ~ector.
The vertical phase offset in number of lines is fed to a vertical address logic section, while the coarse horizontal phase of~set in number of VF sectors i~ fed to a horizontal addres~ logic section. The vertic~ and horizontal addresses used to obtain the state variable voltage value for the capacitor 56 that is associated with the current VF segment are offset from the horizontal and vertical addresses provided to the memory sector 82 and the state variable voltage value stored at the location corresponding to the offset address values i~ provided to a la$ch, not shown, associated with the DAC 76.
The fine horizont~ adjustment that i8 obtained from the currently-addres~ed horizontal lookup table location is fed to a ~ine delay timing sectlon of the digital control logic 30 to provide the output transfer signal illu~trated in ~igure 4, which enables the DAC 76 to provide the output at precisely the point of time in the current VF ~ector that will align the phase of the output signal with that o~ the DIGIVKPA.K15~

~259~i~9 input vi~eo signal of Figule 1~ This insures proper phasing between the statistical sign~ provided by the filter of Figure 3 and the video input signal o~ Figure 1.
Returning to Figure 4, the sequence of memory 5 operations a~sociated with provision of an output statistical sign~ through the DAC 76 with the vertical filter memory oFerations of the Figure 3 circui~ can be bett~r understood. To synchronize the output memory operations with the vertical filter memory op~rations, an address adjustment signal ADD ADJ that is generated internally in the digital logic 30 transitions before the beginning of the jth VF sector to a negative state at reference n~leral 92 which signals the horizontal and vertical address logic se~ments of the digital control logic to provide the offset horizontal and vertical addres~eæ
to obtain the reguired filter output value from the me~oLy sect~r 82, Thi~ data is provided to the latch, not 6hown, associated with the DAC 76 ~o that at the next positive transition of the O~TP~T TRANSFER signal 90, the DAC 76 will 20 produce the proper output signal. Then, the address adjustment signal ri~es at 93 in order to change from the addresses indicating the storage location for the output to those indicating the location of the state variables to be provided next.
In 60m~e applications, it may be useful to ~tore the contents of the memory sector~ 80 and 82 as unvarying masks a~ter the filter of Figure 3 has operated for ~ period o~
time, ~n this case, the switch 25 i8 closed. Closure of the swikch 25 causes the digital control logic 30 to lock the WR signal into an unvarying high ~tate. This keeps the lDIGIVKPA. X161 ' 125~6~9 state variable voltage values in memory sectors 80 and 82 from being changed. ~hus, as the filter operates, the field of values output by the filter of figure 3 thxough the DAC
76 will be "frozenn.
S Obviously many modifications and variations of the present invention can be made in light o the above teachings. However it iB to be understood that within the scope of the appended claims the invention may be practiced other than as specifically described.
We claim:

~DIGIVKPA.~16]

Claims (6)

1. An apparatus for providing, for a time-varying input signal producing a raster-scanned image, a multidimensionally-filtered output signal, comprising:
a first higher-order filter means, responsive to said input signal, for producing a dimensionally filtered signal representative of the subjection of said input signal to at least a first filter function having a first filter bandwidth;
means for providing plural value signals, each corresponding to the value of one of a set of state variables;
a second higher-order filter means responsive to said value signals and to said dimensionally-filtered signal for subjecting said dimensionally-filtered signal to a second filter function having a second filter bandwidth to produce a multidimensionally-filtered output signal representative of the subjection of said input signal to said first and second filter functions; and means responsive to said first and second filter bandwidths for adjusting the phase of said multidimensionally-filtered output signal to substantially align the output signal spatial phase with the spatial phase of said input signal.

2. An apparatus responsive to an input signal representing a raster-scanned image for providing an output signal representing said image with increased contrast characteristics, comprising:
adaptive processor means responsive to said input signal and to a mean value signal indicative of the mean value of said input signal at a point contained in a localized portion of the image represented by said input signal for producing a difference signal representative of a difference between said input and mean value signals;
signal processing means in said adaptive processor means responsive to said input signal, to said mean value signal, and to a variance signal representing the standard deviation of said input signal over said localized image portion for producing an output signal representing said image by increasing the contrast in said image to a selected value; and multidimensional filter means responsive to said input signal and to said difference signal for producing said mean value signal and said variance signal, said multidimensional filter means including:
horizontal means responsive to said input signal for performing horizontal low pass filtration within a horizontal filtration bandwidth of a horizontal portion of said image and vertical means, responsive to said horizontal low pass filtration for performing vertical low pass filtration within a vertical filtration bandwidth of each of a series of vertical portions of said image taken along said horizontal portion, said vertical means providing a filter signal representative of said vertical low pass filtration;

adjustment means for selectively adjusting said vertical bandwidth; and field means responsive to said filter signal for producing said mean value signal and for aligning the phase of said mean value signal with the phase of said input signal based upon said adjusting.

3. The apparatus of Claim 2 wherein said vertical means includes a state variable filter having an order of two or more and said multidimensional filter means further includes state setting means for setting the state variables of said state variable filter for each of said series of vertical portions.

4. The apparatus of Claim 3 wherein said state variable filter includes a pair of serially connected integrating circuits, each having an integrating capacitor and said state setting circuit includes means for setting each of said integrating capacitors to an initial voltage corresponding to a respective state variable.

5. The apparatus of Claim 2 wherein said field means includes a field storage means for sampling said filter signal during the vertical filtration of each of said vertical portions and for storing an array of filter signal samples corresponding to a field of said image and addressing means responsive to said input signal and to said adjustment means for obtaining from said field means the stored filter signal samples for a stored field of said image in synchronism with said input signal by advancing from a first location in said array where a sample is being stored to a second location in said array offset from said first location by a distance corresponding to said horizontal and vertical bandwidths.

6. A video processing apparatus for enhancing presentation characteristics of a raster-scanned image signal, comprising:
processing means responsive to an input signal representative of a raster-scanned image and to a statistical signal representative of a statistical value of said input signal for combining said input signal and said statistical signal to produce an output signal representing an enhancement of said raster-scanned image by increasing the contrast in the image;
plural-order filter means responsive to said input signal and to a filter variable signal for producing said statistical signal during a first image raster field defined by said input signal, said statistical signal produced by two-dimensional filtration of said input signal within a horizontal filter bandwidth and a vertical filter bandwidth, at least one of said filter bandwidths being determined by said filter variable signal; and phase adjustment means coupled between said processing means and said plural-order filter means for adjusting the phase of said statistical signal to substantially equal the phase of said input signal by producing said filter variable signal based upon two-dimensional filtration of a second image raster field defined by said input signal, said second image raster field corresponding to, but preceding, said first image raster field.