CA1209705A - Digital code translator - Google Patents
Digital code translatorInfo
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- CA1209705A CA1209705A CA000431626A CA431626A CA1209705A CA 1209705 A CA1209705 A CA 1209705A CA 000431626 A CA000431626 A CA 000431626A CA 431626 A CA431626 A CA 431626A CA 1209705 A CA1209705 A CA 1209705A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/50—Conversion to or from non-linear codes, e.g. companding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G7/00—Volume compression or expansion in amplifiers
- H03G7/007—Volume compression or expansion in amplifiers of digital or coded signals
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- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Error Detection And Correction (AREA)
Abstract
DIGITAL CODE TRANSLATOR
Abstract The most significant bits of the input digital word address a read-only memory (ROM). Stored at each ROM
address is a table of instruction words, one instruction word for each bit in the output word. The instruction words direct a switch to select each bit for the output word from a choice of 1, 0, or an input bit. The instruction words also command selective bit inversion and selective inclusion of the bit in a parity check.
Implementation of the translator with commercially available hardware is described.
Abstract The most significant bits of the input digital word address a read-only memory (ROM). Stored at each ROM
address is a table of instruction words, one instruction word for each bit in the output word. The instruction words direct a switch to select each bit for the output word from a choice of 1, 0, or an input bit. The instruction words also command selective bit inversion and selective inclusion of the bit in a parity check.
Implementation of the translator with commercially available hardware is described.
Description
Related Applications This application contains subject matter which is related to the subject matter disclosed in U.S. Patent No. ~,486,876 which issued to Gaunt et al on December 4, 5 1984 and U.S. Patent No. 4,488,295 to Sharper which issued on December 11, 1984.
Background of the ~nvention This invention is in the field of Digital Communications; it relates particularly to the translation of information from one digital form to another.
~s digital communications proliferate, and more and more information is communicated via digital facilities, the need to change codes and formats to fit the facility also increases. In one notable example, a system for inserting broadband audio program signals into T carrier time slots, which is described in the Gaunt-Giammusso application referred to abovel encodes samples of the program signal into 14-bit linear pulse code modulated (PCM) words in offset-binary form. The l~-bit words are then compressed into ll-bit PCM words in sign-magnitude form, the order of the bits is rearranged, and a parity bit is added to reflect parity over only certain, not all of the bits. In another example, the Federal Republic of Germany has proposed to CCITT in Contribution #109 to Study Group ~V, May, 1982, another format for compressed 12-bit words for sound program signals.
According to the German proposal, the 12-bit words are also made up of eleven PGM compressed code bits and one parity bit; the more significant bits are interleaved with the less significan~ bits, and parity is taken over only the five most significant bits.
While 8-bits compressed analog-to-digital encoders are common, ll-bit compressing encoders are not.
Furthermore, in some cases, such as the Gaunt-Giammusso arrangement, an unusual compression characteristic is required. Four~een or fifteen bit linear encoders, on the )9~1S
other hand, are easily purchased, and the resulting output words can be compressed by a digital code translator.
It is well-known in the art to translate from one code to another by means of a memory look-up table.
Each possible input code word forms an address of a read-only memory (ROM). Stored at the address is the translated output code word. In the case of a 14-bit input code, however, such a scheme requires 2 4 memory addresses.
With 12 bits per output word, the total memory requirement would be 214 x 12 - 196,608 bits of memory, a rather large amount~ Other available translation methods involve the use of logic circuitry. For very simple translations, available logic chips can be applied, but more complicated translators require considerable design effort and often custom logic integrated circuits. Unless contemplated production is very high volume, such expenditure may not be warranted.
An object of this invention is an inexpensive digital code translator that can convert linearly encoded PCM words to compressed PCM words.
Another object is a digital code translator that can perform compression, selective bit inversion, bit order rearrangement and selective parity inclusion.
~ third object is a code translator that can be assembled from readily available parts.
A fourth object is a code translator the output format of which can be entirely changed by a mere change of the contents of a memory.
~ummary of the Invention In accordance with an aspect of the invention there is provided a digital code translator for reversibly translating an input word into an output word comprising memory means having a multiplicity of addresses for storing at each said address a table of instruction words, address inputs and instruction word outputs; means connecting a ,,1~ .~1 ~2~9~7~S
- ~a -Eirst predetermined selection of bits of said input word to said address inputs; selector switch means having instruction inputs connected to receive said instruction words, a plurality of bit inputs and a switch output for connecting a selected one of said plurality of bit inputs to said switch output according to an instruction word;
means connecting a source of potential representative of a "1'l to a first one of said bit inputs; means connecting a source of potential representative of a zero to a second one of said bit inputs; and means connecting a second pre-determined selection of bits of said input word to others of said bit inputs, respectively; said selector switch means choosing the bits of said output word from said bit inputs in response to the respective instruction words of the table addressed by said first predetermined selection of input word bits.
In this digital code translator for reversibly translating an input word into an output word, a first predetermined selection of bits of the input word addresses a memory. Stored at each such address is a table of instruction words. A bit selection switch chooses each bit ~2OE~71~)S
of the output word from a choice of ~ æero or any one of a second predetermined selection of bits of the input word, according to a respective instruction word. Bit inverting means and parity switch means, both also responsive to the instruction words may be added to provide selective inversion of individual bits and selective inclusion in a parity check of individual bits.
Description of the Drawings FIG. 1 is a functional block diagram of an embodiment of the invention.
FIG. 2 is a compression characteristic useful in explaining the operation of the invention.
FIG. 3 is a schematic diagram of a particularly useful embodiment of the invention.
Detailed Description _ To explain the invention in detail, I refer now to FIG. 1, which is a functional block diagram of an embodiment of the inven~ion. This embodiment will be described in connection with the translation of 14-bit linear PCM words into 12-bit compressed PCM words at a 32kHz rate, although the invention is not, of course, limited to such use.
In FIG. 1 a read-only memory (ROM) 41 is addressed by the six most significant bits of the 14-bit linear input word- At each of the sixty-four possible addresses of memory 41 is stored a table of twelve instruction words. A 1 to 12 counter 43 addresses the twelve table entries in order, under control of a 334kHz clock. The table of twelve stored instruction words is therefore read out in order in response to each 14-bit input word, which may be representative of a single analog 5 ample.
Four bits of each output word of memory 41 address a bit selection switch 45; one bit addresses an inverter switch 47, and one bit addresses a parity switch 49. Bit selection switch 45 operates to selectively connect its output 51 to one of its inputs 0 through 15 under :
s control of each output instruction word from memory 41.
The inputs of switch 45 include the third through ourteenth bits of the linear input word, an always low (zero)input 0, an always high (1) input 1 and the output 15 of a parity register 59. Inverter switch 47 selectively connects bit selector output 51 to code translator output 61 directly, or alternatively through an inverter 63.
Parity switch 49 select:ively connects code translator output 61 to t~e input of a parity register 59. In response to each 14-bit encoded sample input, there~ore, ROM 41 utters twelve instruction words of six bits each.
Each instruction word determines one output bit of the 12-bit compressed output word, whether that bit is inverted, and whether it is included in the parity check.
The ability to select one bit at a time from a choice o~ 1, 0 or a particular input bit allows compression to any characteristic. Consider, ~or example, the translation o~ Table 1.
14--BITLINEAR ll--BIT COMPRESSED
SIGNMAGNITUDE SIGNCHORD STEP
_ SlABCDEFG--------- S 110 ABCDEFG
The ll-bit compressed column is made up of the sign bit S, three cord bits, and seven step bits A through G. Bits represented by dashes in the 14-bit linear column 35 are discarded. As the magnitude of the signal increases, more bits are discarded, indicating coarser steps.
.
3 2~9~05 By the implementa~ion of Table 1, the translator accomplishes the compression illustrated in FIG. 2.
Characteristic 28 of FIG~ 2 is made up of 7 linear chords, 31 ~hrough 37, respectively, each identified by three chord bits. Although only the positive half of compression characteristic 28 is shown according to custom, it is understood that the negative half is symmetrical to that shown but lying in the third quadrant~ Corresponding third quadrant chords, therefore, are identified by the same chord bits but the opposite sign bit. Each segment is further divided by seven bits defining 27, i.e., 128 steps.
A positive sample of magnitude greater than 1/2 maximum, therefore, is encoded by chord 37 into an 11-bit word, the first 4 bits of which are 0110. The last line of Table 1 shows the translation of the l~-bit linear representation of this magnitude to the same ll-bit compressed code word.
Similarly, a negative sample of less than 1/64th maximum magnitude is encoded according to chord 31 (with an equivalent resolution of 14 bits~ the first four bits are 1000. This is implemented by the first line of Table 1.
Digital translation to other compression characteristics involves similar chord identification and copying of the step bits.
The ability to invert any bit is useful in certain kinds of code conversion. If the digital input to code converter 24, fo~ example, is in offset-binary form, the most negative analog value has been encoded as all zeros and the most positive value as all l's. Translating this to a sign-magnitude compressed code requires that the most signi~icant bit of all words be inverted to ~orm the conventional sign bit. In addition, step bits must be inverted for nega~ive signal samples to reflect negative increments from zero instead of positive increments. Chord bits, of course, are not inverted.
The parity check gives enough information to detect that one bit in a word is in error, but not enough information to determine which bit. The receiver, :
~z~ s ~herefore, cannot correct the error but merely rejects the whole word representing one analog sample. If a more significant bit has changed, therefore, and a less significant bit is in error, ignoring the entire word introduces a greater error than using it. It is thus useful to take parity over only the most significant bits, ignoring the lease significant.
The ability to select one bit at a time in response to an individual instruction word also allows bits to be assembled in the output word in any order.
A particularly useful format for 12-bit compressed words to be inserted into 8-bit time slots, as described in the Gaunt-Giammusso application, uses the following bit order: S F A B Z E X Y C G D P. In this notation, S is the sign bit; X, Y and Z are the chord bits;
A through G are the step bits, in order of decreasing significance; and P is a parity bit. The embodiment of FIG. l can assemble these words using the compression characteristic of FIG. 2 as follows:
The first instruction word instructs switch 45 to select the sign bit S by connecting its output 51 to either inp~t 0 or 1. It also commands inverter switch 47 to connect input 51 directly to output 61, bypassing inverter 63, and switch 49 to connect parity register 59 to output 61 so that the sign bit is included in the parity check.
In a similar manner, the second command word selects bit F.
For this bit, output 51 is connected to one of inputs 8 through 13, depending upon the values of inputs S through 6, according to Table 1. If the input sign bit is zero, indicating in offset-binary code a negative sample, the F
bit is inverted by switch 47 and the parity switch 49 is open. Chord bits ~, Y and Z are selected by the seventh, eighth and fifth instruction words, respectively, from inputs 0 and l. In a notable exception stored in the table select addresses 100000 and 011111, which represent the smallest magnitude signals in offset-binary code, the fifth instruction word selects chord bit Z by connecting selector .
~IL2~
output 51 to input 7. This results in the proper chord, according to Table 1, but saves half of the memory space.
It is possible because chords 31 and 32 are co-linear.
Assuming offset-binary input and sign-magnitude o~tput, Table 2 illustrates twelve instruction words that may be stored at table select address 100000 to implement compression chord 31. It can readily be seen that no bits are inverted, that parity is taken over bits S X Y Z A B C
P only, and that the Z bit is chosen from input 7.
Including the parity bit in the calculation serves to reset it for the next sample. To complete the picture, Table 3 illustrates the instruction words that could be stored at ROM address 010101 (in offset~binary code) implementing chord 36 in the third quadrant It can be seen that, according to Table 1, the least significant bit G of the output word is the tenth bit of the input word, that the seven step bits are inverted, and that, again, parity is taken over bits S X Y Z A B C P.
Since the make up of the output word is determined bit by bit by the instruction words stored in ROM 41, the embodiment of the invention shown in FIG. 1 is very versatile. An entirely different translation may be implemented by a simple change in the contents of the ROM.
For example, if the input words are in sign-magnitude form, the first instruction word stored a~ each input address selects the same bit 1, or zero as the most significant bit of the address. To change the output bit order, such _ OUTPUT
BITINPUT SELECT ROM SELECT INV P
z 7 0111 0 0 OUTPUT
BITINPUT SELECT ROM SELECT INV P
___ _ _ 25 S 1 ooOl 0 0 C 6 ~110 1 0 ., as in the German suggestion to CCITT, the order of the words in the table is changed. Different compression characteristics require different words to choose the chord bits.
Even more drastic changes are relatively easy to design with the use of this invention~ A different number of bits in the output word may require, for example, a different clock rate for reading out the ins~ruction words as well as a different number of words in each table.
Different length input words may require more memory - addresses, and more chords in the compression characteristic may require more bits in the instruction words, but these design changes are all well within the ordinary skill of those in the art.
FIG. 3 is a schematic diagram of an embodiment of the invention utilizing commercially available integrated circuits. In this circuit, four 4-bit registers 131, 132, 133, and 134, respectively, each have four input leads, D~
through D3, four output leads, Q0 through Q3, and a clock input. The fourteen parallel outputs S through 14 from the analog-to-digital converter are connected to the D0 through D3 inputs of the four registersO Input D0 of register 131 may be connected to ground; for example, with the sign bit S connected to input Dl, etc., and input D3 of register 134 may also be grounded. A 1 to 12 counter 143 has one input 144 connected to the 384k~z clock signal, four outputs, QA, Qs~ QC and QD, upon which appear the combinational logic that counts from 1 to 12, and a carry output 146. A
programmable read-only mPmory (PROM) 141 has ten address inputs A0 through A9 and six outputs Q0 through Q5.
Address inputs A0 through A3 are connected to counter 143 outputs QA through QD, respectively. Address inputs A9, A8 and A7 are connected to register 131 outputs Ql, Q2 and Q3, respectively, and address inputs A6, A5 and A4 are connected to register 132 outputs Q0, Ql and Q2, respectively. Counter carry output 14~ is connected to tha clock inputs of registers 131 through 134. Two 8 to 1 multiplexers 148 and 150, each have eight signal inputs O
through 7, and three instruction inputs, A, B and C, and two outputs, Y and Y. Signal input 1 of multiplexer 148 is connected to the +5 volt source. Input 0 is connected to 5 ground, and input 2 is connected to output Q3 of register 131. Inputs 3, 4, 5 and 6 of multiplexer 148 are connected to cutputs Q0 through Q3, respectively, of register 132, and input 7 is connected to output Q0 of register 133.
Inputs 0, 1 and 2 of multiplexer 150 are connected to outputs Ql, Q2, and Q3, respectively, of register 133, and inputs 3, 4, 5 of multiplexer 150 are connected to outputs Q0, Ql and Q2, respectively, of register 134. Instruction inputs A, B and C of both multiplexers 148 and 150 are connected to outputs Q0, Ql and Q2, respectively, of PROM
141. A dual 4 to 1 multiplexer 152 has signal inputs X0, Y0, Xl, Yl, X2, ~2, X3 and Y3, and instruction inputs A, B, STX and STY. Multiplexer 152 also has two outputs, ZY and ZX. Instruction inputs A and B of multiplexer 152 are connected to outputs Q4 and Q3, respectively, of PROM 141.
Input STY is connected to ground, and input STX is connected to output Q5 of PROM 141. Signal inputs X0 and Y0 are connected to output ~ of multiplexer 148 and signal input Xl and Yl are connected to output Y of multiplexer 148. Similarly, signal inputs X2 and Y2 and X3 and Y3 are connected to multiplexer 150 outputs Y and Y, respectively.
Finally, the code converter of FIG~ 3 includes a JK flip-flop 159 which performs as a pari~y register. Output ZX of multiplexer 152 is connected to the J and K inputs of flip-flop 159, the Q output is connected to input 7 of multiplexer 150, and the clock input is connected to the 385kHz clock siqnal.
In this specific implemen~ation, registers 131 through 134 may be 4-bit register~ in CMOS supplied, for example, by Motorola under the code MC14076. PROM 141 may be lKx8 capacity manufactured by Intel in NMOS under the code 2708. The particular words stored in the PROM, of course, will be determined by the logic signals required by lZQ~OS
the chosen integrated circuits to perform the functions described in connection with FIG. 1. Multiplexers 148 and 150 can be purchased in TTL logic from Texas Instruments, coded 74LS151, and multiplexer 152 may be Motorola's dual 4-1 multiplexer M~1~539 manufactured in CMOS. Counter 143 can utilize the commonly available chip 74LS161 in TTL
logic. While this chip is capable of counting to 16, it is easily wired by those skilled in the art to count to 12.
Since multiplexer 152 is implemented in CMOS
technology, its inputs that interface with NMOS (PROM 141) and TTL (multiplexers 148 and 150) are connected to the *5 volt source through 10K pull-up resistors.
This circuit operates as follows: The four input registers 131 through 134 operate as a latch to hold in parallel form the 14-bit input words from the linear A to converter. The first six bi~s, S through 6, form part of the address of P~OM 141, the outputs of counter 143 form the remainder of the address. The address bits, therefore, on A0 through A3, step through 12 changes at the 384kHZ
rate, while those on leads A4 through A9 remain constant.
The carry signal from counter 143 updates the 14-bit word as the counter resets. Twelve instruction words are/
therefore, read out of PROM 141 on leads Q0 through Q6 for each input 14-bit word.
The outputs Y and Y of the multiplexers 148 and 150 are connected to specific inputs 0 through 7 according to the logic on the outputs A, B, and C; that is, the first three bits of each instruction word stored in PROM 141. Y, of course, is the inverse of Y.
The chip chosen for multiplexer 152 operates in this manner: When inputs STX and STY are low, outputs ZX
and ZY are connected to the particular respective X and Y
inputs indicated by the logic on inputs A and B. With input STY grounded, therefore, output ZY is always connected to a selected Y input, Y0 through Y3. Output ZX
is connected to the selected X input only when a 0 appears on STX. Thus7 the first five bits of each instruction word 9~0S
chose a particular output bit and whether or not it is inverted. The sixth bit determines whether it is to be included in parity. The output Q of flip-flop 159 changes state with every "1" from output ZX o multiplexer 152. It forms the parity bit, which is the last bit of each 12-bit word ed out of output 161.
I have thus described a digital code translator that is inexpensive to build, easy to design, and very versatile. It will be obvious that many other embodiments can be designed without departing from the principle and scope of the invention.
Background of the ~nvention This invention is in the field of Digital Communications; it relates particularly to the translation of information from one digital form to another.
~s digital communications proliferate, and more and more information is communicated via digital facilities, the need to change codes and formats to fit the facility also increases. In one notable example, a system for inserting broadband audio program signals into T carrier time slots, which is described in the Gaunt-Giammusso application referred to abovel encodes samples of the program signal into 14-bit linear pulse code modulated (PCM) words in offset-binary form. The l~-bit words are then compressed into ll-bit PCM words in sign-magnitude form, the order of the bits is rearranged, and a parity bit is added to reflect parity over only certain, not all of the bits. In another example, the Federal Republic of Germany has proposed to CCITT in Contribution #109 to Study Group ~V, May, 1982, another format for compressed 12-bit words for sound program signals.
According to the German proposal, the 12-bit words are also made up of eleven PGM compressed code bits and one parity bit; the more significant bits are interleaved with the less significan~ bits, and parity is taken over only the five most significant bits.
While 8-bits compressed analog-to-digital encoders are common, ll-bit compressing encoders are not.
Furthermore, in some cases, such as the Gaunt-Giammusso arrangement, an unusual compression characteristic is required. Four~een or fifteen bit linear encoders, on the )9~1S
other hand, are easily purchased, and the resulting output words can be compressed by a digital code translator.
It is well-known in the art to translate from one code to another by means of a memory look-up table.
Each possible input code word forms an address of a read-only memory (ROM). Stored at the address is the translated output code word. In the case of a 14-bit input code, however, such a scheme requires 2 4 memory addresses.
With 12 bits per output word, the total memory requirement would be 214 x 12 - 196,608 bits of memory, a rather large amount~ Other available translation methods involve the use of logic circuitry. For very simple translations, available logic chips can be applied, but more complicated translators require considerable design effort and often custom logic integrated circuits. Unless contemplated production is very high volume, such expenditure may not be warranted.
An object of this invention is an inexpensive digital code translator that can convert linearly encoded PCM words to compressed PCM words.
Another object is a digital code translator that can perform compression, selective bit inversion, bit order rearrangement and selective parity inclusion.
~ third object is a code translator that can be assembled from readily available parts.
A fourth object is a code translator the output format of which can be entirely changed by a mere change of the contents of a memory.
~ummary of the Invention In accordance with an aspect of the invention there is provided a digital code translator for reversibly translating an input word into an output word comprising memory means having a multiplicity of addresses for storing at each said address a table of instruction words, address inputs and instruction word outputs; means connecting a ,,1~ .~1 ~2~9~7~S
- ~a -Eirst predetermined selection of bits of said input word to said address inputs; selector switch means having instruction inputs connected to receive said instruction words, a plurality of bit inputs and a switch output for connecting a selected one of said plurality of bit inputs to said switch output according to an instruction word;
means connecting a source of potential representative of a "1'l to a first one of said bit inputs; means connecting a source of potential representative of a zero to a second one of said bit inputs; and means connecting a second pre-determined selection of bits of said input word to others of said bit inputs, respectively; said selector switch means choosing the bits of said output word from said bit inputs in response to the respective instruction words of the table addressed by said first predetermined selection of input word bits.
In this digital code translator for reversibly translating an input word into an output word, a first predetermined selection of bits of the input word addresses a memory. Stored at each such address is a table of instruction words. A bit selection switch chooses each bit ~2OE~71~)S
of the output word from a choice of ~ æero or any one of a second predetermined selection of bits of the input word, according to a respective instruction word. Bit inverting means and parity switch means, both also responsive to the instruction words may be added to provide selective inversion of individual bits and selective inclusion in a parity check of individual bits.
Description of the Drawings FIG. 1 is a functional block diagram of an embodiment of the invention.
FIG. 2 is a compression characteristic useful in explaining the operation of the invention.
FIG. 3 is a schematic diagram of a particularly useful embodiment of the invention.
Detailed Description _ To explain the invention in detail, I refer now to FIG. 1, which is a functional block diagram of an embodiment of the inven~ion. This embodiment will be described in connection with the translation of 14-bit linear PCM words into 12-bit compressed PCM words at a 32kHz rate, although the invention is not, of course, limited to such use.
In FIG. 1 a read-only memory (ROM) 41 is addressed by the six most significant bits of the 14-bit linear input word- At each of the sixty-four possible addresses of memory 41 is stored a table of twelve instruction words. A 1 to 12 counter 43 addresses the twelve table entries in order, under control of a 334kHz clock. The table of twelve stored instruction words is therefore read out in order in response to each 14-bit input word, which may be representative of a single analog 5 ample.
Four bits of each output word of memory 41 address a bit selection switch 45; one bit addresses an inverter switch 47, and one bit addresses a parity switch 49. Bit selection switch 45 operates to selectively connect its output 51 to one of its inputs 0 through 15 under :
s control of each output instruction word from memory 41.
The inputs of switch 45 include the third through ourteenth bits of the linear input word, an always low (zero)input 0, an always high (1) input 1 and the output 15 of a parity register 59. Inverter switch 47 selectively connects bit selector output 51 to code translator output 61 directly, or alternatively through an inverter 63.
Parity switch 49 select:ively connects code translator output 61 to t~e input of a parity register 59. In response to each 14-bit encoded sample input, there~ore, ROM 41 utters twelve instruction words of six bits each.
Each instruction word determines one output bit of the 12-bit compressed output word, whether that bit is inverted, and whether it is included in the parity check.
The ability to select one bit at a time from a choice o~ 1, 0 or a particular input bit allows compression to any characteristic. Consider, ~or example, the translation o~ Table 1.
14--BITLINEAR ll--BIT COMPRESSED
SIGNMAGNITUDE SIGNCHORD STEP
_ SlABCDEFG--------- S 110 ABCDEFG
The ll-bit compressed column is made up of the sign bit S, three cord bits, and seven step bits A through G. Bits represented by dashes in the 14-bit linear column 35 are discarded. As the magnitude of the signal increases, more bits are discarded, indicating coarser steps.
.
3 2~9~05 By the implementa~ion of Table 1, the translator accomplishes the compression illustrated in FIG. 2.
Characteristic 28 of FIG~ 2 is made up of 7 linear chords, 31 ~hrough 37, respectively, each identified by three chord bits. Although only the positive half of compression characteristic 28 is shown according to custom, it is understood that the negative half is symmetrical to that shown but lying in the third quadrant~ Corresponding third quadrant chords, therefore, are identified by the same chord bits but the opposite sign bit. Each segment is further divided by seven bits defining 27, i.e., 128 steps.
A positive sample of magnitude greater than 1/2 maximum, therefore, is encoded by chord 37 into an 11-bit word, the first 4 bits of which are 0110. The last line of Table 1 shows the translation of the l~-bit linear representation of this magnitude to the same ll-bit compressed code word.
Similarly, a negative sample of less than 1/64th maximum magnitude is encoded according to chord 31 (with an equivalent resolution of 14 bits~ the first four bits are 1000. This is implemented by the first line of Table 1.
Digital translation to other compression characteristics involves similar chord identification and copying of the step bits.
The ability to invert any bit is useful in certain kinds of code conversion. If the digital input to code converter 24, fo~ example, is in offset-binary form, the most negative analog value has been encoded as all zeros and the most positive value as all l's. Translating this to a sign-magnitude compressed code requires that the most signi~icant bit of all words be inverted to ~orm the conventional sign bit. In addition, step bits must be inverted for nega~ive signal samples to reflect negative increments from zero instead of positive increments. Chord bits, of course, are not inverted.
The parity check gives enough information to detect that one bit in a word is in error, but not enough information to determine which bit. The receiver, :
~z~ s ~herefore, cannot correct the error but merely rejects the whole word representing one analog sample. If a more significant bit has changed, therefore, and a less significant bit is in error, ignoring the entire word introduces a greater error than using it. It is thus useful to take parity over only the most significant bits, ignoring the lease significant.
The ability to select one bit at a time in response to an individual instruction word also allows bits to be assembled in the output word in any order.
A particularly useful format for 12-bit compressed words to be inserted into 8-bit time slots, as described in the Gaunt-Giammusso application, uses the following bit order: S F A B Z E X Y C G D P. In this notation, S is the sign bit; X, Y and Z are the chord bits;
A through G are the step bits, in order of decreasing significance; and P is a parity bit. The embodiment of FIG. l can assemble these words using the compression characteristic of FIG. 2 as follows:
The first instruction word instructs switch 45 to select the sign bit S by connecting its output 51 to either inp~t 0 or 1. It also commands inverter switch 47 to connect input 51 directly to output 61, bypassing inverter 63, and switch 49 to connect parity register 59 to output 61 so that the sign bit is included in the parity check.
In a similar manner, the second command word selects bit F.
For this bit, output 51 is connected to one of inputs 8 through 13, depending upon the values of inputs S through 6, according to Table 1. If the input sign bit is zero, indicating in offset-binary code a negative sample, the F
bit is inverted by switch 47 and the parity switch 49 is open. Chord bits ~, Y and Z are selected by the seventh, eighth and fifth instruction words, respectively, from inputs 0 and l. In a notable exception stored in the table select addresses 100000 and 011111, which represent the smallest magnitude signals in offset-binary code, the fifth instruction word selects chord bit Z by connecting selector .
~IL2~
output 51 to input 7. This results in the proper chord, according to Table 1, but saves half of the memory space.
It is possible because chords 31 and 32 are co-linear.
Assuming offset-binary input and sign-magnitude o~tput, Table 2 illustrates twelve instruction words that may be stored at table select address 100000 to implement compression chord 31. It can readily be seen that no bits are inverted, that parity is taken over bits S X Y Z A B C
P only, and that the Z bit is chosen from input 7.
Including the parity bit in the calculation serves to reset it for the next sample. To complete the picture, Table 3 illustrates the instruction words that could be stored at ROM address 010101 (in offset~binary code) implementing chord 36 in the third quadrant It can be seen that, according to Table 1, the least significant bit G of the output word is the tenth bit of the input word, that the seven step bits are inverted, and that, again, parity is taken over bits S X Y Z A B C P.
Since the make up of the output word is determined bit by bit by the instruction words stored in ROM 41, the embodiment of the invention shown in FIG. 1 is very versatile. An entirely different translation may be implemented by a simple change in the contents of the ROM.
For example, if the input words are in sign-magnitude form, the first instruction word stored a~ each input address selects the same bit 1, or zero as the most significant bit of the address. To change the output bit order, such _ OUTPUT
BITINPUT SELECT ROM SELECT INV P
z 7 0111 0 0 OUTPUT
BITINPUT SELECT ROM SELECT INV P
___ _ _ 25 S 1 ooOl 0 0 C 6 ~110 1 0 ., as in the German suggestion to CCITT, the order of the words in the table is changed. Different compression characteristics require different words to choose the chord bits.
Even more drastic changes are relatively easy to design with the use of this invention~ A different number of bits in the output word may require, for example, a different clock rate for reading out the ins~ruction words as well as a different number of words in each table.
Different length input words may require more memory - addresses, and more chords in the compression characteristic may require more bits in the instruction words, but these design changes are all well within the ordinary skill of those in the art.
FIG. 3 is a schematic diagram of an embodiment of the invention utilizing commercially available integrated circuits. In this circuit, four 4-bit registers 131, 132, 133, and 134, respectively, each have four input leads, D~
through D3, four output leads, Q0 through Q3, and a clock input. The fourteen parallel outputs S through 14 from the analog-to-digital converter are connected to the D0 through D3 inputs of the four registersO Input D0 of register 131 may be connected to ground; for example, with the sign bit S connected to input Dl, etc., and input D3 of register 134 may also be grounded. A 1 to 12 counter 143 has one input 144 connected to the 384k~z clock signal, four outputs, QA, Qs~ QC and QD, upon which appear the combinational logic that counts from 1 to 12, and a carry output 146. A
programmable read-only mPmory (PROM) 141 has ten address inputs A0 through A9 and six outputs Q0 through Q5.
Address inputs A0 through A3 are connected to counter 143 outputs QA through QD, respectively. Address inputs A9, A8 and A7 are connected to register 131 outputs Ql, Q2 and Q3, respectively, and address inputs A6, A5 and A4 are connected to register 132 outputs Q0, Ql and Q2, respectively. Counter carry output 14~ is connected to tha clock inputs of registers 131 through 134. Two 8 to 1 multiplexers 148 and 150, each have eight signal inputs O
through 7, and three instruction inputs, A, B and C, and two outputs, Y and Y. Signal input 1 of multiplexer 148 is connected to the +5 volt source. Input 0 is connected to 5 ground, and input 2 is connected to output Q3 of register 131. Inputs 3, 4, 5 and 6 of multiplexer 148 are connected to cutputs Q0 through Q3, respectively, of register 132, and input 7 is connected to output Q0 of register 133.
Inputs 0, 1 and 2 of multiplexer 150 are connected to outputs Ql, Q2, and Q3, respectively, of register 133, and inputs 3, 4, 5 of multiplexer 150 are connected to outputs Q0, Ql and Q2, respectively, of register 134. Instruction inputs A, B and C of both multiplexers 148 and 150 are connected to outputs Q0, Ql and Q2, respectively, of PROM
141. A dual 4 to 1 multiplexer 152 has signal inputs X0, Y0, Xl, Yl, X2, ~2, X3 and Y3, and instruction inputs A, B, STX and STY. Multiplexer 152 also has two outputs, ZY and ZX. Instruction inputs A and B of multiplexer 152 are connected to outputs Q4 and Q3, respectively, of PROM 141.
Input STY is connected to ground, and input STX is connected to output Q5 of PROM 141. Signal inputs X0 and Y0 are connected to output ~ of multiplexer 148 and signal input Xl and Yl are connected to output Y of multiplexer 148. Similarly, signal inputs X2 and Y2 and X3 and Y3 are connected to multiplexer 150 outputs Y and Y, respectively.
Finally, the code converter of FIG~ 3 includes a JK flip-flop 159 which performs as a pari~y register. Output ZX of multiplexer 152 is connected to the J and K inputs of flip-flop 159, the Q output is connected to input 7 of multiplexer 150, and the clock input is connected to the 385kHz clock siqnal.
In this specific implemen~ation, registers 131 through 134 may be 4-bit register~ in CMOS supplied, for example, by Motorola under the code MC14076. PROM 141 may be lKx8 capacity manufactured by Intel in NMOS under the code 2708. The particular words stored in the PROM, of course, will be determined by the logic signals required by lZQ~OS
the chosen integrated circuits to perform the functions described in connection with FIG. 1. Multiplexers 148 and 150 can be purchased in TTL logic from Texas Instruments, coded 74LS151, and multiplexer 152 may be Motorola's dual 4-1 multiplexer M~1~539 manufactured in CMOS. Counter 143 can utilize the commonly available chip 74LS161 in TTL
logic. While this chip is capable of counting to 16, it is easily wired by those skilled in the art to count to 12.
Since multiplexer 152 is implemented in CMOS
technology, its inputs that interface with NMOS (PROM 141) and TTL (multiplexers 148 and 150) are connected to the *5 volt source through 10K pull-up resistors.
This circuit operates as follows: The four input registers 131 through 134 operate as a latch to hold in parallel form the 14-bit input words from the linear A to converter. The first six bi~s, S through 6, form part of the address of P~OM 141, the outputs of counter 143 form the remainder of the address. The address bits, therefore, on A0 through A3, step through 12 changes at the 384kHZ
rate, while those on leads A4 through A9 remain constant.
The carry signal from counter 143 updates the 14-bit word as the counter resets. Twelve instruction words are/
therefore, read out of PROM 141 on leads Q0 through Q6 for each input 14-bit word.
The outputs Y and Y of the multiplexers 148 and 150 are connected to specific inputs 0 through 7 according to the logic on the outputs A, B, and C; that is, the first three bits of each instruction word stored in PROM 141. Y, of course, is the inverse of Y.
The chip chosen for multiplexer 152 operates in this manner: When inputs STX and STY are low, outputs ZX
and ZY are connected to the particular respective X and Y
inputs indicated by the logic on inputs A and B. With input STY grounded, therefore, output ZY is always connected to a selected Y input, Y0 through Y3. Output ZX
is connected to the selected X input only when a 0 appears on STX. Thus7 the first five bits of each instruction word 9~0S
chose a particular output bit and whether or not it is inverted. The sixth bit determines whether it is to be included in parity. The output Q of flip-flop 159 changes state with every "1" from output ZX o multiplexer 152. It forms the parity bit, which is the last bit of each 12-bit word ed out of output 161.
I have thus described a digital code translator that is inexpensive to build, easy to design, and very versatile. It will be obvious that many other embodiments can be designed without departing from the principle and scope of the invention.
Claims (7)
1. A digital code translator for reversibly translating an input word into an output word comprising:
memory means having a multiplicity of addresses for storing at each said address a table of instruction words, address inputs and instruction word outputs;
means connecting a first predetermined selection of bits of said input word to said address inputs;
selector switch means having instruction inputs connected to receive said instruction words, a plurality of bit inputs and a switch output for connecting a selected one of said plurality of bit inputs to said switch output according to an instruction word;
means connecting a source of potential representative of a "1" to a first one of said bit inputs;
means connecting a source of potential representative of a zero to a second one of said bit inputs; and means connecting a second predetermined selection of bits of said input word to others of said bit inputs, respectively;
said selector switch means choosing the bits of said output word from said bit inputs in response to the respective instruction words of the table addressed by said first predetermined selection of input word bits.
memory means having a multiplicity of addresses for storing at each said address a table of instruction words, address inputs and instruction word outputs;
means connecting a first predetermined selection of bits of said input word to said address inputs;
selector switch means having instruction inputs connected to receive said instruction words, a plurality of bit inputs and a switch output for connecting a selected one of said plurality of bit inputs to said switch output according to an instruction word;
means connecting a source of potential representative of a "1" to a first one of said bit inputs;
means connecting a source of potential representative of a zero to a second one of said bit inputs; and means connecting a second predetermined selection of bits of said input word to others of said bit inputs, respectively;
said selector switch means choosing the bits of said output word from said bit inputs in response to the respective instruction words of the table addressed by said first predetermined selection of input word bits.
2. A digital code translator, as in claim 1, wherein said first predetermined selection of bits of said input word comprises the six most significant bits.
3. A digital code translator, as in claim 2, wherein said second predetermined selection of bits of said input word comprises the six least significant bits.
4. A digital code translator, as in claim 1, additionally comprising selective bit inversion means for inverting according to said instruction words designated ones of said chosen bits.
5. A digital code translator, as in claim 1 or 4, additionally comprising parity register means having an output connected to a third one of said bit inputs and an input; and parity switch means for connecting the output of said selector switch means to said parity register means according to said instruction words to include designated bits of said output word in a parity check.
6. A digital code translator, as in claim 1, wherein said memory means comprises a programmable read-only memory.
7. A digital code translator, as in claim 1, further comprising digital counting means for cyclically counting the number of bits in said output word, having a plurality of count outputs, connected to individually address the words of said tables of stored instruction words and a clock input for connection to a source of clock pulses; said counting means advancing one word in a table in response to each clock pulse.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US413,470 | 1982-08-31 | ||
| US06/413,470 US4544916A (en) | 1982-08-31 | 1982-08-31 | Digital code translator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1209705A true CA1209705A (en) | 1986-08-12 |
Family
ID=23637352
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000431626A Expired CA1209705A (en) | 1982-08-31 | 1983-06-30 | Digital code translator |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4544916A (en) |
| CA (1) | CA1209705A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4800574A (en) * | 1983-05-10 | 1989-01-24 | Ricoh Company, Ltd. | Digital modulator/demodulator including non-linear analog-to-digital converter and circuitry compensating for the non-linearity of the converter |
| US5055717A (en) * | 1986-05-30 | 1991-10-08 | Texas Instruments Incorporated | Data selector circuit and method of selecting format of data output from plural registers |
| GB8801014D0 (en) * | 1988-01-18 | 1988-02-17 | British Telecomm | Noise reduction |
| CA2019821C (en) * | 1988-12-28 | 1995-04-25 | Shoichi Takahashi | Signal conversion circuit |
| ES2113404T3 (en) * | 1991-09-06 | 1998-05-01 | Koninkl Philips Electronics Nv | RADIO RECEIVER WITH ANALOGUE DYNAMIC COMPRESSION AND DIGITAL EXPANSION. |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2131635A1 (en) * | 1970-09-15 | 1972-03-16 | It Telecommunicazioni Siemens | Digital compression circuit |
| CH545560A (en) * | 1971-05-06 | 1974-01-31 | ||
| US3945002A (en) * | 1974-10-25 | 1976-03-16 | Bell Telephone Laboratories, Incorporated | Block digital processor for use with nonuniformly encoded digital words |
| US4040049A (en) * | 1975-10-09 | 1977-08-02 | Bell Telephone Laboratories, Incorporated | Tandem block digital processor for use with nonuniformly encoded digital data |
| US4037226A (en) * | 1976-01-07 | 1977-07-19 | Ncr Corporation | Pulse code modulation compressor |
| JPS542050A (en) * | 1977-06-07 | 1979-01-09 | Nec Corp | Block coding and decoding system |
-
1982
- 1982-08-31 US US06/413,470 patent/US4544916A/en not_active Expired - Fee Related
-
1983
- 1983-06-30 CA CA000431626A patent/CA1209705A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US4544916A (en) | 1985-10-01 |
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