GB2149162A - Fixed point to floating point conversion - Google Patents

Abstract

Comprises a register (SR) for serial entry of the fixed point number, a counter (X1) for counting, during such entry, the number of leading insignificant digits, to provide exponent digits for output, and selector means (SEL2) controlled by the state of the counter (X1) to select from the digits entered into the register the mantissa digits for output. <IMAGE>

Description

SPECIFICATION Fixed point to floating point conversion It is common practice to convert analogue signals into a digital form which is transmitted as a series of discrete pulses. The pulses are usually grouped into "words" and each "word" represents a number. For transmission it is convenient to use a code which makes available a relatively wide range of values with approximately constant relative accuracy, e.g. a range of + 4000 to - 4000 with relative accuracy 1 part in 1 6 to 32. Floating point code, wherein each word consists of an index, a mantissa and, if necessary, a sign bit meets these requirements.

Floating-point codes have the advantage of keeping the signal-to-quantisation-noise ratio relatively constant over a large signal level range. One particularly useful form of floating-point code is the A-law code (see CCITT 5378 Recommendation G711, White Book).

On receipt, it is often desired to process floating-point signals by performing calculations with the numbers thus represented e.g. numerical filtering or numerical demodulation. However floating-point code is not convenient for calculation and it is desirable to convert it into a fixed point code commonly used in computers.

Our co-pending UK patent application No 8420076 describes an apparatus for converting a floating-point input into a digit-serial fixed point output. The present invention is concerned with conversion from fixed-point to floating-point.

According to the present invention there is provided apparatus for converting a number represented digit-serially in fixed-point code into a floating-point code, comprising a register for serial entry of the fixed point number, a counter for counting, during such entry, the number of leading insignificant digits, to provide exponent digits for output, and selector means controlled by the state of the counter to select from the digits entered into the register the mantissa digits for output.

Although in principle applicable to numbers to any base, the most common application is likely to be for binary numbers. In this instance the counter will count the number of leading zeros, or for signed numbers, the number of leading bits which are the same as the sign bit.

Conveniently (assuming serial input least significant bit first, sign bit last), this can be achieved by means of a counter clocked at the data input rate with means for resetting the counter whenever the contents of the first two stages of the input register are different.

If the output is also to be in serial form, a 1-bit selector means may be used, arranged to select the mantissa digits sequentially, for example by incrementing the counter.

Some embodiments of the present invention will now be described with reference to the accompanying drawings, in which: Figure 1 shows in outline a fixed point to floating point converter; Figure 2 is a block diagram of a 2's complement to A-law converter; and Figure 3 is a timing diagram for the converter of Fig. 2.

Referring to Fig. 1, it is assumed that a serial input 10-bit fixed point word is to be converted to a serial output, floating point word.

First, the serial input data, least significant bit first, supplied to a serial input SI is clocked into ten-bit shift register SR by clock pulses +,Nwhen an input enable signal ENX is high: when ENX goes low, the clock is inhibited and the input word is staticised in the shift register SR. During this period, a four-bit counter Z1 is incremented, but is reset (to an appropriate value) whenever the most significant bit position of the shift register contains a binary 1. Thus the counter counts the number of leading zeroes and, at the end of the period, its complemented output ABCD indicates the position occupied by the leading non zero bit of the input word; and thus forms the exponent part of the required output floating point word.

In the second phase of operation of the converter, (signalled by an enable signal ENW) a second three-bit counter X2 is clocked by fouT(which may, but need not, be the same as +iN) to provide a sequence of addresses for an 8-line to 1-line multiplexer SEL2. The first four inputs 0-3 of the multiplexer are connected to receive the four bits of the exponent, from the counter X1, and are thus supplied in sequence to serial output SO. Inputs 4 to 7 are paralleled and connected to the output of a 1 6-line to 1-line multiplexer SEL1, which serves to select the mantissa bits in sequence from the shift register output, its addresses being supplied by the counter X1 which is now clocked by fOuTgated with a (the msb of counter X2) and ENW.The initial state of the counter determines the phasing of the selection sequence so that the appropriate bits are selected.

Fig. 2 now shows in rather more detail a practical version of a counter for conversion of a signed 2's complement fixed-point word into A-law code. Fig. 3 is a timing chart.

2's complement is a code comprising a bit defining the sign of a number accompanied by other bits representing the magnitude. If the sign bit is 0 the number is positive and if it is 1 then the number is negative. The magnitude bits have fixed weightings according to their positions relative to the sign bit. The bit furthest from the sign bit is known as the least significant bit (Isb), and has the smallest magnitude weighting. The next bit has twice this weighting, the next four times, the next eight, and so on. Thus a numbering scheme can be built up with the property that the quantum steps between adjacent numbers are equal.

Therefore the code is said to be linear. However, because of this property, the quantisation noise will be fixed at a root mean square value of 1 /2V3 Isb. This means that the signal-toquantisation-noise ratio will increase proportionally as the signal level decreases. Table 1 shows a decimal-to-2's-complement equivalence chart for a 4-bit 2's complement code. The 2's complement sign bit has a weighting of - 1, and the n th bit after the sign bit has a weighting of 2-".

Table 1 Decimal 2's Complement sign magnitude +.875 0 111 +.75 0 110 +.625 0 101 +.5 0 100 +.375 0 011 +.25 0 010 +.125 0 001 0 0 000 -.125 1 111 -.25 1 110 -.375 1 101 -.5 1 100 -.625 1 011 -.75 1 010 -.875 1 001 -1 1 000 The A-law code comprises three parts: a sign bit, exponent bits, and linear bits known as the mantissa. In A-law, positive numbers have a sign bit of 1 and negative numbers 0. The exponent part is adjacent to the sign bit, and is usually 3 bits specifying a multiplying factor to be applied to the mantissa bits. The mantissa bits are linearly coded. The important feature to note about this numbering scheme is that the quantisation noise level decreases as the signal level decreases. For most transmission purposes this is a useful property because the signal-toquantisation-noise ratio will remain relatively constant over a large dynamic range. The equivalence between the A-law and 2's complement codes are shown in table 2.

TABLE 2 A-law word 2's complement word S ABC WXYZ 1 111 WXYZ OlWXYZ1000000001 1 110 WXYZ OOliXYZ100000001 1 101 WXYZ oOO1WXYZiOOOOOO1 1 100 WXYZ OOOOlWXYZ1000001 1 011 WXYZ OOOOOlWXYZ100001 1 010 WXYZ 0000001WXYZ10001 1 001 WXYZ OOOOOOOlWXYZ1001 1 000 WXYZ OOOOOOOOWXYZ1001 0 000-WXYZ 1III1IIIWXYZO111 0 001 WXYZ 11111110WXYZ0111 0 010 WXYZ 1111110WXYZ01111 0 011 WXYZ 11111OWXYZO11111 0 100 WXYZ 11110Z0111111 0 101 WXYZ 1IIOWXYZO1111111 0 110 WXYZ 11OWXYtOllllllll 0 111 WXYZ 1OWXYZOI11111111 This table is a truth chart for the required 2's complement to A-law converter. The important point to note is the way the bits following the 2's complement sign bit form a pattern through the table. It can be seen that the smaller the number the more the sign bit appears to be repeated. In fact the number of consecutive bits that are the same as the sign bit is given by the formula 111 (binary) minus the A-law exponent value.

During the first phase of operation the 2's complement number is clocked into a 12-bit shift register SR. The outputs of the first and second stages of the shift register are compared using an exclusive OR gate EX1. If they are different this will produce a pulse which is inverted in an inverter Ii and used to clear the counter X1. Thus the counter can count only during the times when the input bits are not alternating. During this mode of operation the counter clock (enabled by signal ENX via inverter 12 and OR gate 01) is the same as the input shift register clock enabled by X in an AND gate Al.

At the moment the sign bit of the 2's complement number is clocked into the first stage of the shift register both these clocks are inhibited by the control signal ENX. ENX also inhibits the action of the counter reset connection via an OR gate 02. Thus, the states of the parallel outputs of the shift register SR represent the bits of the input word, and the A, B and C outputs of the counter represent the number of consecutive bits adjacent to the sign bit which were the same as the sign bit. This is therefore a count of the number of repeated sign bits in the input word.

It should be noted that the count is limited to the range 0000 to 0110 (six) during this phase of working. This is because the A-law mantissa bits are treated slightly differently in the case when the exponent is 000. An AND gate A2 and inverter 13 generate a load pulse when the count reaches 011 0, and the reset condition of 0110 ensures that this count is held for subsequent clock periods. A bistable flip-flop FF1 is used to store the fact that the load has operated. If it has then C is changed from a logical '0' to a logical '1' by the action of an OR gate 03. Thus C is the same as C' except when the number input is equivalent to an A-law number with an exponent value of 000.

Observing the states of various nodes of the circuit at the time when the clocks are inhibited it can be seen that the sign bit S is the inverse of the A-law sign bit, A, B and C are the inverses of the A-law exponent bits, and the mantissa bits (or the inverse of the mantissa bits) are captured in the shift register SR. The absolute positions of these mantissa bits will depend on the particular number. In order to assemble all the bits in the correct format for the serial A-law pcm output it is necessary to operate the circuit in its second mode. During this phase of operation the conditions on the various inputs of the (inverting) 8:1 selector SEL1, are transferred to the output SO under the control of an address assy generated in the counter X2.

The moment at which the first bit of the A-law word is selected is governed by the low-to-high transition of the control waveform ENW. ENW is 8 bits wide and it windows the time slots in which the A-law data bits are output. It should however be noted that ENW is not permitted to go high during the period of the first phase of the circuit operation (i.e. when the input word is being clocked into the shift registers). If it is high during this time then the output data will be invalid.It should also be noted that the low-to-high transition should be shifted by an integer number of 8-bits relative to the sync load input to the counter X2 otherwise the afly address will be incorrectly phased. (The counter XZ is assumed to count continuously, the sync load input L (corresponding to state 0) serving for initial synchronisation by ensuring that the counter assumes state 0001 on the clock pulse following the sync load pulse.) Thus when ENW goes high the afi and y controls should all be low and consequently the A-law sign bit S will be seen on the output (of SEL1). The next bit out will be the most significant bit of the A-law exponent A, followed by B, then C.

The next four bits need to be the WXYZ bits of the A-law mantissa, and these are found be examining the states of the inputs to the inverting 16:1 selector SEL2. The location at which the W bit is found is given by addressing the selector with D, , B and C, which are the states of the outputs of counter X1. This is the start address for finding all the mantissa bits WXYZ. The other addresses are generated by stepping the counter further through its cycle. In order to do this the inhibit to the clock for the counter has to be made inoperable when both a and ENW are high. An AND gate A3 generates the waveform to disable the inhibit via an OR gate 04. The counter X1 can therefore continue with its counting during this phase of the circuit operation, and its count range will be an unbounded modulo-16. Thus the address bits D, A, B, C' for the 16:1 selector SEL2 will change in a cyclic manner. This will result in the selection of the X bit of the A-law code, followed by the Y bit, followed by the Z bit. Because the W, X, Y and Z bits of the A-law code are equivalent to the W, X, Y and Z bits in the negative 2's complement code these bits need to be inverted when S is a logical '1'. An exclusive OR gate EX2 performs this operation. The bits decoded in this way are presented as inputs to the data selector SEL1 and are transferred to the output of the device to complete the A-law word.

In fact, normally, the A-law code has alternate bits inverted (ADI). This feature can be easily provided in the arrangement shown by interposing inverters in alternate input lines of the input to the selector SEL1 of Fig. 2.

Claims (5)

1. Apparatus for converting a number represented digit-serially in fixed-point code into a floating-point code, comprising a register for serial entry of the fixed point number, a counter for counting, during such entry, the number of leading insignificant digits, to provide exponent digits for output, and selector means controlled by the state of the counter to select from the digits entered into the register the mantissa digits for output.

2. Apparatus according to claim 1, for converting binary numbers, with means for incrementing the counter each time a bit is entered into the register, and means for resetting the counter whenever the contents of the first two stages of the register are zero.

3. Apparatus according to claim 2 for use with signed numbers, including means for inversion of the output in response to the value of a sign bit entered into the register.

4. Apparatus according to claim 2 or 3 including, for serial output, means arranged to serially output the contents of the counter, representing the exponent bits, and then increment the counter for serial output of the mantissa bits.

5. Apparatus for converting a number represented digit-serially in fixed-point code into a floating-point code substantially as herein described with reference to Fig. 1 or Fig. 2 of the accompanying drawings.