CA1207035A - Circuit de mise en forme d'impulsions d'horloge - Google Patents
Circuit de mise en forme d'impulsions d'horlogeInfo
- Publication number
- CA1207035A CA1207035A CA442221A CA442221A CA1207035A CA 1207035 A CA1207035 A CA 1207035A CA 442221 A CA442221 A CA 442221A CA 442221 A CA442221 A CA 442221A CA 1207035 A CA1207035 A CA 1207035A
- Authority
- CA
- Canada
- Prior art keywords
- clock
- circuit
- input
- output
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
- H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00195—Layout of the delay element using FET's
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Pulse Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA442221A CA1207035A (fr) | 1982-12-22 | 1983-11-29 | Circuit de mise en forme d'impulsions d'horloge |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/452,157 US4479216A (en) | 1982-12-22 | 1982-12-22 | Skew-free clock circuit for integrated circuit chip |
US452,157 | 1982-12-22 | ||
CA442221A CA1207035A (fr) | 1982-12-22 | 1983-11-29 | Circuit de mise en forme d'impulsions d'horloge |
Publications (1)
Publication Number | Publication Date |
---|---|
CA1207035A true CA1207035A (fr) | 1986-07-02 |
Family
ID=63077615
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA442221A Expired CA1207035A (fr) | 1982-12-22 | 1983-11-29 | Circuit de mise en forme d'impulsions d'horloge |
Country Status (1)
Country | Link |
---|---|
CA (1) | CA1207035A (fr) |
-
1983
- 1983-11-29 CA CA442221A patent/CA1207035A/fr not_active Expired
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MKEX | Expiry |