CA1192312A - Single-supply ic digital-to-analog converter for use with microprocessors - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

A single-chip 8-bit DAC with bipolar current sources, an output buffer amplifier for developing an output voltage, ¦
a regulated reference for producing a calibrated output, and operated by a single-voltage supply, e.g. +5 volts. The buffer amplifier includes means providing for driving the output voltage virtually to ground level when the DAC output is zero. The current sources comprise a single-transistor cell driven by an I2L flip-flop circuit, and the reference supply is merged with the reference transistor circuit regulating the DAC current levels, both aiding in reducing required chip area. A highly efficient bias network is utilized to supply the high-level bias currents required.

Description

935.045 Z3~z 1.

¦ BACKGROUND OF THE I~ENTION

¦ Field of the Invention This invention relates to digital-to-analog conver-I ters. More particularly, this invention relates to monolithif S ,I converters that are especially adapted for operation with microprocessors, such a~ may be used in analog control systems.

D ~

li A wide variety of digital-to-`analog converters ~ I~ have heen availa~l now for some time. Such converters ll frequently employ current sources which are selectively-activated in accordancç with a digital input signal. U~ S.
I Reissue Patent No~ RE. 28j633 (Pastoriza) shows one highly ' I !l successful converter design ~f that t~pe. ~ more recent l¦ design is shown in U. S. Patent ~o. 3,9~1~326 (Craven).
lS ¦~ Digital-to-analog ~onverters also are e~pl~yed in successive-.
~! approximation analog~to-digital cor~verters such as disclosed ~, in Canadian Patent No. 1,159,95~6 (Brokaw ek al~; the latter converter particularly is advantageous in that it incorporates inverted mode transistor circui.try (sometimes . referred to as I L, for "integrated injection logic"), , togeth~r with bipolar transistor circuitry, on the sam~
. monolithic chip.

-2-935.045 ~231Z

There have been pro~sa1~ for converters esp-cia11J
¦suited for use with microprocessors, as for example described ( lin the paper by SchoefE entitled "A Microprocessor Compatible ,Hiyh-Speed 8-Bit DAC", in the February, lg78, ISSCC Digest of ~Technical Papers, at p~ges 13Z-133.

¦ Although many proposals have been put forward, none has provided a satisfactory converter capable of xequire~
pexform~nce, and yet suitably simple in design to be manufac-),tured economically. Particularly, prior art designs have llnot provided a monolithic converter including a reference source and an amplifier to produce voltage output, all 'operable by a single supply, e~g. +5 volt. It is a principal object of this invention to provide solutions to the problems liencountered in achieving that goal.

15 ll SUMMA~Y OF T~E I~VE~TION
,I T~ nr~ wi t-l~ nnf~ ;mr~nr~nt~ ;~cnf~ nf the invention, there is disclosed herein a digital-to-analog converter in~orporating a superior ~uffer amplifier capa~le , o producing an outpuk voltage between zero and some nominal ¦I value while operating from a single supplyO In accordance with another aspect of the invention, there is provided a simplified one-transistor current-source cell capable of i operation directly with I2L switchi.ng logic, to permit a 2~ 935 045 .:ignificant reduction in part coun f the chip. I st~ll another aspect of this invention, a converter is provided ( havlng a novel simplified reference supply for regulating the gain of the current sources to stabilize the output-cur- I
rent of the converter. In yet another aspect o~ the invention, a converter bias current network is provided having high efficiency, znd thus reducing the requixed power while still achi.eving excellent performanceO

.' 1, ~ Other objects, aspects and advantages of the ¦invention will be pointed out in, or apparent from, the fvllowing detailed description of a preferred embodiment of the inveniion, considered together with the accompanying . ! drawings .
I I
i BRIEF DESCRIPTIO~ OF THE DRAWINGS

j FIGURE 1 is a block diagram illustrating the llpxeferred embodiment;
l ll FIGURE 2A and 2B together present a detailed ~circuit diagram of the preferred embodiment, i FIGURE 3 is a diagrammatic pxesentation of the !'reference supply circuitry or the current sources;
1.
.
E~IG~RE 4 shows aspects of the buffer amplifier;

~} ~

935.045 ~g231Z ~ '-FIGURES 5 and 6 illustrate the functioning of the .- bias current network; and FIGURES 7A and 78 present a perspective section view¦
of the structure of a drive transistor used in the buffer amplifier, and a schematic diagram of the elements of that ¦ transistor. I
.
DESCRIPTIO~ OF A PREFERRED EMBODIMæNT
Referring now to Figure 1, the microprocessor logic control signals CS and CE are directed to a gate 20 which ¦con-trols the I2L data latches generally indicated at 22. The 11 latches are Lransparent to data on the data bus 24 when both ¦ICE and CS are àt logic ~0~'.. The input data is stored in the latches when either CE or CS goes to logic "l".
. As shown in Figure 2, the data latches 22 ~I comprise eight I L flip-^flops G20/G30 - G27/G37 (although j for simplicity only the first and eighth are shown).
: ~ The out.put of the control gate 20, which swings around l 1.2 volts, is applied to the bases of eig~t transistors : I~Ql0-Q17 which act together with respective data input : ¦I transistors Q~-Q7 to control the initially disabled I~L
1I yate pairs G~/GlO - G7/Gl7. Dependîng on the status o the ! input data, one or the other of the two gate lines 26, 28, letc~, is pulled down to control the associated eight set/reset ~' l i 23~
,~35.045 lip-f].ops G20/G30 - G27/G37. If the ].eft-hand fli~ fl~p ~ section (G20-G27) is turned on, current will flow through the ( associated collector 30, etc., connected to the emitter of a corresponding PNP current source transistor Q20-Q27. This current is drawn from the ~ransistor emitter circuit, inter-rupting flow ihrough the transistor to an R/2~ ladder network !
generally indicated at 32, and which functions in the usual ~way to provide an analog output current corresponding to the ~binary input on the data bus 24.

~eferring now in more detail to the current source transistors Q20-Q27, the voltage between the common base line .. . 34 and the emitter-resistor rail 36 is controlled by a regulat-I ing reference source illustrated in simplified format in Figure 3. This arrangement includes a band-gap cell of the typa disclosed in U. S. Patent No. 3,8B~,863 (Brokaw), having two transistors Q51 and Q52 with associated resistors R31 and I
R32 and operated at different current densities. As explained¦
in that patent, the collector currents of the two transistors ¦
are sensed by an error amplifier 38. In the present arrange-ment, however, the amplifier output is directed to the Pmitter resistor rail 36 to which is connectéd a reference resistor R8 and a reference transistor Q50. These elements, together with another resistor R30, provide fee~back to the bases of tran-llsistors Q51 and Q52, and drive the rail 36 to a volta~e j,producing through R8 a feedbacX current which develops a voltage across ~30 equal to the band-gap voltage (VGo~ e.g.

-v -~ 9~5.045 essentially 1.205V. for silicon. This sets the current through Q50 and all 8 DAC P~IPs at a temperature independent lOO~A.

In the particular embodiment disclosed in Figure I -2, the differential error amplifier comprises QS3 and Q54, ¦ and a common emitter output amplifier Q58. The pow~r supply rejection of the loop is enhanced by common-mode feedback I¦ through QS6, which fixes the collector base voltage of Q~l ¦l and Q52, and balances the error amplifier. A shunt regulator~
I generally indicated at 39 and of known design, biases the l¦common base rail 34 at 1.2V.
. 1l .
; Referring now to Figure 4 together with Figure 2, the output o~ tne R/2R ladder 30 is directed along a line 40 1~ to the output buffer amplifi~r generally indicated at 42 ¦ and inclu~ing special features to accommodate the unipolar, ground referenced output swing of the R/2~ ladder. This amplifier comprises a ver~tical P~P di~ferential input pair Q43/Q44 with Q44 serving to provide a feedback signal corre-llsponding to the amplifier output voltage. The ladder signal : 20 11 is coupled by Q43 up through a unique ~P~ current mirror cir--l '¦cuit with iransistors Q34-Q39. The signal passes from Q36 and ~34 to Q37 which drives Q35/Q39 controlling Q40, a special ~,ldriver for ~he output emitter follower Q41 producing an out-put voltage at the VoUT(E'~RCE) pin. This pin ~s connected ~ 312 935.045 '1 t~ the VOuT ~SE~SE) pin and ~; the Range Select pi~ for a 2.56 volt range. (Alternatively, the Range Select pin can be connected to analog common, to provide a 10 volt range.) The output voltage is fed back to the base of Q44, which functions to halance the signal from the R/2R ladder.
. I .

One of the principal problems in achieving a ground referenced output voltage swing in a single supply converter results from saturation in the output stage when the DAC signal level becomes very small, i.e. approaching zero, thus limiting the ability of the output stage to drive the output voltage down close to zero. In a nGrmal amplifier, the conse~uent unbalance in the feedback causes the amplifier to tend to overdrive, thereby further intensifying the satura tion problem. This problem has been solved by a special cir-cuit arrangement now to be described. I

Referring al50 to Fiyure 7, the output driver tran-¦
sistor Q40 includes the usual eptiaxial layer, a collector C
(n~), and a base ~p) having an emitter F (n+). In addition, the base is formed with a second n~ electrode laheled C3, and shown as a second emitter in the circuit diagrams of Figures I
2 and 4 This element is connected externally to the base of' Q35. Normally, this element is not negative with respect to the base of Q40, so that no current will flow. However, as ~23~2 ~-- .

the amplif -r output voltage gets close to zero, th~s ~lement begins to serve as an inverted-mode collector (thus being labeled C3), and collects current so as to limit the base drive at Q35. This prevents the saturation of Q40, and also ¦
controls the equilibrium points of the other transistors associated with Q35. In effect, the additional collector senses the onset of saturation in Q40, and operates through an interior feed~ack loop including Q35/Q39 to prevent further significant saturation while still developing the correct , output signal. The result is that overload of the entire amplifiex is prevented, and the output voltage can be driven down close to zero, even though only a single supply voltage ~is employed.

Tn ~rnr~nC~ with a further as~ect of the inven-tion, the ou~put signal from Q40 prefera~ly is developed from a separate collector C2 formed in a deep n* plug extending down to the buried layer. This Kelvin connection avoids ~e effects of the voltage drop across the internal resistance hetween the conventional collector Cl and the buried layer.
.

jl R~ferring now to Figures 5 and 6 as well as to the upper lef, hand corner o~ Figure 2~, the converter of this invention includes a unique highly efficient biasing network utilizing lateral P~Ps developing the relatively high level currents reguired by the I L circuitry, the ECL control gate 2~ 1 20 and the reference supply for the current sources Q20-Q27.

_9~ i 23~ 93'; ~ 04~

Th~ sinale bias su~lv transistor Q75 is formed with split collectors proportioned for the respective required bias currents, and is deliberately operated in high level injec-tion. Under these conditions, ~ and Ic (total) form a constant product, i.e. ~ ICT = K. One collector 60 is connected to a current m~rror 62 also connected to the base of Q75. In more detail, as shown in Figure 6, collector 60 is connected . -to the base of a feedback transistor Q73 the collector of which is connected to the base of Q75. The collector 60 and the emitter of Q75 are connected to a pair of transistors Q76 and Q77 having emitters with an area ratio of 1.25:1, to establish that ratio cf currents therethrough~ The combined current is delivered to the I L main injector rall. ~This ail is the more positive of the two supply connections to the I2L clrcuitry, and lS connected to all of the I L elements indicated schematically as half~arrow emitters; the more negative terminal is the buried layer.

With the current mirror feedback shown, the base ¦current IB for Q75 will be oC ICT M, w~ere CX~ is the proportion of total collector current in collector 60, and M
~ is khe current mirror ratio. Since ~ is defined as ICT/IB~

I ;t can be developed that c~M = ICT/K, where K is the constant previously described, resulting from the initial aevice design characteristics Thus~ by properly ad~sting C~: and M with ~5 ~reference to the requirements of -the different circuit sections .4 f ~35.0~5 fo~ bias urrents, i.e. by fixing the relative are~ :
emitters of Q76 and Q77 and the ~split collectors of Q75, st~ble bias currents can be ob-tained for the individual circuit sections. Moreover, as will be apparent from S Figure S, the circuit arrangement makes use of all o the current for biasing purposes, without loss. The circuit in effect recovers both the base current and the collector current of the feedback collector to be used as a current source ~or biasing purposes. Figure 6 has been includea alongside of Figure 5 to permit rèady comparison of the block diagram presentation with the actual circuitry.
`

Although a preferred embodiment of this invention has been described hereinabove in detail, i.t is desired to lemphasize ~hat this has been for the purpose of illustrating ¦the invention, and should not be considered as necessarily limitative of the invention, it being understood that many modifications can be made by those skilled in the art while : sti.ll practicing the invention claimed herein~
. I

CLAIMS: !

Claims (16)

I CLAIM:

1. In an IC digital-to-analog converter for use with a single supply voltage and operable to produce an output voltage referred to ground potential:
a plurality of current sources to be activated in a pattern corresponding to an applied digital signal;
means coupled to said current sources to produce an analog signal corresponding to the pattern of activation of said sources;
a buffer amplifier having an input circuit receiving said analog signal and an output circuit for producing an out-put voltage corresponding to said analog signal;
said output circuit including a drive transistor including means to sense the onset of saturation in the transistor and to produce a corresponding saturation signal;
and feedback means coupled to said sensing means and responsive to said saturation signal for reducing the level of the signal applied to said drive transistor as saturation begins to occur and developing an output voltage at levels near ground potential when said analog signal is near zero.

2. A converter as in Claim 1, wherein said sensing means comprises a second emitter in said drive transistor normally non-conductive but which begins to draw current as its potential approaches the transistor base potential when the applied signal approaches zero.

3. A converter as in Claim 2, including a base-driven transistor producing an output which is coupled to the input of said drive transistor; and means connecting said second emitter to the base of said base-driven transistor to limit the base current thereof as saturation is approached, thereby to correspondingly limit the signal applied to said drive transistor.

4. A converter as in Claim 1, wherein said drive transistor includes a first collector supplied with current;
a second collector for said drive transistor and diffused in a deep n+ plug extending down to the buried layer of the transistor; and means connecting said second collector to provide an output signal for said amplifier.

5. A converter as in Claim 1, including a differential pair of transistors;
means connecting said analog signal to one of said differential pair; and means connecting a signal to the other of said differential pair corresponding to the amplifier output voltage.

6. An IC digital-to-analog converter comprising:
a power supply producing a unipolar d-c voltage with respect to the reference potential of a reference terminal;
a plurality of current sources to be activated in a pattern corresponding to an applied digital signal and receiving power from said power supply;
means coupled to said current sources to develop from the currents thereof a unipolar analog signal with re-spect to said reference potential and corresponding in mag-nitude to the pattern of activation of said sources; and a buffer amplifier energized by said power supply, said buffer amplifier having an input circuit receiving said analog signal and an output circuit for producing an output voltage with respect to said reference potential in accord-ance with said analog signal;
said buffer amplifier including a drive transistor with saturation sensing means coupled to said circuit means operable to adjust automatically the input signal to said drive transistor so as to reduce saturation effects, as they axe sensed, thereby developing said output signal substan-tially in the full range between said reference potential and a second potential.

7. A converter as in Claim 17, wherein said circuit means comprises feedback means coupled to said sensing means and responsive to said saturation signal for reducing the level of the signal applied to said drive transistor as saturation begins to occur and developing an output voltage at levels substantially at said reference potential when said analog signal is substantially at zero.

8. A converter as in Claim 7, wherein said reference potential is ground.

9. An IC digital-to-analog converter comprising:
a power supply producing a d-c voltage with respect to the reference potential of a reference terminal;
a plurality of signal sources to be activated in a pattern corresponding to an applied digital signal;
means coupled to said signal sources to develop therefrom an analog signal corresponding in magnitude to the pattern of activation of said sources; and a buffer amplifier energized by said power supply, said buffer amplifier having an input circuit receiving said analog signal and an output circuit for producing an output voltage which is unipolar with respect to said reference potential and has a magnitude in accordance with said analog signal;

said buffer amplifier including a drive transistor with saturation sensing means; and circuit means coupled to said saturation sensing means and operable to adjust automatically the input signal to said drive transistor so as to reduce saturation effects, as they are sensed, and developing said output signal sub-stantially in the full range between said reference poten-tial and a second potential.

10. A converter as in Claim 9, wherein said circuit means comprises feedback means coupled to said sensing means and responsive to said saturation signal for reducing the level of the signal applied to said drive transistor as saturation begins to occur and developing an output voltage at levels substantially at said reference potential when said analog signal is substantially at the corresponding end of its range of variation.

11. In an IC electronic component of the type includ-ins an amplifier and signal-generating circuitry for develop-ing a variable input signal for said amplifier; said amplifier having a signal-responsive drive transistor for producing an output signal varying in correspondence to said input signal;
said component including power supply means comprising two supply terminals one of which is at a reference potential;
that improvement in such component for enabling said amplifier to be supplied with operating power only from said two power supply terminals and yet produce said output signal so that it faithfully varies with said input signal at any output level within a range of levels extending down to said reference potential; said improvement comprising;

means in said drive transistor for sensing the onset of saturation;
control signal means coupled to said sensing means for developing a control signal reflecting the degree of saturation in said drive transistor; and circuit means responsive to said control signal and operable automatically to adjust the drive signal applied to said drive transistor so as to reduce said satur-ation while providing for the development of said output signal at levels down to said reference potential without the detrimental changes in amplifier responsiveness which otherwise would result from uncontrolled saturation in the drive transistor.

12. Apparatus as claimed in Claim 11, wherein said saturation sensing means comprises an additional electrode diffused into the semiconductive material of said drive transistor.

13. Apparatus as claimed in Claim 12, wherein said drive transistor comprises a base diffusion into which is diffused an emitter electrode;
said additional electrode being diffused into said base.

14. Apparatus as claimed in Claim 11, wherein said circuit means comprises negative feedback means operable to develop a feedback signal opposing the input signal to said drive transistor as the onset of saturation is de-tected by sensing means.

15. Apparatus as claimed in Claim 11, wherein said drive transistor comprises base, emitter and collector electrodes operable for controlling the currents within said transistor; and a separate collector forming part of said drive transistor for developing said output signal without the effects of the voltage drop across the internal resistance of the transistor.

16. Apparatus as claimed in Claim 12, wherein said reference potential is ground.