CA1163700A - Radar signal processor - Google Patents
Radar signal processorInfo
- Publication number
- CA1163700A CA1163700A CA000385456A CA385456A CA1163700A CA 1163700 A CA1163700 A CA 1163700A CA 000385456 A CA000385456 A CA 000385456A CA 385456 A CA385456 A CA 385456A CA 1163700 A CA1163700 A CA 1163700A
- Authority
- CA
- Canada
- Prior art keywords
- count
- video
- processor
- threshold
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/28—Details of pulse systems
- G01S7/285—Receivers
- G01S7/292—Extracting wanted echo-signals
- G01S7/2923—Extracting wanted echo-signals based on data belonging to a number of consecutive radar periods
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/28—Details of pulse systems
- G01S7/285—Receivers
- G01S7/292—Extracting wanted echo-signals
- G01S7/2923—Extracting wanted echo-signals based on data belonging to a number of consecutive radar periods
- G01S7/2925—Extracting wanted echo-signals based on data belonging to a number of consecutive radar periods by using shape of radiation pattern
Landscapes
- Engineering & Computer Science (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Radar Systems Or Details Thereof (AREA)
- Variable-Direction Aerials And Aerial Arrays (AREA)
Abstract
ABSTRACT
A processor for operating on video and azimuth signals from a radar system having an antenna which scans in azimuth. The processor enhances the signal-to-noise ration of the video signals while imposing thereon a substantially constant azimuth delay error.
The processor includes a first circuit for forming and storing a count indicative of the video signal history in each range zone. The processor also includes a second circuit for generating and removing a flag signal indicative of azimuth leading and trailing edges respec-tively of a target pulse in the video signal. A gating circuit is included to pass video signals, for a given range zone, to an output terminal during the presence of a flag signal associated with the zone.
A processor for operating on video and azimuth signals from a radar system having an antenna which scans in azimuth. The processor enhances the signal-to-noise ration of the video signals while imposing thereon a substantially constant azimuth delay error.
The processor includes a first circuit for forming and storing a count indicative of the video signal history in each range zone. The processor also includes a second circuit for generating and removing a flag signal indicative of azimuth leading and trailing edges respec-tively of a target pulse in the video signal. A gating circuit is included to pass video signals, for a given range zone, to an output terminal during the presence of a flag signal associated with the zone.
Description
~ 7~ PD 7913~
l~ADA~ SIGNAL PROC~SSOR
1 I'he government of ttle United States of A~erica has rights i.n this invent;.on pursuant to Contract No.
N0002~-73-C-1175 awarded by the Department of the Navy.
' BACKGROUND OF_TIIE I~VEN17 ON
1. Field of the Invention This invention relates to radar siynal processors.
More specifically, this invention relates to improvements ; ' in radar signal processors providing enhanced video s;.gnal-to-noise ratios.
While the present invention ;s described herein '~''~ wi'th reference to specific embodiments, it should be understood that the invention is not limited thereto.
The improvements of the present invention may be adapted and employed for a variety of requirelnents as tl~ose 'skilled in the art will recogn;.ze in light of the present disclosure.
l~ADA~ SIGNAL PROC~SSOR
1 I'he government of ttle United States of A~erica has rights i.n this invent;.on pursuant to Contract No.
N0002~-73-C-1175 awarded by the Department of the Navy.
' BACKGROUND OF_TIIE I~VEN17 ON
1. Field of the Invention This invention relates to radar siynal processors.
More specifically, this invention relates to improvements ; ' in radar signal processors providing enhanced video s;.gnal-to-noise ratios.
While the present invention ;s described herein '~''~ wi'th reference to specific embodiments, it should be understood that the invention is not limited thereto.
The improvements of the present invention may be adapted and employed for a variety of requirelnents as tl~ose 'skilled in the art will recogn;.ze in light of the present disclosure.
2. Description of the Prior Art - -For radar systems whose primary function is dlsplay, .20 only a limi.ted amount of hardware can be devoted to filtra-tion functi'ons. This typically limits video filters used in displays to types such as single loop video integrators.
A single loop video inteyrator processes the incominy video signal using an inteyrati.on technique that substan-t.ially improves the signal-to noise ratio of the system.
Un~orturlately, si.nce the respollse of the integrator folloiJs ti)e siynal with some delay, this technique causes a delay ~. ' ~i37~0 l error (a~imuth bias error) wll;ch causes the irilage to be displayed ;n an improper az;muth`posit;on. Th;s azimuth bias error varies with the strèngth of the video signal, making bias delay compensation difficult if not impossi~le.
SUMMARY OF TEIE INVENTION
The signal processor of the present invention operates on video and azimuth signals from a radar system haviny a scanning antenna to improve the s;gnal-to-noise ratio of the video signal while ensuring the azimuth bias error is substantially constant and thereor readily correctable.
The radar signal processor of the present inven-tion includes a circuit which forms and stores a count whichis indicative of the history of the amplitude of the video signal within each of a plurality of range zones.
A second circuit is included which generates a flac~ bit, when a count threshold is exceeded. For each range zone, the flag bit is stored along with the count. The presence of the flag bit indicat~s that the leading edge of a target has been detected in the azimuth dimension.
Logic is provided to gate the radar video signal through the processor to an output terminal whenever the flag bit is present.
. .
BRIEF DESCRIPTION OF T~IE DRAWII~GS
FIG. 1 is a block diagram representation of the radar signal processor of the present invention;
FIG. 2 is a graph comparing the signal detect-ability of the present invention to that of a typical single loop integrator; and FIG. 3 is a graph showing the azimuth bias comparison of the present invention to that of a typical single loop integrator.
11~371~0 1 ~SCRIPTIO~ o~ Tll~ VENTIO~J
~ ~lock diayram of the processor 10 of the present inventiotl is shown in FIG. 1. It includes a digital mernory 12, a clisplay range counter 14, a video integrator address control 16, a display video tllreshold comparator 18, flip/flops 20 and 22 c~unt update logic 24 and a shift register 26 for forming and storing a count indicative of the video signal history for eacll of a plurality o range zones.
The digital memory 12 provides one address for each display range zone. At each address the memory can store a six bit word which is then used to provide video inte-gration for the range zone unique to that address. Five of the memory bits stored at each address are used to store a running count of the digital video history. The digital video history is a record of the n~m~er of s~eeps dur;ng ~Ihich the receiv~d video siynal exceeded an operator selectcd i.e. display threshold. The video display - threshold selection is made at an operator control panel 19.
The sixth bit is used as a flag bit to indicate whether the count threshold has ~een reached for a particular range bin. For example, if the flag bit is false or at a logic level "0", it indicates that the count threshold has not been reached and likewise, if the flag bit is true or at a logical "1 level, the count threshold has been reached.
The memory 12 is addressed by the range counter 14 and the video integrator address control 16. The range.
counter 14 is synchronized to the radar range by a master trigger signal from a radar transmitter 15.
The radar video signal from the radar receiver 17 is compared to the operator selected video display threshold by the comparator 18. THe comparator 18 provides inputs to flip/flops 20 and 22. Flip/flops 20 and 22 provide 11~00 1 data to thc count update logic ~hich determines the cxtent to wl~ich the COUIIt is to chanye lhe prev;ous coullt- for a particular ranye zone address is prov;dcd by the me~mory 12 to the count update logic 24. lhe count update logic 24 then incremellts or decremel-lts the counl: according to 1:he outputs of the Ll;p/flops 20 and 22 arld stores the new count in register 26. In the preferred embodiment, if the threshold is exceeded and the flag is false, the count is incremented by two by flip/fl~ 20 and count update logic 24. If the threshold is exceeded and the flag is true, the count is decremented by one by flip/~lop 20 and logic 24. If the threshold is not exceeded and the flag is false, the count is decremented by one by flip/flop 22 and logic 24.
If the threshold is not exceeded and the flag ;s true, the count is incremented by t~o by flip/flop 22 and logic 24. Ihe count will not decrement below zero. The count update logic 24 ;ncludes a shlft register, a summer or ad-ler and reset: logic, (not shown). It is understood, ho~/ever, that other component devices or circuits can be used to perform the function of count update logic 24 without departiny from ~he scope o~ this inventon. A
microprocessor, for exalnple, could provide such a feasible alternative.
The count stored in register 26 is input to the integrator memory 12 where it replaces the previous count at the same ran~e zone address. The current count is also input to a comparator 28 ~here it is compared to the inte-yrator count threshold provided by the register 30.
A count comparator 28 and an integrator coun~
tllreshold selection circuit 30 are provided for adding or removing a flag bit indicative of a leading or trailing l~W7~0 1 edge of a target in the azimuth dimension ~hen the stored count, for a given rangc zone, exceeds the predetermined integrator co~nt threshold.
The comparator 28 provides a logic level "1" output i~ the integrator count threshold is exceeded and a logic level "0" output if the integrator count threshold is not exceeded. The flag bit ;s input to the memory 12 at the same range bin address as the correspondincJ integrator count.
If the flag is true, the digitized video signal is ~assed from the radar receiver 17 to a video memory 33 by a gate 32.
As an optional feature, the digital video can be forced to be at least a minimum discernable level when the lS correlator flag is true so that the digital video display is nonzero when the flag bit is true. This allows the digital video azimuth width to be the same as tlle analocJ
vidco azimuth width.
When the count threshold is exceeded, as when a target leading edye is detected, the flag is true, the counl: is reset to zero and counter logic is reversed so that a video amplitude exceeding the display threshold decrements the counter by "1" and an amplitude not `-exceeding the display thresl-old increments the counter by "2". This indicates that the processor 10 is now in a mode searching for the trailing edge of the video signal.
The trailing edge threshold is typically equal to the leading edge threshold. When it is reached, the flag bit is removed by logic 24 and counter logic is reversed once again, and the video input to the video memory for this range bin is set to zero. The next range clock from the display range counter 14 increments the display range counter 14 which then addresses the next range zone in the video memory 12 to reini~iate the correlation process.
~1ti37~
1 ~e~cause the processor 10 is a binary accumulator, it docs not directly provide an indicatlon oL the signal amplilu(le for display. Instead of displaying the output Or the~ inte~Jrator directly, as in sinyle loop integration technique of the prior art, the present invention passes the digitized video for memoL-y and/or display when a predetermined count is reached.
Since the target is expected to provide a certain azimuth profile, ,i.e., sinx , the expected azimuth delay ,in declaring a target leading and trailing edge can be accurately predicted. It is nearly constant for each integrator count threshold regardless of the video s,ignal amplitude. This makes bias delay compensation by microprocessor 34 possible.
The video memory 33 implements'the specific objective of storing radar video for azimuth compensation. Radar v;,deo is received as a sequenc~ of range bins on st:alldard radar sweep lines. Each ranye bin is digitized into three ~ or four ~its of video. The output video is in the form 2n f horizontal raster lines for a composite video format ior display. The microprocessor 34 sends data to the vi,deo memory 33 which defines the init,ial range start point and azimuth angle (corrected for bias delay) of a sweep line and also a control which initiates the loading of a sweep line. Old video information is read out of the memory 33 while new video information is written into the memory 33.
For each cell, peak detection (not shown) is used to combine old video with new video for the cell.
The performance of the present invention as obtained from computer simula,tions is shown in FIGS. 2 and 3. ~IG. 2 compares the signal detectability of the present invention 40 with that of a typical signal loop integrator 42 for radar with thirteen sweeps per azimuth ' beamwidth. These results show that the signal detec-tion capability of the two integrators is essentially llW7~:~0 1 identical and ~l~at no d~tecta~ility loss is incurre~d byusing the sigllal processor of the present invention.
l~`I(;. 3 compares the a~imuth centroi(l (beallsplit) bias o~ the present inventioll 44 witll that of a typical S single loop integrator 46. hote tha~ the single loop integrator azimuth ~ias varies from four to ten sweeps, as the signal-to-noise ratio changes for an azimul;h varia-tion of 250 percent. On the contrary, the azim~lth bias of the present invent;on is effectively constant. This allows a very simple and very accurate azimuth bias correction to be made for the radar signal processor of the present invention.
I'hus, the s,ignal processor 10 of the ~resent invention provides approximately the same dctectability as the single loop integrator, a very predictable delay in leading and trailiny edge response and significantly ' improved azimuth accuracy as compared to the single loop integration technique.
- While the present invention has been described herein with reference to a particular embodiment, it should be ~nderstood that the invention is not limited thereto. One skilled in the art to which this invention pertains will recogni~e that many circuits a~d subsystems can be employed to implement a variety of functions described above. It is nonetheless contemplated ~y the appended claims to cover any and all such modifications within the teachings of the present invention.
WJB:kl~
[88-1/20-1~]
A single loop video inteyrator processes the incominy video signal using an inteyrati.on technique that substan-t.ially improves the signal-to noise ratio of the system.
Un~orturlately, si.nce the respollse of the integrator folloiJs ti)e siynal with some delay, this technique causes a delay ~. ' ~i37~0 l error (a~imuth bias error) wll;ch causes the irilage to be displayed ;n an improper az;muth`posit;on. Th;s azimuth bias error varies with the strèngth of the video signal, making bias delay compensation difficult if not impossi~le.
SUMMARY OF TEIE INVENTION
The signal processor of the present invention operates on video and azimuth signals from a radar system haviny a scanning antenna to improve the s;gnal-to-noise ratio of the video signal while ensuring the azimuth bias error is substantially constant and thereor readily correctable.
The radar signal processor of the present inven-tion includes a circuit which forms and stores a count whichis indicative of the history of the amplitude of the video signal within each of a plurality of range zones.
A second circuit is included which generates a flac~ bit, when a count threshold is exceeded. For each range zone, the flag bit is stored along with the count. The presence of the flag bit indicat~s that the leading edge of a target has been detected in the azimuth dimension.
Logic is provided to gate the radar video signal through the processor to an output terminal whenever the flag bit is present.
. .
BRIEF DESCRIPTION OF T~IE DRAWII~GS
FIG. 1 is a block diagram representation of the radar signal processor of the present invention;
FIG. 2 is a graph comparing the signal detect-ability of the present invention to that of a typical single loop integrator; and FIG. 3 is a graph showing the azimuth bias comparison of the present invention to that of a typical single loop integrator.
11~371~0 1 ~SCRIPTIO~ o~ Tll~ VENTIO~J
~ ~lock diayram of the processor 10 of the present inventiotl is shown in FIG. 1. It includes a digital mernory 12, a clisplay range counter 14, a video integrator address control 16, a display video tllreshold comparator 18, flip/flops 20 and 22 c~unt update logic 24 and a shift register 26 for forming and storing a count indicative of the video signal history for eacll of a plurality o range zones.
The digital memory 12 provides one address for each display range zone. At each address the memory can store a six bit word which is then used to provide video inte-gration for the range zone unique to that address. Five of the memory bits stored at each address are used to store a running count of the digital video history. The digital video history is a record of the n~m~er of s~eeps dur;ng ~Ihich the receiv~d video siynal exceeded an operator selectcd i.e. display threshold. The video display - threshold selection is made at an operator control panel 19.
The sixth bit is used as a flag bit to indicate whether the count threshold has ~een reached for a particular range bin. For example, if the flag bit is false or at a logic level "0", it indicates that the count threshold has not been reached and likewise, if the flag bit is true or at a logical "1 level, the count threshold has been reached.
The memory 12 is addressed by the range counter 14 and the video integrator address control 16. The range.
counter 14 is synchronized to the radar range by a master trigger signal from a radar transmitter 15.
The radar video signal from the radar receiver 17 is compared to the operator selected video display threshold by the comparator 18. THe comparator 18 provides inputs to flip/flops 20 and 22. Flip/flops 20 and 22 provide 11~00 1 data to thc count update logic ~hich determines the cxtent to wl~ich the COUIIt is to chanye lhe prev;ous coullt- for a particular ranye zone address is prov;dcd by the me~mory 12 to the count update logic 24. lhe count update logic 24 then incremellts or decremel-lts the counl: according to 1:he outputs of the Ll;p/flops 20 and 22 arld stores the new count in register 26. In the preferred embodiment, if the threshold is exceeded and the flag is false, the count is incremented by two by flip/fl~ 20 and count update logic 24. If the threshold is exceeded and the flag is true, the count is decremented by one by flip/~lop 20 and logic 24. If the threshold is not exceeded and the flag is false, the count is decremented by one by flip/flop 22 and logic 24.
If the threshold is not exceeded and the flag ;s true, the count is incremented by t~o by flip/flop 22 and logic 24. Ihe count will not decrement below zero. The count update logic 24 ;ncludes a shlft register, a summer or ad-ler and reset: logic, (not shown). It is understood, ho~/ever, that other component devices or circuits can be used to perform the function of count update logic 24 without departiny from ~he scope o~ this inventon. A
microprocessor, for exalnple, could provide such a feasible alternative.
The count stored in register 26 is input to the integrator memory 12 where it replaces the previous count at the same ran~e zone address. The current count is also input to a comparator 28 ~here it is compared to the inte-yrator count threshold provided by the register 30.
A count comparator 28 and an integrator coun~
tllreshold selection circuit 30 are provided for adding or removing a flag bit indicative of a leading or trailing l~W7~0 1 edge of a target in the azimuth dimension ~hen the stored count, for a given rangc zone, exceeds the predetermined integrator co~nt threshold.
The comparator 28 provides a logic level "1" output i~ the integrator count threshold is exceeded and a logic level "0" output if the integrator count threshold is not exceeded. The flag bit ;s input to the memory 12 at the same range bin address as the correspondincJ integrator count.
If the flag is true, the digitized video signal is ~assed from the radar receiver 17 to a video memory 33 by a gate 32.
As an optional feature, the digital video can be forced to be at least a minimum discernable level when the lS correlator flag is true so that the digital video display is nonzero when the flag bit is true. This allows the digital video azimuth width to be the same as tlle analocJ
vidco azimuth width.
When the count threshold is exceeded, as when a target leading edye is detected, the flag is true, the counl: is reset to zero and counter logic is reversed so that a video amplitude exceeding the display threshold decrements the counter by "1" and an amplitude not `-exceeding the display thresl-old increments the counter by "2". This indicates that the processor 10 is now in a mode searching for the trailing edge of the video signal.
The trailing edge threshold is typically equal to the leading edge threshold. When it is reached, the flag bit is removed by logic 24 and counter logic is reversed once again, and the video input to the video memory for this range bin is set to zero. The next range clock from the display range counter 14 increments the display range counter 14 which then addresses the next range zone in the video memory 12 to reini~iate the correlation process.
~1ti37~
1 ~e~cause the processor 10 is a binary accumulator, it docs not directly provide an indicatlon oL the signal amplilu(le for display. Instead of displaying the output Or the~ inte~Jrator directly, as in sinyle loop integration technique of the prior art, the present invention passes the digitized video for memoL-y and/or display when a predetermined count is reached.
Since the target is expected to provide a certain azimuth profile, ,i.e., sinx , the expected azimuth delay ,in declaring a target leading and trailing edge can be accurately predicted. It is nearly constant for each integrator count threshold regardless of the video s,ignal amplitude. This makes bias delay compensation by microprocessor 34 possible.
The video memory 33 implements'the specific objective of storing radar video for azimuth compensation. Radar v;,deo is received as a sequenc~ of range bins on st:alldard radar sweep lines. Each ranye bin is digitized into three ~ or four ~its of video. The output video is in the form 2n f horizontal raster lines for a composite video format ior display. The microprocessor 34 sends data to the vi,deo memory 33 which defines the init,ial range start point and azimuth angle (corrected for bias delay) of a sweep line and also a control which initiates the loading of a sweep line. Old video information is read out of the memory 33 while new video information is written into the memory 33.
For each cell, peak detection (not shown) is used to combine old video with new video for the cell.
The performance of the present invention as obtained from computer simula,tions is shown in FIGS. 2 and 3. ~IG. 2 compares the signal detectability of the present invention 40 with that of a typical signal loop integrator 42 for radar with thirteen sweeps per azimuth ' beamwidth. These results show that the signal detec-tion capability of the two integrators is essentially llW7~:~0 1 identical and ~l~at no d~tecta~ility loss is incurre~d byusing the sigllal processor of the present invention.
l~`I(;. 3 compares the a~imuth centroi(l (beallsplit) bias o~ the present inventioll 44 witll that of a typical S single loop integrator 46. hote tha~ the single loop integrator azimuth ~ias varies from four to ten sweeps, as the signal-to-noise ratio changes for an azimul;h varia-tion of 250 percent. On the contrary, the azim~lth bias of the present invent;on is effectively constant. This allows a very simple and very accurate azimuth bias correction to be made for the radar signal processor of the present invention.
I'hus, the s,ignal processor 10 of the ~resent invention provides approximately the same dctectability as the single loop integrator, a very predictable delay in leading and trailiny edge response and significantly ' improved azimuth accuracy as compared to the single loop integration technique.
- While the present invention has been described herein with reference to a particular embodiment, it should be ~nderstood that the invention is not limited thereto. One skilled in the art to which this invention pertains will recogni~e that many circuits a~d subsystems can be employed to implement a variety of functions described above. It is nonetheless contemplated ~y the appended claims to cover any and all such modifications within the teachings of the present invention.
WJB:kl~
[88-1/20-1~]
Claims (10)
1. A processor for operating on video and azimuth signals from a radar system, having an antenna which scans in azimuth, such that the signal-to-noise ratio of the video signals being processed therethrough is enhanced while the delay in detecting the leading edge of the target in the azimuth dimension is substantially con-stant, said processor comprising:
first means for forming and storing a count indica-tive of the video signal history for each of a plurality of range zones;
second means for providing a flag signal indicative of a leading edge of a target in the azimuth dimension when the stored count associated with a given range zone exceeds a preselected level and for removing said flag signal on a trailing edge of said target; and gating means for allowing the radar video signals for a given zone to pass to a display memory during the presence of a flag signal associated with said given zone.
first means for forming and storing a count indica-tive of the video signal history for each of a plurality of range zones;
second means for providing a flag signal indicative of a leading edge of a target in the azimuth dimension when the stored count associated with a given range zone exceeds a preselected level and for removing said flag signal on a trailing edge of said target; and gating means for allowing the radar video signals for a given zone to pass to a display memory during the presence of a flag signal associated with said given zone.
2. The processor of Claim 1 wherein said first means includes means for storing a video threshold level and for comparing said radar video signals to said video threshold level.
3. The processor of Claim 2 wherein said first means includes means for incrementing the count a first preselected amount for each respective range zone during each antenna scan when the radar video signal for the given range zone exceeds said first threshold level and for decrementing the count a second preselected amount during each antenna scan when the radar video signal for the given range zone does not exceed said first threshold.
- 4. The processor of Claim 3 wherein said first means includes means for incrementing the count by said first preselected amount for each respective range zone during each antenna scan when the flag signal is present and the radar video signal for the given range zone does not exceed said video threshold and for decrementing the count by said second preselected amount during each antenna scan when the flag signal is present and the radar video signal for the given range zone exceeds said video threshold.
5. The processor of Claim 1 wherein said second means includes means for storing a first count threshold level.
6. The processor of Claim 5 wherein said second means includes means for comparing the current count to said first count threshold level and for providing a flag signal when the current count reaches said first count threshold.
7. The processor of Claim 6 wherein said second means includes means for resetting the count whenever the count reaches a count threshold.
8. The processor of Claim 7 wherein said second means includes means for removing the flag signal when the count reaches a second count threshold.
9. A processor for operating on video and azimuth signals from a radar system having an antenna which scans in azimuth such that the signal-to-noise ratio of the video signals being processed therethrough is enhanced while the delay in detecting the leading edge of the target in the azimuth dimension is substantially con-stant, said processor comprising:
first means for forming and storing a count indica-tive of the video signal history for each of a plurality of range zones, said first means including means for storing a video threshold, means for comparing said video signals to said threshold, means for incrementing the count a first preselected amount for each respec-tive range zone during each antenna scan when the radar video signal for the given range zone exceeds said video threshold level and for decrementing the count a second preselected amount during each antenna scan when the radar video signal for the given range zone does not exceed said video threshold, and means for incrementing the count by said first preselected amount for each respective range zone during each antenna scan when a flag signal is present and the radar video signal for the given range zone does not exceed said video threshold and for decrementing the count by said second preselected amount during each antenna scan when the flag signal is present and the radar video signal for the given range zone exceeds said video threshold;
second means for providing said flag signal indica-tive of a leading edge of a target in the azimuth dimen-sion when the stored count associated with a given range zone exceeds a preselected level and for removing said flag signal on a trailing edge of said target when the stored count associated with a given range zone exceeds a preselected level; and gating means for allowing the radar video signals for a given zone to pass to a display memory during the presence of a flag signal associated with said given zone.
first means for forming and storing a count indica-tive of the video signal history for each of a plurality of range zones, said first means including means for storing a video threshold, means for comparing said video signals to said threshold, means for incrementing the count a first preselected amount for each respec-tive range zone during each antenna scan when the radar video signal for the given range zone exceeds said video threshold level and for decrementing the count a second preselected amount during each antenna scan when the radar video signal for the given range zone does not exceed said video threshold, and means for incrementing the count by said first preselected amount for each respective range zone during each antenna scan when a flag signal is present and the radar video signal for the given range zone does not exceed said video threshold and for decrementing the count by said second preselected amount during each antenna scan when the flag signal is present and the radar video signal for the given range zone exceeds said video threshold;
second means for providing said flag signal indica-tive of a leading edge of a target in the azimuth dimen-sion when the stored count associated with a given range zone exceeds a preselected level and for removing said flag signal on a trailing edge of said target when the stored count associated with a given range zone exceeds a preselected level; and gating means for allowing the radar video signals for a given zone to pass to a display memory during the presence of a flag signal associated with said given zone.
10. The processor of Claim 9 wherein said second means includes means for resetting the count whenever the count reaches said preselected levels.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US193,199 | 1980-10-02 | ||
| US06/193,199 US4355312A (en) | 1980-10-02 | 1980-10-02 | Radar signal processor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1163700A true CA1163700A (en) | 1984-03-13 |
Family
ID=22712621
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000385456A Expired CA1163700A (en) | 1980-10-02 | 1981-09-09 | Radar signal processor |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4355312A (en) |
| JP (1) | JPH0353585B2 (en) |
| AU (1) | AU539748B2 (en) |
| CA (1) | CA1163700A (en) |
| DE (1) | DE3152403A1 (en) |
| ES (1) | ES8304319A1 (en) |
| WO (1) | WO1982001254A1 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL8202784A (en) * | 1982-07-09 | 1984-02-01 | Hollandse Signaalapparaten Bv | DATA CONVERSION UNIT T.B.V. AN IMPULSE RADAR DEVICE. |
| US4554547A (en) * | 1982-12-13 | 1985-11-19 | Allied Corporation | Range processor for DME |
| US4607258A (en) * | 1983-03-10 | 1986-08-19 | Sperry Corporation | Radar video dehancer |
| US7808423B2 (en) * | 2007-04-05 | 2010-10-05 | Honeywell International Inc. | Methods for rapid target acquisitions in range measurement systems |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3969616A (en) * | 1965-06-29 | 1976-07-13 | General Dynamics Corporation | Digital range computer systems for air navigation systems such as tacan |
| US3680095A (en) * | 1967-04-17 | 1972-07-25 | Hughes Aircraft Co | Automatic detection criteria control unit for pencil beam radars |
| FR2043871A5 (en) * | 1969-02-28 | 1971-02-19 | Dassault Electronique | |
| US3683380A (en) * | 1971-01-11 | 1972-08-08 | Thomas C Cantwell Jr | Cascaded digital integrator target detection system |
| CH550409A (en) * | 1972-10-12 | 1974-06-14 | Contraves Ag | ACCUMULATING RADAR ECHO DETECTOR. |
| US3987441A (en) * | 1974-03-04 | 1976-10-19 | Rca Corporation | Tracking gate servoed by relative range |
| JPS5841474B2 (en) * | 1975-04-04 | 1983-09-12 | 三菱電機株式会社 | radar |
| US4048636A (en) * | 1975-09-26 | 1977-09-13 | The United States Of America As Represented By The Secretary Of The Navy | Secondary radar/iff anti-target splitting azimuth determiner |
| US4195297A (en) * | 1978-02-23 | 1980-03-25 | Motorola, Inc. | Short range radar tracking apparatus |
-
1980
- 1980-10-02 US US06/193,199 patent/US4355312A/en not_active Expired - Lifetime
-
1981
- 1981-09-09 CA CA000385456A patent/CA1163700A/en not_active Expired
- 1981-10-01 JP JP56503299A patent/JPH0353585B2/ja not_active Expired
- 1981-10-01 DE DE813152403A patent/DE3152403A1/en active Granted
- 1981-10-01 ES ES505928A patent/ES8304319A1/en not_active Expired
- 1981-10-01 WO PCT/US1981/001325 patent/WO1982001254A1/en active Application Filing
- 1981-10-01 AU AU77232/81A patent/AU539748B2/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| WO1982001254A1 (en) | 1982-04-15 |
| ES505928A0 (en) | 1983-02-16 |
| DE3152403C2 (en) | 1991-01-10 |
| ES8304319A1 (en) | 1983-02-16 |
| DE3152403A1 (en) | 1982-11-18 |
| AU539748B2 (en) | 1984-10-11 |
| JPS57501648A (en) | 1982-09-09 |
| US4355312A (en) | 1982-10-19 |
| AU7723281A (en) | 1982-04-28 |
| JPH0353585B2 (en) | 1991-08-15 |
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