CA1156385A - Channel identification apparatus useful in a sweep type tuning system - Google Patents
Channel identification apparatus useful in a sweep type tuning systemInfo
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- CA1156385A CA1156385A CA000352638A CA352638A CA1156385A CA 1156385 A CA1156385 A CA 1156385A CA 000352638 A CA000352638 A CA 000352638A CA 352638 A CA352638 A CA 352638A CA 1156385 A CA1156385 A CA 1156385A
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Abstract
RCA 73,145 ABSTRACT OF THE DISCLOSURE
In a tuning system for generating a tuning voltage for tuning a television receiver, channel identification apparatus includes a memory for storing binary signals repre-senting boundary voltages having magnitudes corresponding to magnitudes of the tuning voltage between tuning voltage ranges for respective adjacent channels. As the memory locations are addressed, the boundary voltages are compared to the tuning voltages. Control apparatus causes the memory location associated with the next boundary voltage to be addressed and causes channel number apparatus to generate binary signals representing the next channel number when the magnitude of a predetermined one of the boundary voltage associated with an addressed one of the memory locations and the tuning voltage exceeds the magnitude of the other one.
Display apparatus displays the channel number represented by the binary signals generated by the channel number means.
In a tuning system for generating a tuning voltage for tuning a television receiver, channel identification apparatus includes a memory for storing binary signals repre-senting boundary voltages having magnitudes corresponding to magnitudes of the tuning voltage between tuning voltage ranges for respective adjacent channels. As the memory locations are addressed, the boundary voltages are compared to the tuning voltages. Control apparatus causes the memory location associated with the next boundary voltage to be addressed and causes channel number apparatus to generate binary signals representing the next channel number when the magnitude of a predetermined one of the boundary voltage associated with an addressed one of the memory locations and the tuning voltage exceeds the magnitude of the other one.
Display apparatus displays the channel number represented by the binary signals generated by the channel number means.
Description
` 1156385 1 -1- RCA 73,145 CHANNEL IDENTIFICATION APPAR~TUS US~FUL IN
A SWEEP TYPE TUNING SY~TEM
The present invention relates to the field of digital tuning systems.
A number of digital tuning systems for control'ing a voltage controlled oscillator to generate a local oscillator signal for tuning a radio or television receiver are known.
These digital tuning systems may b~i generally categorized as being either of the frequency syllthesizer, voltage synthesizer or voltage sweep type.
lS Frequency synthesizers are typically closed loop.
One type of frequency synthesizer includes a phase or fre~uency comparator for generating the control voltage for a local oscillator signal by comparing the phase and/or frequency of a variable frequency signal derived by the ~, 20frequency division of the local oscillator signal and a , relatively stable reference frequency signal. The frequency ., of the loop and thereby the frequency of the local oscillator signal is determined by division factors of fixed and , .,~
programmable frequency dividers in the loopO The programmable divider is controlled in response to binary signals repre-senting the number of a selected channel to determine the particular local oscillator frequency. Another type of frequency synthesizer includes a counter for counting in cycles of a voltage controlled local oscillator signal and a count comparator for comparing the number accumulated by the counter with a number derived from binary signals representing the channel number of a selected channel to develop a local oscillator control voltage. In either system channel numbers of selected channels can be readily displayed in response to the binary signals representing the number of the selected channels. Although such frequency synthe-sizers are advantageous in that the frequencies of the local oscillator signal are relatively accurate because of the closed loop nature of the systems, such systems are relatively expensive due ~o the cost of the high speed dividers and ... .
1 -2- RCA 73,145 counters they nccessarily employ.
Voltage synthesizers are typically open loop ssystems and generally include a m~mory having a plurality of tuning volta~e memory loc~tions for storing binary signals representing the tuning voltages ~r each of the channels that a user may s~lect. The channel numbers of selected channels can be readily displayed, for example, in response to binary signals representing the channel numbers and utilized to address corresponding ~uning voltage memory locations. Although such voltage synthesizers are advanta-geous in that they are relatively inexpensive compared with frequency synthesizers because they do not require high 15speed frequency dividers and counters, they tend to be less accurate because the required precision and resolution in converting the binary signals stored in the tuning voltage memory locations to the corresponding tuning voltages is not readily attainable in open loop systems.
20 ~any tuning systems of the voltage sweep type are known. Basically, they all generate a ramp-like tuning voltage which is utilized to sweep the frequency of the local ~ oscillator signal. In its simplest form, the magnitude of the tuning voltage is increased or decreased under user 25control by means of a potelltiometer or the like until the user determines that an acceptable station has been reached.
" Signal sweeping systems are also ~nown in which the ~agnitudeof a tuning voltage is changed until a carrier is automatic-ally detected~ Such sweep syste~s are advantageous in ~Othat they are relatively accurate compared to voltage synthesizers since the tuning voltage is continuously adjusted until an acceptable channel is located and are relatively inexpensive compared to frequency synthesizers since they do not require high speed frequency ~ividers and 35counters. Ho~ev~r, since ~he tuning voltage is not derived as part of an operation involving the use of binary signals representing the number of a selected channel, additional apparatus must be provided for channel identification.
While it is possible to employ high speed counters - 40to determine the frequency of the local oscillator signal and .
1 -3- RCA 73,145 from the frequency derive the number of the selected channel, the use of high speed counters is to be avoided to maintain 5the cost effectiveness of sweep type systems.
Apparatus are also known for monitoring the channel to which a receiver is tuned by examining the tuning voltage.
In these systems the tuning voltage for a selected channel to which the receiver is already tuned is compared with voltages lOhaving magnitudes corresponding to the magnitudes of the tun-ing voltage to tune respective channels stored in memory loca-tions of a memory. The memory locations are successively addressed until there is at least an approximate equality between the tuning voltage and one of the stored voltages.
15The number of the selected channel is derived from the address of the memory location at which the approximate equality existed. Such systems may be used by television rating services to identify a limited number of channels in a par-ticular viewing area. However, they are not particularly well 20suited for television receivers to identify all of the _ channels in the television tuning range because of the need for greater resolution in accurately distinguishing between closely spaced channels in the latter application. ~oreover, such monitoring systems are not particularly well suited for
A SWEEP TYPE TUNING SY~TEM
The present invention relates to the field of digital tuning systems.
A number of digital tuning systems for control'ing a voltage controlled oscillator to generate a local oscillator signal for tuning a radio or television receiver are known.
These digital tuning systems may b~i generally categorized as being either of the frequency syllthesizer, voltage synthesizer or voltage sweep type.
lS Frequency synthesizers are typically closed loop.
One type of frequency synthesizer includes a phase or fre~uency comparator for generating the control voltage for a local oscillator signal by comparing the phase and/or frequency of a variable frequency signal derived by the ~, 20frequency division of the local oscillator signal and a , relatively stable reference frequency signal. The frequency ., of the loop and thereby the frequency of the local oscillator signal is determined by division factors of fixed and , .,~
programmable frequency dividers in the loopO The programmable divider is controlled in response to binary signals repre-senting the number of a selected channel to determine the particular local oscillator frequency. Another type of frequency synthesizer includes a counter for counting in cycles of a voltage controlled local oscillator signal and a count comparator for comparing the number accumulated by the counter with a number derived from binary signals representing the channel number of a selected channel to develop a local oscillator control voltage. In either system channel numbers of selected channels can be readily displayed in response to the binary signals representing the number of the selected channels. Although such frequency synthe-sizers are advantageous in that the frequencies of the local oscillator signal are relatively accurate because of the closed loop nature of the systems, such systems are relatively expensive due ~o the cost of the high speed dividers and ... .
1 -2- RCA 73,145 counters they nccessarily employ.
Voltage synthesizers are typically open loop ssystems and generally include a m~mory having a plurality of tuning volta~e memory loc~tions for storing binary signals representing the tuning voltages ~r each of the channels that a user may s~lect. The channel numbers of selected channels can be readily displayed, for example, in response to binary signals representing the channel numbers and utilized to address corresponding ~uning voltage memory locations. Although such voltage synthesizers are advanta-geous in that they are relatively inexpensive compared with frequency synthesizers because they do not require high 15speed frequency dividers and counters, they tend to be less accurate because the required precision and resolution in converting the binary signals stored in the tuning voltage memory locations to the corresponding tuning voltages is not readily attainable in open loop systems.
20 ~any tuning systems of the voltage sweep type are known. Basically, they all generate a ramp-like tuning voltage which is utilized to sweep the frequency of the local ~ oscillator signal. In its simplest form, the magnitude of the tuning voltage is increased or decreased under user 25control by means of a potelltiometer or the like until the user determines that an acceptable station has been reached.
" Signal sweeping systems are also ~nown in which the ~agnitudeof a tuning voltage is changed until a carrier is automatic-ally detected~ Such sweep syste~s are advantageous in ~Othat they are relatively accurate compared to voltage synthesizers since the tuning voltage is continuously adjusted until an acceptable channel is located and are relatively inexpensive compared to frequency synthesizers since they do not require high speed frequency ~ividers and 35counters. Ho~ev~r, since ~he tuning voltage is not derived as part of an operation involving the use of binary signals representing the number of a selected channel, additional apparatus must be provided for channel identification.
While it is possible to employ high speed counters - 40to determine the frequency of the local oscillator signal and .
1 -3- RCA 73,145 from the frequency derive the number of the selected channel, the use of high speed counters is to be avoided to maintain 5the cost effectiveness of sweep type systems.
Apparatus are also known for monitoring the channel to which a receiver is tuned by examining the tuning voltage.
In these systems the tuning voltage for a selected channel to which the receiver is already tuned is compared with voltages lOhaving magnitudes corresponding to the magnitudes of the tun-ing voltage to tune respective channels stored in memory loca-tions of a memory. The memory locations are successively addressed until there is at least an approximate equality between the tuning voltage and one of the stored voltages.
15The number of the selected channel is derived from the address of the memory location at which the approximate equality existed. Such systems may be used by television rating services to identify a limited number of channels in a par-ticular viewing area. However, they are not particularly well 20suited for television receivers to identify all of the _ channels in the television tuning range because of the need for greater resolution in accurately distinguishing between closely spaced channels in the latter application. ~oreover, such monitoring systems are not particularly well suited for
2~sweep type systems to display the channel numbers of channels passed before an acceptable channel is located since the tun-ing voltage changes until an acceptable channel is located.
In sweep systems, it may be desirable to display the channel number of channels passed to reach the acceptable channel so 30that users have a visible indication that the system is oper-ating and are therefore not annoyed by apparent lack of operation as an acceptable channel is sought.
A system for tuning a receiver to various channels 35includes a local oscillator means for generating a local oscillator signal appropriate for tuning the receiver to various channels in response to the magnitudes of a tuning voltage. The tuning voltage may be generated by apparatus -, including signal-seeking means for changing the magnitude of 40 the tuning voltage to automatically locate an acceptable . .
, 1 -4- RCA 73,145 channel or manual means for changing the magnitude of the tuning voltage until an acceptable channel is located by a suser. To display the channel numbers, the tuning system includes memory means, e.g., a PROM (Programmable Read Only Memory), including a plurality of memory locations each for storing binary signals representing a respective boundary voltage substantially equal to the tuning voltage at a fre-quency between the tuning voltage ranges of adjacent channels.
Address means is provided for addressing the memory locations.
As the memory locations are addressed, comparison means compares the tuning voltage to the boundary voltages. Control means causes the address means to address the memory location 15corresponding to the boundary voltage for the next channe~
until the magnitude of a predetermined one of the tuning voltage and the boundary voltage associated with an addressed memory exceeds the magnitude of the other one. Channel number display means displays the channel number of the 20channel associated with a presently addressed memory location.
By additional means, where it is desired to display channel numbers as the magnitude of the tuning voltage is being changed, the addressing of memory locations in sequence may occur during the interval in which the magnitude of the 25tuning voltage is being changed.
IN THE DRAWINGS:
FIGURES 1, la, lb and lc, which should be referred to concurrently, show partially in block diagram form and partially in schematic diagram form an embodiment of the 30present tuning system as it is employed in a television receiver.
FIGURE 2 shows tuning voltage characteristics of a voltage controlled tuner that may be employed in the present tuning system useful in facilitating an under-35standing of the present tuning system.
., 1 -5- RCA 73,145 of a boundary voltage memory emplo~ in the present tuning system.
FIGURES 4a, 4b and 4c show a flow chart indicating the operation of the arran~ement shown in FIGURES 1, la, lb and lc.
FIGURES 5 and 6 show in block diagram form apparatus for programming of a boundary voltage memory employed in ~Othe present invention.
FIGURES 7 and 8 show in logic diagram form implementations of portions of the present tuning system.
The color television receiver shown in FIGURE 1 15includes an antenna 1, an RF processing unit 3, a mixer 5 and a voltage controlled local oscillator 7 arranged to generate an IF signal. The IF signal is processed by an IF processing unit 9 and coupled to a sound processing unit 11, a picture processing unit 13 and a synchronization unit 2015. An audio response is generated by a speaker 17 in response to audio signals derived from the IF signal by - sound processing unit 11. Electron beams representing red, : green and blue information are generated by a picture tube 19 in response to picture signals derived from the IF signal : 25by picture processing unit 13. The electron beams are deflected in a raster portion to form an image in response to horizontal and vertical sycnhronization signals generated by a deflection unit 21 in response to horizontal and vertical synchronization pulses derived from the IF signal ~by synchronization unit 15.
Local oscillator 7 includes tuned circuit configura-tions (not shown) for each of a low VHF band covering channels 2 through 6, a high VHF band covering channels 7 through 13 and a UHF band covering channels 14 through 83.
~5The tuned circuits are selectively activated in response to VL (VHF Low), VH (VHF High) and U (U~F) band selection signals generated by a tuniny sys~em 23 which is constructed in accordance with the present invention. Each of the tuned circuit configurations includes an inductor and varactor 40diode (not shown). The varactor diode is reverse biased by . ,, ~ , - 6 -- RCA 73 ,145 a tuning voltage generated by ~unirg system 23 to exhibit a capacitance. The magnitude of the tllning voltage determir.es the capacitance of the tuned circuit and therehy the frequency 5 of local oscillator 23. The band cielection signals and the tuning voltage are also coupled to RF unit 3 to control selectively enable~ tuned circuit configurations similar to the ones in local oscillator 7 so as to track the tuning of local oscillator 7.
A portion of the I~ signal is coupled to an auto-matic fine tuning (AFT) discriminator 25 which generates an AFT signal having a magnitude representing the magnitude of the deviation of the frequency of a picture carrier component of the IF signal from lts nominal value,such as 45~75 MHz 15 in the United States of America.
~he AFT signal is utilized by tuning system 23 as will be described below to develop the tuning voltage. The IF signal is also coupled to an automatic gain control (AGC) unit 27 which generates 1~F and IF AGC signals for controlling the gains of the RF and IF stages, respectively, in accordance with the RF signal strength as manifested by the amplitude of the IF signal.
The portions of the receiver shown in FIGURE 1, 25 with the exception of tuning system 23, are conventional and may therefore comprise corresponding portions of a CTC-93 television chassis manufactured by RCA Corporation and described in detail in "RCA Service Data, File 1978 C-7".
Tuning system 23 is of the sweep/signal seeking type described above and includes a ramp voltage generator 29 and automatic channel detection circuits 31. I~hen a user depresses either an up push button (UPPB) 33 or a down push button (DNPB) 35, ramp voltage generator 29 generates a 35 ramp voltage which increases or decreases, respectively, as a function of time until automatic channel detection circuits 31 detect the presence of a channel acceptable for viewing.
A channel identification arrangement 36 displays the channel nul~ber of the first acceptable channel to which 40 tuning system 23 tunes the receiver after one of U~PB 33 or DNPB 35 are depressed and also the channel numbers of the `
115,6385 1 - RCA 73,145 channels passed to reach the first acceptable channel. In the latter manner, the user is made aware, during periods sin which an acceptable channel is sought, that tuning system 23 is operating. This is a desirable feature since acceptable channels, especially in the UHF band, may be considerably separated.
Channel identification arrangement 36 includes a tuning voltage boundary memory 37 having memory locations for storing binary signals representing boundary voltages having magnitudes correspording to the lowest and highest magnitude of a tuning voltage range corresponding to each of channels 2 through 83 to which ~uning system 23 may tune 15the receiver. Tuning voltage boundary memory 37 comprises a PROM (Programmable Read Only Memory) for reasons which will be explained below. ~ tuning voltage ~oundary memory address register 39 addresses memory locations of tuning voltage boundary PROM 37 under the control of a microprocessor 2041. Channel identification arrangement 36 also includes a channel number mernory 43, comprising a RO~I (Read Only ~lemory), having memory locations for storing binary signals represent-ing channel numbers 02 through 83 ~nd a channel number address register 45 for addressing the memory locations of memory 43 25under the control of microprocessor 41.
As memory locations of memory 37 are addressed,a digital-to-analog converter 47 generates the boundary voltages in response to the stored binary signals. When the tuning voltage is swept in the direction of increasing 30magnitu~es, the upper boundary voltages are compared to the tuning voltage by an UP voltage comparator 49. As long as an acceptable channel is not detected, whenever the magnitude of the tuning voltage exceeds the magnitude of an upper boundary voltage, an ADD (ADDress) C~ANGE signal is generated 36by UP comparator 49 and coupled through an ~ND gate 51, enabled by an UP .~A~IP signal, and an OR gate 53 to micro-processor 41. In response, microprocessor 41 causes tuning voltage address register 39 to address the memory location of tuning voltage boundary memory 37 corresponding to the 40 upper boundary voltage for the next higher channel and 1 -8- RCA 73,145 causes channel number address rec3istcr 45 to address the memory location of channel number memory 43 corresponding sto the next higher channel. I~hen the tuning voltage is swept in the direction of decreasing magnitudes, the lower boundary voltages are compared to the tuning voltage by a DN voltage comparator 55. As long as an acceptable channel is not detected, whenever the magnitude of the tuning lOvoltage falls below the magnitude of a lower boundary voltage, an ADD CHANGE signal is generated by DN comparator 55 and coupled through an AND gate 57, enabled by a DN R~lP signal, and O~ gate 53 to microprocessor 41. In response to the ADD CHANGE signal, microprocessor 41 causes tuning voltage 15boundary address register 39 to address the memory location of tuning voltage boundary memory 37 corresponding to the lower boundary voltage for the next lower channel and causes channel number address register 45 to address the memory location of channel number memory 43 corresponding to the 20channel number for the same next lower channel.
As the memory locations of channel number memory 43 are addressed, a two-digit channel number display unit S9, which may include two arrays of seven-segment light-emitting diodes each arranged in a conventional manner to display 25numberS~ displays the corresponding channel number. In addition, a band decoder 61 examines the channel number to determine which of the low VHF, hi~h VHF or UHF bands it a is in to generate the VL, VH and U band selection signals.
An acceptable channel is detected by examining the 30magnitude of the AFT signal, the average value of the hori-zontal synchronization pulses, and the magnitude of the AGC
signal coupled to the IF. For this purpose, automatic channel detection circuits 31 (see FIGVRE la) includes:
an AFT voltage comparator 63 for generating an AFT VALID
35signal when the magnitude of the AFT signal is between predetermined threshold values defining its control range;
an average detector 65 and average synchronization voltage comparator 67 for generating a SYNC VALID signal when the average voltage of the horizontal synchronization pulses is 40 within a predetermined range of values; and an AGC voltage I
`~s ---` 1156385 1 -9- RCA 73,145 comparator 69 for generating an AGC V~LID signal when the IF AGC is below a predetermined threshold.
5 The AFT signal is examined to determine the presence of an IF carrier. The carrier detlcted may be that of the souhd component of the IF signal rather than that of the picture carrier. Under these conditions, the average voltage of the synchronization pulses will not be within the pre-determined range established by average synchronization voltage comparator 67. Thus, the synchronization pulses are examined to prevent tuning system 23 from tuning the q receiver to a sowld carrier rather than a picture carrier.
The IF AGC signal is examined so that the receiver will not 15be tuned to carriers having insufficient signal strength to produce a picture without an undue amount of interference or "snow" as it is sometimes called in the picture. Since the amount of interference which is tolerable is dependent on the particular user's preferences, AGC comparator 69 may 20include a potentiometer or the like for adjusting the predetermined threshold voltage to which the IF AGC signal is compared. The IF AGC signal rather than the RF AGC signal is utilized since the RF AGC in conventional color television receivers remains substantially constant until the signal 25strength is appreciable.
The ~FT VALID signal is coupled to ramp voltage generator 29. The SYNC VALID and AGC VALID signals are combined by an AND gate 71 and coupled to microprocessor 41 but only after a predetermined time delay, determined by 30a delay unit 73, after the generation of the AFT VALI~ signal.
The predetermined time delay is selected to allow synchroni-zation unit 15 and AGC unit 27 to have time to settle after a carrier is detected.
Ramp voltage generator 29 (see FIGURE lb) includes 35a differential amplifier 75 and a capacitor 77 configured ~; as a voltage integrator. A number of transmission gates have their cc.nduction controlled in response to control signals generated by automatic channel detection circuits 31 and microprocessor 41 to start and stop the generation of the 40ramp tuning voltage and control the direction in which its :::
. ~
' -- l 156385 I -10- RCA 73,145 magnitude is changed.
An UP pulse is generated by microprocessor 41 when:
(1) a power up detector 76 detects that the receiver has been turned on by sensing the level of one of the receiver's power supply voltages;
(2) UPPB 33 is depressed;
In sweep systems, it may be desirable to display the channel number of channels passed to reach the acceptable channel so 30that users have a visible indication that the system is oper-ating and are therefore not annoyed by apparent lack of operation as an acceptable channel is sought.
A system for tuning a receiver to various channels 35includes a local oscillator means for generating a local oscillator signal appropriate for tuning the receiver to various channels in response to the magnitudes of a tuning voltage. The tuning voltage may be generated by apparatus -, including signal-seeking means for changing the magnitude of 40 the tuning voltage to automatically locate an acceptable . .
, 1 -4- RCA 73,145 channel or manual means for changing the magnitude of the tuning voltage until an acceptable channel is located by a suser. To display the channel numbers, the tuning system includes memory means, e.g., a PROM (Programmable Read Only Memory), including a plurality of memory locations each for storing binary signals representing a respective boundary voltage substantially equal to the tuning voltage at a fre-quency between the tuning voltage ranges of adjacent channels.
Address means is provided for addressing the memory locations.
As the memory locations are addressed, comparison means compares the tuning voltage to the boundary voltages. Control means causes the address means to address the memory location 15corresponding to the boundary voltage for the next channe~
until the magnitude of a predetermined one of the tuning voltage and the boundary voltage associated with an addressed memory exceeds the magnitude of the other one. Channel number display means displays the channel number of the 20channel associated with a presently addressed memory location.
By additional means, where it is desired to display channel numbers as the magnitude of the tuning voltage is being changed, the addressing of memory locations in sequence may occur during the interval in which the magnitude of the 25tuning voltage is being changed.
IN THE DRAWINGS:
FIGURES 1, la, lb and lc, which should be referred to concurrently, show partially in block diagram form and partially in schematic diagram form an embodiment of the 30present tuning system as it is employed in a television receiver.
FIGURE 2 shows tuning voltage characteristics of a voltage controlled tuner that may be employed in the present tuning system useful in facilitating an under-35standing of the present tuning system.
., 1 -5- RCA 73,145 of a boundary voltage memory emplo~ in the present tuning system.
FIGURES 4a, 4b and 4c show a flow chart indicating the operation of the arran~ement shown in FIGURES 1, la, lb and lc.
FIGURES 5 and 6 show in block diagram form apparatus for programming of a boundary voltage memory employed in ~Othe present invention.
FIGURES 7 and 8 show in logic diagram form implementations of portions of the present tuning system.
The color television receiver shown in FIGURE 1 15includes an antenna 1, an RF processing unit 3, a mixer 5 and a voltage controlled local oscillator 7 arranged to generate an IF signal. The IF signal is processed by an IF processing unit 9 and coupled to a sound processing unit 11, a picture processing unit 13 and a synchronization unit 2015. An audio response is generated by a speaker 17 in response to audio signals derived from the IF signal by - sound processing unit 11. Electron beams representing red, : green and blue information are generated by a picture tube 19 in response to picture signals derived from the IF signal : 25by picture processing unit 13. The electron beams are deflected in a raster portion to form an image in response to horizontal and vertical sycnhronization signals generated by a deflection unit 21 in response to horizontal and vertical synchronization pulses derived from the IF signal ~by synchronization unit 15.
Local oscillator 7 includes tuned circuit configura-tions (not shown) for each of a low VHF band covering channels 2 through 6, a high VHF band covering channels 7 through 13 and a UHF band covering channels 14 through 83.
~5The tuned circuits are selectively activated in response to VL (VHF Low), VH (VHF High) and U (U~F) band selection signals generated by a tuniny sys~em 23 which is constructed in accordance with the present invention. Each of the tuned circuit configurations includes an inductor and varactor 40diode (not shown). The varactor diode is reverse biased by . ,, ~ , - 6 -- RCA 73 ,145 a tuning voltage generated by ~unirg system 23 to exhibit a capacitance. The magnitude of the tllning voltage determir.es the capacitance of the tuned circuit and therehy the frequency 5 of local oscillator 23. The band cielection signals and the tuning voltage are also coupled to RF unit 3 to control selectively enable~ tuned circuit configurations similar to the ones in local oscillator 7 so as to track the tuning of local oscillator 7.
A portion of the I~ signal is coupled to an auto-matic fine tuning (AFT) discriminator 25 which generates an AFT signal having a magnitude representing the magnitude of the deviation of the frequency of a picture carrier component of the IF signal from lts nominal value,such as 45~75 MHz 15 in the United States of America.
~he AFT signal is utilized by tuning system 23 as will be described below to develop the tuning voltage. The IF signal is also coupled to an automatic gain control (AGC) unit 27 which generates 1~F and IF AGC signals for controlling the gains of the RF and IF stages, respectively, in accordance with the RF signal strength as manifested by the amplitude of the IF signal.
The portions of the receiver shown in FIGURE 1, 25 with the exception of tuning system 23, are conventional and may therefore comprise corresponding portions of a CTC-93 television chassis manufactured by RCA Corporation and described in detail in "RCA Service Data, File 1978 C-7".
Tuning system 23 is of the sweep/signal seeking type described above and includes a ramp voltage generator 29 and automatic channel detection circuits 31. I~hen a user depresses either an up push button (UPPB) 33 or a down push button (DNPB) 35, ramp voltage generator 29 generates a 35 ramp voltage which increases or decreases, respectively, as a function of time until automatic channel detection circuits 31 detect the presence of a channel acceptable for viewing.
A channel identification arrangement 36 displays the channel nul~ber of the first acceptable channel to which 40 tuning system 23 tunes the receiver after one of U~PB 33 or DNPB 35 are depressed and also the channel numbers of the `
115,6385 1 - RCA 73,145 channels passed to reach the first acceptable channel. In the latter manner, the user is made aware, during periods sin which an acceptable channel is sought, that tuning system 23 is operating. This is a desirable feature since acceptable channels, especially in the UHF band, may be considerably separated.
Channel identification arrangement 36 includes a tuning voltage boundary memory 37 having memory locations for storing binary signals representing boundary voltages having magnitudes correspording to the lowest and highest magnitude of a tuning voltage range corresponding to each of channels 2 through 83 to which ~uning system 23 may tune 15the receiver. Tuning voltage boundary memory 37 comprises a PROM (Programmable Read Only Memory) for reasons which will be explained below. ~ tuning voltage ~oundary memory address register 39 addresses memory locations of tuning voltage boundary PROM 37 under the control of a microprocessor 2041. Channel identification arrangement 36 also includes a channel number mernory 43, comprising a RO~I (Read Only ~lemory), having memory locations for storing binary signals represent-ing channel numbers 02 through 83 ~nd a channel number address register 45 for addressing the memory locations of memory 43 25under the control of microprocessor 41.
As memory locations of memory 37 are addressed,a digital-to-analog converter 47 generates the boundary voltages in response to the stored binary signals. When the tuning voltage is swept in the direction of increasing 30magnitu~es, the upper boundary voltages are compared to the tuning voltage by an UP voltage comparator 49. As long as an acceptable channel is not detected, whenever the magnitude of the tuning voltage exceeds the magnitude of an upper boundary voltage, an ADD (ADDress) C~ANGE signal is generated 36by UP comparator 49 and coupled through an ~ND gate 51, enabled by an UP .~A~IP signal, and an OR gate 53 to micro-processor 41. In response, microprocessor 41 causes tuning voltage address register 39 to address the memory location of tuning voltage boundary memory 37 corresponding to the 40 upper boundary voltage for the next higher channel and 1 -8- RCA 73,145 causes channel number address rec3istcr 45 to address the memory location of channel number memory 43 corresponding sto the next higher channel. I~hen the tuning voltage is swept in the direction of decreasing magnitudes, the lower boundary voltages are compared to the tuning voltage by a DN voltage comparator 55. As long as an acceptable channel is not detected, whenever the magnitude of the tuning lOvoltage falls below the magnitude of a lower boundary voltage, an ADD CHANGE signal is generated by DN comparator 55 and coupled through an AND gate 57, enabled by a DN R~lP signal, and O~ gate 53 to microprocessor 41. In response to the ADD CHANGE signal, microprocessor 41 causes tuning voltage 15boundary address register 39 to address the memory location of tuning voltage boundary memory 37 corresponding to the lower boundary voltage for the next lower channel and causes channel number address register 45 to address the memory location of channel number memory 43 corresponding to the 20channel number for the same next lower channel.
As the memory locations of channel number memory 43 are addressed, a two-digit channel number display unit S9, which may include two arrays of seven-segment light-emitting diodes each arranged in a conventional manner to display 25numberS~ displays the corresponding channel number. In addition, a band decoder 61 examines the channel number to determine which of the low VHF, hi~h VHF or UHF bands it a is in to generate the VL, VH and U band selection signals.
An acceptable channel is detected by examining the 30magnitude of the AFT signal, the average value of the hori-zontal synchronization pulses, and the magnitude of the AGC
signal coupled to the IF. For this purpose, automatic channel detection circuits 31 (see FIGVRE la) includes:
an AFT voltage comparator 63 for generating an AFT VALID
35signal when the magnitude of the AFT signal is between predetermined threshold values defining its control range;
an average detector 65 and average synchronization voltage comparator 67 for generating a SYNC VALID signal when the average voltage of the horizontal synchronization pulses is 40 within a predetermined range of values; and an AGC voltage I
`~s ---` 1156385 1 -9- RCA 73,145 comparator 69 for generating an AGC V~LID signal when the IF AGC is below a predetermined threshold.
5 The AFT signal is examined to determine the presence of an IF carrier. The carrier detlcted may be that of the souhd component of the IF signal rather than that of the picture carrier. Under these conditions, the average voltage of the synchronization pulses will not be within the pre-determined range established by average synchronization voltage comparator 67. Thus, the synchronization pulses are examined to prevent tuning system 23 from tuning the q receiver to a sowld carrier rather than a picture carrier.
The IF AGC signal is examined so that the receiver will not 15be tuned to carriers having insufficient signal strength to produce a picture without an undue amount of interference or "snow" as it is sometimes called in the picture. Since the amount of interference which is tolerable is dependent on the particular user's preferences, AGC comparator 69 may 20include a potentiometer or the like for adjusting the predetermined threshold voltage to which the IF AGC signal is compared. The IF AGC signal rather than the RF AGC signal is utilized since the RF AGC in conventional color television receivers remains substantially constant until the signal 25strength is appreciable.
The ~FT VALID signal is coupled to ramp voltage generator 29. The SYNC VALID and AGC VALID signals are combined by an AND gate 71 and coupled to microprocessor 41 but only after a predetermined time delay, determined by 30a delay unit 73, after the generation of the AFT VALI~ signal.
The predetermined time delay is selected to allow synchroni-zation unit 15 and AGC unit 27 to have time to settle after a carrier is detected.
Ramp voltage generator 29 (see FIGURE lb) includes 35a differential amplifier 75 and a capacitor 77 configured ~; as a voltage integrator. A number of transmission gates have their cc.nduction controlled in response to control signals generated by automatic channel detection circuits 31 and microprocessor 41 to start and stop the generation of the 40ramp tuning voltage and control the direction in which its :::
. ~
' -- l 156385 I -10- RCA 73,145 magnitude is changed.
An UP pulse is generated by microprocessor 41 when:
(1) a power up detector 76 detects that the receiver has been turned on by sensing the level of one of the receiver's power supply voltages;
(2) UPPB 33 is depressed;
(3) an AFT VALID signal has not been generated during an upward search; and
(4) an AFT VALID signal has been generated but SYNC VALID and AGC VALID signals have not been generated during an upward search.
A DN pulse is generated when:
(1) DNPB 35 is depressed;
(2) an ~FT VALID signal has not been generated during a downward search; and (3) an AFT VALID signal has been generated but SYNC VALID and AGC VALID signals have not been generated 20during a downward search.
When either an UP pulse or a DN pulse is generated, a START R~lP pulse is also generated by microprocessor 41.
The START R~IP pulse sets a set-reset flip-flop (S-R FF) 78 thereby causing thc conduction of a transmission 25gate 79. The UP pulse is coupled through an AND gate 81, enabled by the simultaneous presence of the START RA~IP pulse, to the S input of a S-R FF 83. As a result, S-R FF 83 is I set and thereby an UP RAMP signal is generated. The UP RAMP
signal causes the conduction of a transmission gate 85. By 30virtue of the conduction of transmission gate 79 and 85, a positive voltage V is coupled to the noninverting (+) input of differential amplifier 75 through a resistor 87 and the magnitude of the tuning voltage is caused to increase or ramp up. The DN pulse is coupled through an AND gate 89, 35enabled by the simultaneous presence of the START R~lP pulse, to the R input of S-R FF 83. As a result, S-R FF 83 is reset and a DN RAMP signal is thereby generated. The DN RP~1P
signal causes the conduction of transmission gate 91. By virtue of the conduction of transmission gates 79 and 91, ~ positive voltage V is coupled to the inverting (-) input of ~' ' ~g . - 1156385 RCA 73,145 differential amplifier 75 through a resistor 93 and the magnitude of t}c tuning voltage is caused to decrease or
A DN pulse is generated when:
(1) DNPB 35 is depressed;
(2) an ~FT VALID signal has not been generated during a downward search; and (3) an AFT VALID signal has been generated but SYNC VALID and AGC VALID signals have not been generated 20during a downward search.
When either an UP pulse or a DN pulse is generated, a START R~lP pulse is also generated by microprocessor 41.
The START R~IP pulse sets a set-reset flip-flop (S-R FF) 78 thereby causing thc conduction of a transmission 25gate 79. The UP pulse is coupled through an AND gate 81, enabled by the simultaneous presence of the START RA~IP pulse, to the S input of a S-R FF 83. As a result, S-R FF 83 is I set and thereby an UP RAMP signal is generated. The UP RAMP
signal causes the conduction of a transmission gate 85. By 30virtue of the conduction of transmission gate 79 and 85, a positive voltage V is coupled to the noninverting (+) input of differential amplifier 75 through a resistor 87 and the magnitude of the tuning voltage is caused to increase or ramp up. The DN pulse is coupled through an AND gate 89, 35enabled by the simultaneous presence of the START R~lP pulse, to the R input of S-R FF 83. As a result, S-R FF 83 is reset and a DN RAMP signal is thereby generated. The DN RP~1P
signal causes the conduction of transmission gate 91. By virtue of the conduction of transmission gates 79 and 91, ~ positive voltage V is coupled to the inverting (-) input of ~' ' ~g . - 1156385 RCA 73,145 differential amplifier 75 through a resistor 93 and the magnitude of t}c tuning voltage is caused to decrease or
5 ramp down.
The UP RAÇlP and DN RAMP signals are coupled to AND
gates 51 and 53, respectively, to ~nable the appropriate one of UP voltage comparator 49 or DN voltage comparator 55 and to microprocessor 41.
The tuning voltage versus frequency characteristics for television receivers employing varactor diodes over the entire VHF and UHE~ tuning range is not continuous and includes overlapping portions as is indicated in FIGURE 2.
That is, the magnitude of the tuning voltage for channel 6 15 is higher than the magnitude of the tuning voltage for channel 7, and the magnitude of the tuning voltage for channel 13 is higher than the magnitude of the tuning voltage for channel 14. Accordingly, it is desirable to cause the magnitude of the tuning voltage to be rapidly changed from 20 the magnitude corresponding to the end of one band to the magnitude-corresponding to the beginning of the next band in both the upward and downward ramping directions. A
fast UP/DN control unit 95 is responsive to sig~als repre-senting channels 2, 6, 7, 13, 14 and 83, i.e., the channels 25 at the boundaries of the various bands, genera~ed by band decoder 61 to generate a FAST DN signal in the upward ramping direction and a FAST UP signal in the downward ramping direction when the end of a band is reached.
Either of the FAST UP or FAST DN signals cause an 30 OR gate 97 to generate a STOP RA~IP signal. The STOP RAMP
signal resets S-R FF 78 and causes transmission gate 79 to be rendered nonconductive. The FAST DN signal causes a transmission gate 99 to be rendered conductive, thereby coupling positive voltage V to the inverting (-) input of 35 differential amplifier 75 through a resistor 101 having a lower resistance value than resistors 87 and 93 (used for normal ramping). As a result, in the upward ramping direc-tion, the magnitude of the tuning voltage is relatively rapidly decreased between bands. The FAST UP signal causes 40 a transmission gate 103 to be rendered conductive, thereby i~
1 -12- RCA 73,145 coupling a positive voltage V to the noninverting (+) input of differential ~mplifier 75 through a resistor 105 ha~ing a 510wer resistance than resistors 37 and ~3. As a result, in the downward ramping direction, the magnitude of the tuning voltage is relatively rapidly increased between bands.
The UP R~`IP and DN R~P signals are coupled to AND
gates 51 and 53, respecti~ely, to enable the appropriate one lOof UP voltage comparator 49 or DN voltage comparator 55, and to microprocessor 41.
When the magnitude of the tuning vol.aye corre-I sponding to the beginning of the ne:~t band is reached by fast ramping in either the downward or upward direction, fast 15UP/DN detector 95 terminates the appropriate one of the FASTUP or FAST DN signals.
During the fast ramping intervals, tuning system 23 is disabled from responding to either the ADD CIIAMG~ or the AFT VALID signals by means of NOR gate 107, AND gate 109 20and AND gate 111 since the tuniny voltage generated during these intervals changes in the wrong direction.
During the normal ramping intervals, if an AFT VALID
signal is generated, a STOP RAMP signal is generated by OR
gate 97. In response, S-R FF 7~ is reset and transmission 25gate 79 is rendered nonconductive to terminate ramping.
In addition, in response to the AFT VALID signal, transmission gates 113 and 115 are rendered conductive, thereby coupling a portion of the positive voltage V to the inverting (-) input of differential amplifier 75 as a reference voltage 30and a portion of the AFT discriminator signal to the non-inverting (+) input of differential amplifier 75. Since any change in the tuning voltage, such as for example may be caused by the lea]cage of charge from capacitor 77, causes a corresponding change in the AFT signal applied to differ-35ential amplifier 75, the tuning voltage is maintainedsubstantially constant.
~ icroprocessor 41 controls the operation of tuning system 23 primarily by controlling the addressing of tuning --- voltage boundary memory 37 and channel number memory 43.
40Microprocessor 41 (see FIGURE lc) includes input ports for -` I 156385 1 -13- RCA 73,145 receiving various input signals generated within tuning system 23, a central processing unit (CPU) 119 for evaluating the in-put signals, and output ports 121 for coupling output signals sgenerated by CPU 119 in response to the input signals to var-ious portions of tuning system 23. The output signals gene-rated by CPU 119 are determined by a program permanently stored in memory locations of a R~q (Random Access ~lemory) 123 and addressed by a R~1 address register 125 under the control oof CPU 119 as the program is executed.
Before describing the program stored in R~l 123, it will be helpful to examine the arrangement of'the memory loca-tions of tuning voltage boundary memory 37 as shown in FIGURE
3. Within a band, the boundary voltages stored in memory 37 have magnitudes substantially equal to the magnitudes of the tuning voltage at frequencies midway between the nominal fre-quencies of the picture carriers of adjacent channels. As a result, each of tl-ese boundary voltages represents the end of the tuning voltage range for one channel and the beginning of 20the tunin~ voltage range for the next channel. Thus, for example, in the low VHF band the boundary voltages indicated by 2 , 3 , 4 and 5 correspond to the highest magnitude of tuning voltage range for channels 2, 3, 4 and 5, respectively, as well as the lowest magnitude of the tuning voltage range 25for channels 3, 4, 5 and 6, respectively, and are therefore also identified by 3 , 4 , 5 and 6 , respectively. In addi-' tion, a boundary voltage having a magnitude substantially e~ual to the lowest magnitude of the tuning voltage for the lowest channel in each band, e.g., 2 , and a boundary voltage 30having a magnitude substantially equal to the highest magni-tude of the tuning range for the highest channel in each band, e.g., 6+, are stored in memory locations of memory 37. The boundary voltages and channel numbers are stored in consecu-tive order in memories 37 and 43, respectively. As indicated 35in FIGURE 3, the memory locations of memories 37 and 43 are addressed in continuous circular or "wrap around" fashion in both ramping directions.
The flow chart of the program stored in RAM 123 for controlling tuning system 23 is indicated in FIGURES 4a, 4b 40and 4c. Since the program stored in R~M 123 is utilized _., ., . ._ . , .
-`` I 1S6385 1 -14- RCA 73,145 primarily to control the addressing of memories 37 and 43, the flow chart of FIGURES 4a, 4b and 4c does not indicate certain operations of tuning system 23, such as fast up and sdown ramping, which are controlled by portions of tuning system 23 outside of microprocessor 41. However, where considered helpful in facilitating an understanding in the overall operation of tuning system 23, certain operations of tuning system 23, such as the generation of the STOP R~lP
10signal, although controlled by portions of tuning system 23 outside of microprocessor 41, are included in the flow chart shown in FIGURES 4a, 4b and 4c.
¦ When the receiver is turned on, the memory locations of memory 43 corresponding to channel 2 and the 15memory locations of memory 37 corresponding to the highest magnitude in the tuning range for channel 2, i.e., 2+, are addressed and an upward search for the presence of an acceptable picture carrier for channcl 2 is ir~itiated ~program ste~s 00 through 10). As sc-,on as an~ carrier is 20detected, as indicated by the presence of an AFT VALID
signal, a STOP RANP signal is generated. If the carrier is 3 a picture carrier and is of sufficient amplitude, as indicated by the presence of both the SYNC VALID and AGC
VALID signals, channel 2 is an acceptable channel and the 25tuning sequence is completed. However, if the carrier is not a picture carrier, as indicated by the absence of a SYNC VALID signal, or the carrier detected has insufficient amplitude, indicated by the absen~e of an AGC VALID signal, the upward search is reinitiated until a picture carrier 30having a sufficient amplitude is located. ~s long as no carrier is detected, as indicated by the absence of an AFT
VALID signal, the me~.ory locations of memories 43 and 37 are successively addressed in the order of increasing channel numbers whenever the magnitude of the tuning voltage exceeds 35the magnitude of a presently generated upper boundary voltage and the magnitude of the tuning voltage is thereafter increased in iterative fashion (program steps 11 through 17).
In this operation, whenever the channel number of the first channel in the next band (in the order of increasing channel .A 40numbers) is reached, the address for tuning voltage boundary : . , .
..
1 1 5638~ `
-15- RCA 73,145 memory 37 is increas~d by one so as to skip over the lower boundary voltage for the lowest channel in the next band 5 (program steps 15 and 16). In other words, during upward searches the lower boundary volt:age (7, 14 and 2 for the lowest number channels 7, 14 and 2) in each band is skipped. The operation of addressing successive memory locations of memories 43 and 37 and causing the magnitude 10 Of the tuning voltage to increase continues until a carrier is detected. When a carrier is detected, if it is a picture carrier and its amplitude is sufficient, the tuning sequence is completed (program steps 18, 19 and 203. If the carrier detected is not a picture carrier or its 15 amplitude is not sufficient, the search for another carrier is continued.
Once a tuning sequence has been completed, i.e., an acceptable channel has been located, no action is taken unless UPPB 33 or DNPB 35 is depressed causing microprocessor 20 41 to generate an UP signal or a DN signal, respectively (program step 21). If the UPPB 33 has been depressed and tuning system 23 was previously set to ramp in the upward direction, as indicated by the UP ~AMP signal (program step 22), an upward search, as described above, is initiated.
25 If UPPB 33 has been depressed and tuning system 23 was previously set to ramp in the downward directiori, as indicated by the DN RAt~P signal (program step 22), the address for tuning voltage boundary memory 37 is increased by one (program step 23). If the latter were not done, the boundary 30 voltage then generated would be the lower boundary voltage for the presently tuned channel rather than the upper boundary voltage. As a result, the boundary voltages generated during the subsequent upward search would be out of step with the generated channel numbers.
If DNP~ 35 is depressed, a downward search is initiated. The downward search sequence, indicated by the flow chart shown in FIGU~E 4c, is similar to the upward search sequence shown in FIGURES 4a and 4b and will not be described in detail. ~owever, it should be noted if a ,.
40 downward search is initiated after the termination of an als63ss 1 - 16 - RCA 73,145 upward search, the address for tunin(3 volt~ge boundary memory 37 is decreased by one so as to coordinate the ~oundary voltages and channel numbers generated during the subsequent search (program steps 24 and 25). In addition, boundary voltages 83+, 13+ and 6 for channels 83, 13 and 6, respectively, are skipped during a downward search by decreasing the address for tuning voltage boundary memory 37 when the channel number is 83, 13 or 6 (program steps 26 and 27).
Since the voltages stored in memory 37 are only utilized for determining the channel numbers to be displayed, they need not be as precise as voltages stored in a memory of a tuning system of the voltage synthesizer type which are utilized for tuning a receiver. Nevertheless, at the present state of the art, it is difficult to specify the tuning voltage characteristics for a large number of varactor controlled tuners within predetermined limits even for displaying channel numbers.
~herefore, it i5 desirable that the receiver manufacturer program the information in memory 37 so that the stored b~undary voltages correspond to the tuning voltage character-istics of the particular local oscillator and RF portion for which they are intended. For this purpose, it is desirable that memory 37 be a pRorl. The binary signals representing the boundary voltages may be entered in memory 37 utiliziny the arrangement shown in FIGURE 5. In the arrangement of FIGUR~ 5, the output of D/A converter 47 is co~pled to the tuning voltage input of ~F unit 3 and local oscillator 7. The appropriate band selection signals are externally generated by a band selection control unit 501.
Binary signals representing the address of the memory locations of memory 37 are externa]ly generated by an address register 502. In addition, test equipment including a frequency synthesizer 503, an up,/down counter 504, a frequency counter 505 and a write push button 507 is connected to various portions of the receiver as shown in FIG~E 5.
r~ith this arrangement~ the ~ollowing setup procedures may be employed to store the binary signals representing the boundary voltages.
. '' '' ' , ~ .
- ~ i `` ` 1156385 1 -17- RCA 73,145 (1) f~ddress the memory location in which the boundary voltage is to be stored.
(2) Set frequency synthexizer 503 to the frequency corresponding to the boundary voltage.
(3) Change the contents of up/down counter 504 until the desired IF (45.75 ~Hz) is indicated by frequency counter 505.
(4) Depress write push button 507 to enter the binary signals generated by up/down counter 504.
In this arrangement since D/~ converter 47 employed during normal operation is employed during setup, the errors of D/A converter 47 are accounted for by the set-up procedure.
Another arrangement for programming memory 47 is 15shown in FIGURE 6. With this arrangement, the following set-up procedure may be employed by means of address register 601.
(1) Address the memory location in which the boundary voltage is to be stored.
(2) Set frequency synthesizer 602 to the frequency corresponding to the boundary voltage.
, (3) Adjust variable voltage source 603 until ; frequency counter 604 indicates the desired IF (45.75 MHz).
(4) Change the contents of up/down counter 604 25until a comparator 605 indicates a state change by means of, for example, a lamp 606 coupled to its output.
(5) Press write push button 607 to enter the binary i signals generated by up/down counter 604.
If comparators 49 and 55 are included within a 30single integrated circuit, their offset voltage character-istics will tend to be similar. Therefore, it may be desirable to employ one of voltage comparators 49 and SS
as comparator 605 so that their offset voltage character-istics are accounted for during setup.
FIGURE 7 shows a logic implementation of fast up/down control unit 95 (s~lown in block diagram form in FIGURE 1). During an upward search, whenever binary signals representing the channel number of the last channel in a band, i.e., channel number 06, 13 or 83, are generated by channel number memory 43 (of the arrangement shown in FIGURE 1), .. :.. . . .. .. .. . .
, - als63ss 1 -18- RCA 73,145 band decoder 61 (of the arrangemellt shown in FIGURE 1) generates a signal representing the occurrence. In response, san OR gate 701 couples a high level logic signal to the S
(Set) inputs of D (Data) FFs 703 and 705 thereby causinq low level logic signals to be developed at their Q outputs.
As soon as binary signals representing the channel number of the first channel in the next band, i.e., channel number 1007, 14 or 02, are generated, a high level FAST DN ENABLE
logic signal is generated by the logic configuration including logic gates 707, 709, 711, 713, 715 and 717. At the same time, OR gate 717 generates a high level logic signal which triggers a monostable multivibrator (~IS:lV) 719. ~1S~ 719 15generates a positive-going FAST DN TIr1E pulse which has a duration sufficiently long for the fast down ramping interval to be completed. In response to the UP R~tlP signal generated by S-R FF 83 (of the arrangement shown in FIGURE lb) and : the FAST DN ENABLE and FAST DN TIllE sisnals, an AWD gate 721 20generates a high level FAST DN signal.
~ The FAST DN signal terminates when the tuning voltage has a magnitude substantially equal to the lowest magnitude of the tuning voltage range of the lowest channel in the next band. A comparator 72~ determines when the tuning 25voltage has a magnitude corresponding to the beginning, in the upward direction, of the tuning voltage range for channel 7. When the beginning of the tunillg voltage range for ¦ channel 7 is reached, a high lcvel logic signal is coupled to the C (Cloc~) input of D FF 703. As a result, since the 30D input of D FF 703 is coupled to ~ignal ground, D FF 703 is reset causing a high level logic signal to be developed at its Q output. In response, by means of logic gates 707, 709 and 711, the FAST D~l ENABLE signal becomes a low logic level, and by means of AND gate 721, the high level FAST DN
35signal is terminated (i.e., becomes a low logic level).
Assuming that the magnitudes at the beginnings of the tuning voltage ranges, in the upward scanning direction, for channels 2 and 14 are approximately the same (as shown in FIGURE 2), a single comparator 725 may be used 40to determine when the tuning voltage has a magnitude ~.
115638~ ` `
1 -19- RCA 73,145 correspondin-3 to t~le beginning of the tuning voltage ranges for channels 2 an(l 14. When the b~g~t-niny~; o~ the tuning svoltage ranqe~ for channels 2 and 7 are reached, D FF 705 is reset and by means of logic gates 713, 715, 709 and 711 the FAST DN ENABLE signal becomes a low logic level, and by means of AND ~ate 711 the high level FAST DN signal is terminated (i.e., becomes a low logic level).
~uring a downward search, by means of OR gate 717 a D FF 727 is set when the binary signals representing the lowest channel number, i.e., channel number 02, 07 or 14, in a band are generated. As soon as binary signals repre-senting the first channel number in the next band, i.e., 15channel number 83, 06 or 13, are generated, an AND gate 729 generates a high logic level FAST UP ENABLE signal. At the same time, MS.`5V 731 is tirggered by means of OR gate 701 to generate a high logic level FAST UP TI~lE pulse which has a duration sufficiently long for fast down ramping to be 20completed. An AND gate 733, in response to the FAST UP
ENABLE signal, FAST UP TIrlE pulse and DN RA~P signal, generates a high level FAST UP signal. When the tuning voltage has a magnitude correspondin~J to the }~eginning of the tuning ranges for the highest channels in the next bands, 25aSsuming that these magnitudes are approximately the same (as shown in FIGURE 2), a comparator 735 causes D FF 727 to be reset. As a result, the high logic level FAST UP
EN~BLE: and FAST UP signals are terminated.
While the threshold voltages for comparators 723, 30725 and 735 of the implementation of control unit 95 shown in FIGURE 7 are derived from a resistive divider 736,it is noted that they ma~ be derived by addressing corresponding memory locations of T~l boundary memory 37 during the fast up and fast down ramping intervals.
An implementation of AFT comparator 63 shown in block diagram form in FIGI~RE la is shown in FIGURE 8. AFT
comparator 63 includes a comparator 801 for detecting a pre-determined voltage corresponding to the positlve "hump" of the AFT voltage and a comparator 803 for detecting a pre-40determined voltage corresponding to the negative "hump" of `` ll56385 1 - 20 - RCA 73,145 the AFT voltage. The remaining logic portion of AFT com-parator 63 detects the sequence of the "humps" of the AFT
voltage to determine whether the AFT voltage is in its control range,i.e., the portion hetween the humps, thereby indicating that a carrier has a fre-~-uency near enough to the desired IF ~45.75 ~z) so that normal ramping may be stopped. For this purpose, the logic portion of AFT comparator 63 is arranged so that 10 when the frequency of the local oscillator is being increased and, as a result, the frequency of the IF signal is being decreased, the negative hump is detected before the positive hump and that when the frequency of the local oscillator signal is being decreased and, as a result, the frequency 15 of the IF signal is being increased, the positive hump is detected before the negative hump. ~hen the second of the two humps is detected, an AFT VALID signal is generated.
The logic portion of AFT comparator 63 is arranged so that after a carrier has been detected, the first hump detected 20 thereafter is disregarded in a subsequent sequence detection operation. This is done since, in this situa~ion, when ramp-ing is again initiated, the first hump detected is associated with the previously detected carrier rather than the next one.
The logic portion of AFT comparator 63 includes four 25 D FFs 805, 807, 809 and 811 which are reset in response to a START R~`lP signal. Assuming that the ramping direction is downward, i.e., the frequency of the IF signal is increasing, the first hump detected will be the negative hump associated with the previously detected carrier. Accordingly, D FF 805 30 is set and an AND gate 813 is enabled. The next hump detected will be the positive hump associated with the next carrier. Accordingly, D FF 807 is set and AND gate 815 is enabled. In addition, since AND gate 813 was already enabled, D FF 80~ is set. However, since an AND gate 817 is disabled due to the absence of a high logic level UP RA~P
signal, an AFT VALID signal is not generated by an OR gate 819.
The next hump detected will be the negative hump 40 associated with the next carrier. Accordingly, since AND
gate 815 was already enabled by set D FF 80/, D FF 811 is set.
;~ -1 -21- RC~ 73,145 Since an AND gate 821 is enabled by a high logic level DN ~P
signal, an A~T V~LID signal is generated ~y O~ gate 819.
Thus, in the downward ramping direction, the first negative hump is disregarded and an AFT VALID signal is generated after a positive hump--neyative hump sequence.
In the upward ramping direction, the logic portion of AFT
comparator 63 operates in a similar fashion to disregard lOthe first positive hump and generate an AFT VALID signal after a negative hump--positive hump sequence.
Since the portions of automatic channel detection circuit 31 for evaluating the synchronization and AGC signals are well known in the signal seeking art, no detailed 15description of these components of the present system will be provided.
While automatic channel detection circuits 31 have been described with reference to the specific arrangement shown in FIGURE la, it will be appreciated that other 20arrangements for the same purpose, such as for example, the arrangement disclosed in U.S. Patent Number 3,632,864, may be employed. Furthermore, whi]e the present tuning and : channel number identification system has been described in terms of an automatic signal seeking system, the channel 25identification apparatus may include tuning systems in which a ramp or ramp-like tuning voltaye is generated in response to manual control, by means of a potentiometer arrangement or the like, until an acceptable channel is located. These and other modifications are intended to be included within 30the scope of the present invention as defined by the fo~lowing c~aims.
~0 ',~ J
The UP RAÇlP and DN RAMP signals are coupled to AND
gates 51 and 53, respectively, to ~nable the appropriate one of UP voltage comparator 49 or DN voltage comparator 55 and to microprocessor 41.
The tuning voltage versus frequency characteristics for television receivers employing varactor diodes over the entire VHF and UHE~ tuning range is not continuous and includes overlapping portions as is indicated in FIGURE 2.
That is, the magnitude of the tuning voltage for channel 6 15 is higher than the magnitude of the tuning voltage for channel 7, and the magnitude of the tuning voltage for channel 13 is higher than the magnitude of the tuning voltage for channel 14. Accordingly, it is desirable to cause the magnitude of the tuning voltage to be rapidly changed from 20 the magnitude corresponding to the end of one band to the magnitude-corresponding to the beginning of the next band in both the upward and downward ramping directions. A
fast UP/DN control unit 95 is responsive to sig~als repre-senting channels 2, 6, 7, 13, 14 and 83, i.e., the channels 25 at the boundaries of the various bands, genera~ed by band decoder 61 to generate a FAST DN signal in the upward ramping direction and a FAST UP signal in the downward ramping direction when the end of a band is reached.
Either of the FAST UP or FAST DN signals cause an 30 OR gate 97 to generate a STOP RA~IP signal. The STOP RAMP
signal resets S-R FF 78 and causes transmission gate 79 to be rendered nonconductive. The FAST DN signal causes a transmission gate 99 to be rendered conductive, thereby coupling positive voltage V to the inverting (-) input of 35 differential amplifier 75 through a resistor 101 having a lower resistance value than resistors 87 and 93 (used for normal ramping). As a result, in the upward ramping direc-tion, the magnitude of the tuning voltage is relatively rapidly decreased between bands. The FAST UP signal causes 40 a transmission gate 103 to be rendered conductive, thereby i~
1 -12- RCA 73,145 coupling a positive voltage V to the noninverting (+) input of differential ~mplifier 75 through a resistor 105 ha~ing a 510wer resistance than resistors 37 and ~3. As a result, in the downward ramping direction, the magnitude of the tuning voltage is relatively rapidly increased between bands.
The UP R~`IP and DN R~P signals are coupled to AND
gates 51 and 53, respecti~ely, to enable the appropriate one lOof UP voltage comparator 49 or DN voltage comparator 55, and to microprocessor 41.
When the magnitude of the tuning vol.aye corre-I sponding to the beginning of the ne:~t band is reached by fast ramping in either the downward or upward direction, fast 15UP/DN detector 95 terminates the appropriate one of the FASTUP or FAST DN signals.
During the fast ramping intervals, tuning system 23 is disabled from responding to either the ADD CIIAMG~ or the AFT VALID signals by means of NOR gate 107, AND gate 109 20and AND gate 111 since the tuniny voltage generated during these intervals changes in the wrong direction.
During the normal ramping intervals, if an AFT VALID
signal is generated, a STOP RAMP signal is generated by OR
gate 97. In response, S-R FF 7~ is reset and transmission 25gate 79 is rendered nonconductive to terminate ramping.
In addition, in response to the AFT VALID signal, transmission gates 113 and 115 are rendered conductive, thereby coupling a portion of the positive voltage V to the inverting (-) input of differential amplifier 75 as a reference voltage 30and a portion of the AFT discriminator signal to the non-inverting (+) input of differential amplifier 75. Since any change in the tuning voltage, such as for example may be caused by the lea]cage of charge from capacitor 77, causes a corresponding change in the AFT signal applied to differ-35ential amplifier 75, the tuning voltage is maintainedsubstantially constant.
~ icroprocessor 41 controls the operation of tuning system 23 primarily by controlling the addressing of tuning --- voltage boundary memory 37 and channel number memory 43.
40Microprocessor 41 (see FIGURE lc) includes input ports for -` I 156385 1 -13- RCA 73,145 receiving various input signals generated within tuning system 23, a central processing unit (CPU) 119 for evaluating the in-put signals, and output ports 121 for coupling output signals sgenerated by CPU 119 in response to the input signals to var-ious portions of tuning system 23. The output signals gene-rated by CPU 119 are determined by a program permanently stored in memory locations of a R~q (Random Access ~lemory) 123 and addressed by a R~1 address register 125 under the control oof CPU 119 as the program is executed.
Before describing the program stored in R~l 123, it will be helpful to examine the arrangement of'the memory loca-tions of tuning voltage boundary memory 37 as shown in FIGURE
3. Within a band, the boundary voltages stored in memory 37 have magnitudes substantially equal to the magnitudes of the tuning voltage at frequencies midway between the nominal fre-quencies of the picture carriers of adjacent channels. As a result, each of tl-ese boundary voltages represents the end of the tuning voltage range for one channel and the beginning of 20the tunin~ voltage range for the next channel. Thus, for example, in the low VHF band the boundary voltages indicated by 2 , 3 , 4 and 5 correspond to the highest magnitude of tuning voltage range for channels 2, 3, 4 and 5, respectively, as well as the lowest magnitude of the tuning voltage range 25for channels 3, 4, 5 and 6, respectively, and are therefore also identified by 3 , 4 , 5 and 6 , respectively. In addi-' tion, a boundary voltage having a magnitude substantially e~ual to the lowest magnitude of the tuning voltage for the lowest channel in each band, e.g., 2 , and a boundary voltage 30having a magnitude substantially equal to the highest magni-tude of the tuning range for the highest channel in each band, e.g., 6+, are stored in memory locations of memory 37. The boundary voltages and channel numbers are stored in consecu-tive order in memories 37 and 43, respectively. As indicated 35in FIGURE 3, the memory locations of memories 37 and 43 are addressed in continuous circular or "wrap around" fashion in both ramping directions.
The flow chart of the program stored in RAM 123 for controlling tuning system 23 is indicated in FIGURES 4a, 4b 40and 4c. Since the program stored in R~M 123 is utilized _., ., . ._ . , .
-`` I 1S6385 1 -14- RCA 73,145 primarily to control the addressing of memories 37 and 43, the flow chart of FIGURES 4a, 4b and 4c does not indicate certain operations of tuning system 23, such as fast up and sdown ramping, which are controlled by portions of tuning system 23 outside of microprocessor 41. However, where considered helpful in facilitating an understanding in the overall operation of tuning system 23, certain operations of tuning system 23, such as the generation of the STOP R~lP
10signal, although controlled by portions of tuning system 23 outside of microprocessor 41, are included in the flow chart shown in FIGURES 4a, 4b and 4c.
¦ When the receiver is turned on, the memory locations of memory 43 corresponding to channel 2 and the 15memory locations of memory 37 corresponding to the highest magnitude in the tuning range for channel 2, i.e., 2+, are addressed and an upward search for the presence of an acceptable picture carrier for channcl 2 is ir~itiated ~program ste~s 00 through 10). As sc-,on as an~ carrier is 20detected, as indicated by the presence of an AFT VALID
signal, a STOP RANP signal is generated. If the carrier is 3 a picture carrier and is of sufficient amplitude, as indicated by the presence of both the SYNC VALID and AGC
VALID signals, channel 2 is an acceptable channel and the 25tuning sequence is completed. However, if the carrier is not a picture carrier, as indicated by the absence of a SYNC VALID signal, or the carrier detected has insufficient amplitude, indicated by the absen~e of an AGC VALID signal, the upward search is reinitiated until a picture carrier 30having a sufficient amplitude is located. ~s long as no carrier is detected, as indicated by the absence of an AFT
VALID signal, the me~.ory locations of memories 43 and 37 are successively addressed in the order of increasing channel numbers whenever the magnitude of the tuning voltage exceeds 35the magnitude of a presently generated upper boundary voltage and the magnitude of the tuning voltage is thereafter increased in iterative fashion (program steps 11 through 17).
In this operation, whenever the channel number of the first channel in the next band (in the order of increasing channel .A 40numbers) is reached, the address for tuning voltage boundary : . , .
..
1 1 5638~ `
-15- RCA 73,145 memory 37 is increas~d by one so as to skip over the lower boundary voltage for the lowest channel in the next band 5 (program steps 15 and 16). In other words, during upward searches the lower boundary volt:age (7, 14 and 2 for the lowest number channels 7, 14 and 2) in each band is skipped. The operation of addressing successive memory locations of memories 43 and 37 and causing the magnitude 10 Of the tuning voltage to increase continues until a carrier is detected. When a carrier is detected, if it is a picture carrier and its amplitude is sufficient, the tuning sequence is completed (program steps 18, 19 and 203. If the carrier detected is not a picture carrier or its 15 amplitude is not sufficient, the search for another carrier is continued.
Once a tuning sequence has been completed, i.e., an acceptable channel has been located, no action is taken unless UPPB 33 or DNPB 35 is depressed causing microprocessor 20 41 to generate an UP signal or a DN signal, respectively (program step 21). If the UPPB 33 has been depressed and tuning system 23 was previously set to ramp in the upward direction, as indicated by the UP ~AMP signal (program step 22), an upward search, as described above, is initiated.
25 If UPPB 33 has been depressed and tuning system 23 was previously set to ramp in the downward directiori, as indicated by the DN RAt~P signal (program step 22), the address for tuning voltage boundary memory 37 is increased by one (program step 23). If the latter were not done, the boundary 30 voltage then generated would be the lower boundary voltage for the presently tuned channel rather than the upper boundary voltage. As a result, the boundary voltages generated during the subsequent upward search would be out of step with the generated channel numbers.
If DNP~ 35 is depressed, a downward search is initiated. The downward search sequence, indicated by the flow chart shown in FIGU~E 4c, is similar to the upward search sequence shown in FIGURES 4a and 4b and will not be described in detail. ~owever, it should be noted if a ,.
40 downward search is initiated after the termination of an als63ss 1 - 16 - RCA 73,145 upward search, the address for tunin(3 volt~ge boundary memory 37 is decreased by one so as to coordinate the ~oundary voltages and channel numbers generated during the subsequent search (program steps 24 and 25). In addition, boundary voltages 83+, 13+ and 6 for channels 83, 13 and 6, respectively, are skipped during a downward search by decreasing the address for tuning voltage boundary memory 37 when the channel number is 83, 13 or 6 (program steps 26 and 27).
Since the voltages stored in memory 37 are only utilized for determining the channel numbers to be displayed, they need not be as precise as voltages stored in a memory of a tuning system of the voltage synthesizer type which are utilized for tuning a receiver. Nevertheless, at the present state of the art, it is difficult to specify the tuning voltage characteristics for a large number of varactor controlled tuners within predetermined limits even for displaying channel numbers.
~herefore, it i5 desirable that the receiver manufacturer program the information in memory 37 so that the stored b~undary voltages correspond to the tuning voltage character-istics of the particular local oscillator and RF portion for which they are intended. For this purpose, it is desirable that memory 37 be a pRorl. The binary signals representing the boundary voltages may be entered in memory 37 utiliziny the arrangement shown in FIGURE 5. In the arrangement of FIGUR~ 5, the output of D/A converter 47 is co~pled to the tuning voltage input of ~F unit 3 and local oscillator 7. The appropriate band selection signals are externally generated by a band selection control unit 501.
Binary signals representing the address of the memory locations of memory 37 are externa]ly generated by an address register 502. In addition, test equipment including a frequency synthesizer 503, an up,/down counter 504, a frequency counter 505 and a write push button 507 is connected to various portions of the receiver as shown in FIG~E 5.
r~ith this arrangement~ the ~ollowing setup procedures may be employed to store the binary signals representing the boundary voltages.
. '' '' ' , ~ .
- ~ i `` ` 1156385 1 -17- RCA 73,145 (1) f~ddress the memory location in which the boundary voltage is to be stored.
(2) Set frequency synthexizer 503 to the frequency corresponding to the boundary voltage.
(3) Change the contents of up/down counter 504 until the desired IF (45.75 ~Hz) is indicated by frequency counter 505.
(4) Depress write push button 507 to enter the binary signals generated by up/down counter 504.
In this arrangement since D/~ converter 47 employed during normal operation is employed during setup, the errors of D/A converter 47 are accounted for by the set-up procedure.
Another arrangement for programming memory 47 is 15shown in FIGURE 6. With this arrangement, the following set-up procedure may be employed by means of address register 601.
(1) Address the memory location in which the boundary voltage is to be stored.
(2) Set frequency synthesizer 602 to the frequency corresponding to the boundary voltage.
, (3) Adjust variable voltage source 603 until ; frequency counter 604 indicates the desired IF (45.75 MHz).
(4) Change the contents of up/down counter 604 25until a comparator 605 indicates a state change by means of, for example, a lamp 606 coupled to its output.
(5) Press write push button 607 to enter the binary i signals generated by up/down counter 604.
If comparators 49 and 55 are included within a 30single integrated circuit, their offset voltage character-istics will tend to be similar. Therefore, it may be desirable to employ one of voltage comparators 49 and SS
as comparator 605 so that their offset voltage character-istics are accounted for during setup.
FIGURE 7 shows a logic implementation of fast up/down control unit 95 (s~lown in block diagram form in FIGURE 1). During an upward search, whenever binary signals representing the channel number of the last channel in a band, i.e., channel number 06, 13 or 83, are generated by channel number memory 43 (of the arrangement shown in FIGURE 1), .. :.. . . .. .. .. . .
, - als63ss 1 -18- RCA 73,145 band decoder 61 (of the arrangemellt shown in FIGURE 1) generates a signal representing the occurrence. In response, san OR gate 701 couples a high level logic signal to the S
(Set) inputs of D (Data) FFs 703 and 705 thereby causinq low level logic signals to be developed at their Q outputs.
As soon as binary signals representing the channel number of the first channel in the next band, i.e., channel number 1007, 14 or 02, are generated, a high level FAST DN ENABLE
logic signal is generated by the logic configuration including logic gates 707, 709, 711, 713, 715 and 717. At the same time, OR gate 717 generates a high level logic signal which triggers a monostable multivibrator (~IS:lV) 719. ~1S~ 719 15generates a positive-going FAST DN TIr1E pulse which has a duration sufficiently long for the fast down ramping interval to be completed. In response to the UP R~tlP signal generated by S-R FF 83 (of the arrangement shown in FIGURE lb) and : the FAST DN ENABLE and FAST DN TIllE sisnals, an AWD gate 721 20generates a high level FAST DN signal.
~ The FAST DN signal terminates when the tuning voltage has a magnitude substantially equal to the lowest magnitude of the tuning voltage range of the lowest channel in the next band. A comparator 72~ determines when the tuning 25voltage has a magnitude corresponding to the beginning, in the upward direction, of the tuning voltage range for channel 7. When the beginning of the tunillg voltage range for ¦ channel 7 is reached, a high lcvel logic signal is coupled to the C (Cloc~) input of D FF 703. As a result, since the 30D input of D FF 703 is coupled to ~ignal ground, D FF 703 is reset causing a high level logic signal to be developed at its Q output. In response, by means of logic gates 707, 709 and 711, the FAST D~l ENABLE signal becomes a low logic level, and by means of AND gate 721, the high level FAST DN
35signal is terminated (i.e., becomes a low logic level).
Assuming that the magnitudes at the beginnings of the tuning voltage ranges, in the upward scanning direction, for channels 2 and 14 are approximately the same (as shown in FIGURE 2), a single comparator 725 may be used 40to determine when the tuning voltage has a magnitude ~.
115638~ ` `
1 -19- RCA 73,145 correspondin-3 to t~le beginning of the tuning voltage ranges for channels 2 an(l 14. When the b~g~t-niny~; o~ the tuning svoltage ranqe~ for channels 2 and 7 are reached, D FF 705 is reset and by means of logic gates 713, 715, 709 and 711 the FAST DN ENABLE signal becomes a low logic level, and by means of AND ~ate 711 the high level FAST DN signal is terminated (i.e., becomes a low logic level).
~uring a downward search, by means of OR gate 717 a D FF 727 is set when the binary signals representing the lowest channel number, i.e., channel number 02, 07 or 14, in a band are generated. As soon as binary signals repre-senting the first channel number in the next band, i.e., 15channel number 83, 06 or 13, are generated, an AND gate 729 generates a high logic level FAST UP ENABLE signal. At the same time, MS.`5V 731 is tirggered by means of OR gate 701 to generate a high logic level FAST UP TI~lE pulse which has a duration sufficiently long for fast down ramping to be 20completed. An AND gate 733, in response to the FAST UP
ENABLE signal, FAST UP TIrlE pulse and DN RA~P signal, generates a high level FAST UP signal. When the tuning voltage has a magnitude correspondin~J to the }~eginning of the tuning ranges for the highest channels in the next bands, 25aSsuming that these magnitudes are approximately the same (as shown in FIGURE 2), a comparator 735 causes D FF 727 to be reset. As a result, the high logic level FAST UP
EN~BLE: and FAST UP signals are terminated.
While the threshold voltages for comparators 723, 30725 and 735 of the implementation of control unit 95 shown in FIGURE 7 are derived from a resistive divider 736,it is noted that they ma~ be derived by addressing corresponding memory locations of T~l boundary memory 37 during the fast up and fast down ramping intervals.
An implementation of AFT comparator 63 shown in block diagram form in FIGI~RE la is shown in FIGURE 8. AFT
comparator 63 includes a comparator 801 for detecting a pre-determined voltage corresponding to the positlve "hump" of the AFT voltage and a comparator 803 for detecting a pre-40determined voltage corresponding to the negative "hump" of `` ll56385 1 - 20 - RCA 73,145 the AFT voltage. The remaining logic portion of AFT com-parator 63 detects the sequence of the "humps" of the AFT
voltage to determine whether the AFT voltage is in its control range,i.e., the portion hetween the humps, thereby indicating that a carrier has a fre-~-uency near enough to the desired IF ~45.75 ~z) so that normal ramping may be stopped. For this purpose, the logic portion of AFT comparator 63 is arranged so that 10 when the frequency of the local oscillator is being increased and, as a result, the frequency of the IF signal is being decreased, the negative hump is detected before the positive hump and that when the frequency of the local oscillator signal is being decreased and, as a result, the frequency 15 of the IF signal is being increased, the positive hump is detected before the negative hump. ~hen the second of the two humps is detected, an AFT VALID signal is generated.
The logic portion of AFT comparator 63 is arranged so that after a carrier has been detected, the first hump detected 20 thereafter is disregarded in a subsequent sequence detection operation. This is done since, in this situa~ion, when ramp-ing is again initiated, the first hump detected is associated with the previously detected carrier rather than the next one.
The logic portion of AFT comparator 63 includes four 25 D FFs 805, 807, 809 and 811 which are reset in response to a START R~`lP signal. Assuming that the ramping direction is downward, i.e., the frequency of the IF signal is increasing, the first hump detected will be the negative hump associated with the previously detected carrier. Accordingly, D FF 805 30 is set and an AND gate 813 is enabled. The next hump detected will be the positive hump associated with the next carrier. Accordingly, D FF 807 is set and AND gate 815 is enabled. In addition, since AND gate 813 was already enabled, D FF 80~ is set. However, since an AND gate 817 is disabled due to the absence of a high logic level UP RA~P
signal, an AFT VALID signal is not generated by an OR gate 819.
The next hump detected will be the negative hump 40 associated with the next carrier. Accordingly, since AND
gate 815 was already enabled by set D FF 80/, D FF 811 is set.
;~ -1 -21- RC~ 73,145 Since an AND gate 821 is enabled by a high logic level DN ~P
signal, an A~T V~LID signal is generated ~y O~ gate 819.
Thus, in the downward ramping direction, the first negative hump is disregarded and an AFT VALID signal is generated after a positive hump--neyative hump sequence.
In the upward ramping direction, the logic portion of AFT
comparator 63 operates in a similar fashion to disregard lOthe first positive hump and generate an AFT VALID signal after a negative hump--positive hump sequence.
Since the portions of automatic channel detection circuit 31 for evaluating the synchronization and AGC signals are well known in the signal seeking art, no detailed 15description of these components of the present system will be provided.
While automatic channel detection circuits 31 have been described with reference to the specific arrangement shown in FIGURE la, it will be appreciated that other 20arrangements for the same purpose, such as for example, the arrangement disclosed in U.S. Patent Number 3,632,864, may be employed. Furthermore, whi]e the present tuning and : channel number identification system has been described in terms of an automatic signal seeking system, the channel 25identification apparatus may include tuning systems in which a ramp or ramp-like tuning voltaye is generated in response to manual control, by means of a potentiometer arrangement or the like, until an acceptable channel is located. These and other modifications are intended to be included within 30the scope of the present invention as defined by the fo~lowing c~aims.
~0 ',~ J
Claims (7)
1. Apparatus for tuning a television receiver to various channels, comprising: local oscillator means responsive to a tuning voltage for generating a local oscillator signal having frequencies for tuning said receiver to said channels; tuning control means for generating said tuning voltage; said tuning control means including direction means for selectively causing the frequency of said local oscillator signal to be changed in an increasing or decreasing sense; memory means including a plurality of memory locations for storing binary signals representing respective channel boundaries corresponding to respective frequencies;
address means for addressing said memory locations;
comparison means for generating an address change signal when the frequency of said local oscillator signal traverses a frequency corresponding to a boundary stored in an addressed one of said memory locations; control means for causing said address means to address the memory location corresponding to the next consecutive boundary in response to said address change signal as long as the frequency of said local oscillator is being substantially changed by said direction means; channel number means for generating binary signals representing channel numbers; said control means causing said channel number means to generate the binary signals representing the channel number next in the order corresponding to the sense of the change of the frequency of said local oscillator in response to said address change signal as long as said frequency is being substantially changed by said direction means;
and display means responsive to the binary signals representing said channel numbers for displaying said RCA 73145 Canada
address means for addressing said memory locations;
comparison means for generating an address change signal when the frequency of said local oscillator signal traverses a frequency corresponding to a boundary stored in an addressed one of said memory locations; control means for causing said address means to address the memory location corresponding to the next consecutive boundary in response to said address change signal as long as the frequency of said local oscillator is being substantially changed by said direction means; channel number means for generating binary signals representing channel numbers; said control means causing said channel number means to generate the binary signals representing the channel number next in the order corresponding to the sense of the change of the frequency of said local oscillator in response to said address change signal as long as said frequency is being substantially changed by said direction means;
and display means responsive to the binary signals representing said channel numbers for displaying said RCA 73145 Canada
2. The apparatus recited in Claim 1 wherein said memory locations store respective boundary voltages having magnitudes substantially equal to the magnitudes of tuning voltages at frequencies between tuning voltage ranges of respective adjacent channels, and wherein said comparison means generates said address change signal when the magnitude of a pre-determined one of the boundary voltages stored in an addressed one of said memory locations and said tuning voltage exceeds the magnitude of the other.
3. The apparatus recited in claim 2 wherein: at least some of said memory locations store boundary voltages having magnitudes substantially equal to the magnitudes of said tuning voltages at frequencies midway between the frequencies of picture carriers of respective adjacent channels.
4. The apparatus recited in claim 3 wherein:
said direction means includes up switch means for causing the magnitude of said tuning voltage to increase when operated and down switch means for causing the magnitude of said tuning voltage to decrease when operated; said control means causes said address means to address the memory location corresponding to the next higher boundary voltage if said up switch means is operated next in succession after said down switch means is operated and to address the memory location corresponding to the next lower boundary voltage if said down switch means is operated next in succession after said up switch means is generated.
RCA 73145 Canada
said direction means includes up switch means for causing the magnitude of said tuning voltage to increase when operated and down switch means for causing the magnitude of said tuning voltage to decrease when operated; said control means causes said address means to address the memory location corresponding to the next higher boundary voltage if said up switch means is operated next in succession after said down switch means is operated and to address the memory location corresponding to the next lower boundary voltage if said down switch means is operated next in succession after said up switch means is generated.
RCA 73145 Canada
5. The apparatus recited in Claim 3 wherein:
said control means includes automatic channel detection means for detecting the presence of carriers associated with respective channels; and said tuning voltage means includes stop means for stopping further changes in the magnitude of said tuning voltage upon the detection of one of said carriers.
said control means includes automatic channel detection means for detecting the presence of carriers associated with respective channels; and said tuning voltage means includes stop means for stopping further changes in the magnitude of said tuning voltage upon the detection of one of said carriers.
6. The apparatus recited in claim 1 or 2 wherein:
said control means includes a microprocessor.
said control means includes a microprocessor.
7. The apparatus recited in claim 2 wherein: said memory means includes a programmable read only memory programmed to store all of said boundary voltages at the time of manufacture of said receiver.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US4376479A | 1979-05-30 | 1979-05-30 | |
| US43,764 | 1979-05-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1156385A true CA1156385A (en) | 1983-11-01 |
Family
ID=21928769
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000352638A Expired CA1156385A (en) | 1979-05-30 | 1980-05-23 | Channel identification apparatus useful in a sweep type tuning system |
Country Status (2)
| Country | Link |
|---|---|
| JP (2) | JPS55162619A (en) |
| CA (1) | CA1156385A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60109796U (en) * | 1983-12-27 | 1985-07-25 | スタンレー電気株式会社 | Ceramic cutter with heater |
-
1980
- 1980-05-23 CA CA000352638A patent/CA1156385A/en not_active Expired
- 1980-05-29 JP JP7266380A patent/JPS55162619A/en active Granted
-
1981
- 1981-05-28 JP JP8242481A patent/JPS5726919A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55162619A (en) | 1980-12-18 |
| JPS6234175B2 (en) | 1987-07-24 |
| JPS5726919A (en) | 1982-02-13 |
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