CA1146264A - Solid state digital television camera - Google Patents
Solid state digital television cameraInfo
- Publication number
- CA1146264A CA1146264A CA000369623A CA369623A CA1146264A CA 1146264 A CA1146264 A CA 1146264A CA 000369623 A CA000369623 A CA 000369623A CA 369623 A CA369623 A CA 369623A CA 1146264 A CA1146264 A CA 1146264A
- Authority
- CA
- Canada
- Prior art keywords
- digital
- solid state
- converter
- filter
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/80—Camera processing pipelines; Components thereof
- H04N23/84—Camera processing pipelines; Components thereof for processing colour signals
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Color Television Image Signal Generators (AREA)
- Processing Of Color Television Signals (AREA)
- Color Television Systems (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A solid state digital television camera has a solid state image sensing device, an A-D converter for converting the output of the image sensing device to a digital color signal, a filter for providing a predetermined filter characteristic to the digital color signal, and a digital color modulator for modulating the output of the above filter to produce a digital modulated signal.
In this digital television camera, the process rate between the solid state image sensing device and the filter is selected to a sampling rate of the solid state image sensing device or where fsc is a color subcarrier frequency, p is 3 or 4, and m and n are relatively small integers. The process rate for the remains is selected to pfsc. In addition, a D-D converter for converting the process rate from
A solid state digital television camera has a solid state image sensing device, an A-D converter for converting the output of the image sensing device to a digital color signal, a filter for providing a predetermined filter characteristic to the digital color signal, and a digital color modulator for modulating the output of the above filter to produce a digital modulated signal.
In this digital television camera, the process rate between the solid state image sensing device and the filter is selected to a sampling rate of the solid state image sensing device or where fsc is a color subcarrier frequency, p is 3 or 4, and m and n are relatively small integers. The process rate for the remains is selected to pfsc. In addition, a D-D converter for converting the process rate from
Description
26~
13RCI<GRO~ND O~ Tll]- INV~ITT~
~ield of_the Inventlon This invention relates to a television camera usincJ
a solict state irnage sensing dcvice such as a cllar(Je couplt-~cl cleviee for producincJ a eolor tc~lt?visioll sicJllal with the digital proeess being performed.
Deseription oc the Prior Art ~__ _ _ _ __ _ ~ eol.or televis.ion eamera has bcen proposecl in whieh an image pie]~up output (an analog signal) derivecl from the solid state image sensing cleviee is subjeete~cl-to a dicJital intermediate process and a standard analog color television signal is finally produeed. As eomparecl with another eonventional eolor televisiorl eamera in whieh a eolor television sicJnal is analog-proeessecl over the whole signa].
lS proeess interval, the aforesaid eolor television eamera is partieularly supe~rior in signal proeess, cireuit eonstrue-tion, reliability, e-te. Aeeordingly, in eonsideration of interfaee with other digital equipments, the signal proee~ss of most color -television eameras is reeen-tly apt to be digitized.
In the ease of digital-proeessing the image piekup output for producing a eolor television signal, the proeess rate in produeing a digital modulated eolor signal is normally seleeted to a frequeney whieh is three or four times the eolor subearrier frequeney fsc. This is eaused by the eolor subearrier frequeney ESc of the standard eolor television signal, the band width of a video signal, easy proeess of the signal when the video signal is eon-sidered as two-dimensional sampling system, and so on.
Aeeordint31y, wllen 3fsc or 4fse is seleeted as the 6~L
frequeney of a reEerenee clock, eircuit systems for dicJital signal process must be all processecl by a rate oE 3fse or ~fse sueh as the frequeney of a drive pulse for drivincJ
a solid state image sensing deviee, a sanlp]incJ rate of a sampling pu]se for samplincJ-holclin(3 the ou-tput of the solid state image sensing device, a process rate Eor eonverting the image sensing output from its analog form to its digital form, and the like. Ilowever, if this ref-erenee eloek is used for proeessing the circuit system, the frequency exeeeds 10M~lz -to inerease tile proeessing speed of the circuit system. ~ur-ther, iE ~ cut-off fre-quency is made constant as in the digital filter used for limiting the frequency band of a color signal by way of example, the number of delay elements or -the like used in this digital filter increases in proportion to the proeess rate. Therefore, a digital proeess cireuit of large scale must be prepared resulting in a trouble of forming an integrated eircuit.
SUMM~RY OF THE INV~NTION
~0 ~eeordingly, an objeet of this invention is to provide a solid state digital television eamera in which the number of digital process cireuits to be proeessed by the ref-erence clock is made as small as possible while eireuits treatable by a frequency lower than that of the referenee clock are used so that the in-tegrated cireuit construction is made easier. In other words, different from the ref-erence clock, the sampling rate Eor driving the solid state L
image sensing device is adapted to utilize a frequeney lower than that of this reference cloek. Therefore, with
13RCI<GRO~ND O~ Tll]- INV~ITT~
~ield of_the Inventlon This invention relates to a television camera usincJ
a solict state irnage sensing dcvice such as a cllar(Je couplt-~cl cleviee for producincJ a eolor tc~lt?visioll sicJllal with the digital proeess being performed.
Deseription oc the Prior Art ~__ _ _ _ __ _ ~ eol.or televis.ion eamera has bcen proposecl in whieh an image pie]~up output (an analog signal) derivecl from the solid state image sensing cleviee is subjeete~cl-to a dicJital intermediate process and a standard analog color television signal is finally produeed. As eomparecl with another eonventional eolor televisiorl eamera in whieh a eolor television sicJnal is analog-proeessecl over the whole signa].
lS proeess interval, the aforesaid eolor television eamera is partieularly supe~rior in signal proeess, cireuit eonstrue-tion, reliability, e-te. Aeeordingly, in eonsideration of interfaee with other digital equipments, the signal proee~ss of most color -television eameras is reeen-tly apt to be digitized.
In the ease of digital-proeessing the image piekup output for producing a eolor television signal, the proeess rate in produeing a digital modulated eolor signal is normally seleeted to a frequeney whieh is three or four times the eolor subearrier frequeney fsc. This is eaused by the eolor subearrier frequeney ESc of the standard eolor television signal, the band width of a video signal, easy proeess of the signal when the video signal is eon-sidered as two-dimensional sampling system, and so on.
Aeeordint31y, wllen 3fsc or 4fse is seleeted as the 6~L
frequeney of a reEerenee clock, eircuit systems for dicJital signal process must be all processecl by a rate oE 3fse or ~fse sueh as the frequeney of a drive pulse for drivincJ
a solid state image sensing deviee, a sanlp]incJ rate of a sampling pu]se for samplincJ-holclin(3 the ou-tput of the solid state image sensing device, a process rate Eor eonverting the image sensing output from its analog form to its digital form, and the like. Ilowever, if this ref-erenee eloek is used for proeessing the circuit system, the frequency exeeeds 10M~lz -to inerease tile proeessing speed of the circuit system. ~ur-ther, iE ~ cut-off fre-quency is made constant as in the digital filter used for limiting the frequency band of a color signal by way of example, the number of delay elements or -the like used in this digital filter increases in proportion to the proeess rate. Therefore, a digital proeess cireuit of large scale must be prepared resulting in a trouble of forming an integrated eircuit.
SUMM~RY OF THE INV~NTION
~0 ~eeordingly, an objeet of this invention is to provide a solid state digital television eamera in which the number of digital process cireuits to be proeessed by the ref-erence clock is made as small as possible while eireuits treatable by a frequency lower than that of the referenee clock are used so that the in-tegrated cireuit construction is made easier. In other words, different from the ref-erence clock, the sampling rate Eor driving the solid state L
image sensing device is adapted to utilize a frequeney lower than that of this reference cloek. Therefore, with
2~9~
an attention beiny paid to the above aspcct, t~e cliyital process circuit systems of process rate haviny th~ afore-said sampliny rate are increased in num~)e2^, and portions having uneven process rates are interposecl therebetween with a D-D converter for beiny coupled to ~ach other.
A further ob~ect oE -this invention is to provide a solid state digital television camera in which outputs of an ima~e sensinc~ device usiny a charcJe coupled device or the lil;e for procluciny a discrète imaye pickup signal are all treatecl by di~ital circuits to finally obtain a standard television signal, and -to ob-tain a video output which is less in siynal deterioration caused by the temperature drift, secular variation, noise, etc. oE the circuit.
The above and other objects, features and advanta~es of this invention will be apparent from the following description taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF TH~ DRAWINGS
Fig. 1 is a view showiny the relation of spatial sampling between two solid state imaye sensiny devices;
Fig. 2 is a block diayram showing one example of this invention;
Fig. 3 is a block diagram of a gamma correction cir-cuit of this invention;
Fig. 4 is a graph used for explaininy the operation of the circuit of Fig. 3;
Fig. 5 is a block diagram showiny a filter device used in this invention;
Fig. G is a block diagram showincJ a cligital fi]ter usecl in this i.nvention;
Fig. 7 is a block diacJram showing a D-D converter usecl in this invention;
Fig. 8 is a block diagram showincl cliqital modulators used in thi.s lnven-t1.on;
Figs. 9A and 9B are vector diagrams used for explain-ing this invention; and Fi.gs. ln~ to 10F are waveform diagrams used Eor e~plaininc3 the operation of the modulator of Fig. ~.
DETAII D D~SCRIPTIO~ OF T~IE PR~F~RR~D ~IBODI~I~NT
A description will hereinafter be given on one embodi-ment of this invention which is applied to a color television camera using a charge coupled device (CCD) as its image sensincJ devi.ce wi-th reference to Fig. 1 et seq. This embodiment uses a two-chip type color television camera, in which one CCD 1 provides a green sic~nal G only from its entire surface and the other CCD 2 provides a red signal R and a blue signal B alternately in a line sequential manner as`shown in Fig. 1. In order to prevent the aliasing noise from being generated and to improve the resolution in the horizontal direction, the spatial samp].ing phase be-t~7een the CCDs 1 and 2 iS shifted by T/2 where r is an arranging pitch of picture elements in the horizontal di-rection.
Referring to Fig. 2, the image pickup outpu-t, or the red and blue signals R and B, from the CCD chip 2 is first converted to a 1-sample 8-bi-t digital signal or a word signal by an analog-to-digital (A-D) converter 3 and thus 30~ converted sicJnal is suppli.ed to a signa]. process circuit 4 6~
for effecting a signal process. In ~his connection, since the input signal o:E this A-D converter 3, or the output itself of the CCD chip 2 is already sampled by the CCD
drive cloc~, the A-D converter 3 is sufEicient to have only a functi.on to quantize the ou-tput of CCD chip 2.
The aforesaid signal process implies a process for gamma (y)-correction, white clip, pedes-tal clamp or the like as ell known.
The digital signal subjected to the above si~nal proeess is supplied to a filter device 6. As shown, the filter device 6 consists of a simultaneous circuit 7 for making line sequential signals in a simultaneous form, a digital filter 8 for providing a clesired filter charac-teristic, and a matrix circuit 9. The matrix circuit 9 functions to produce band-limited digital color signals, or red signal CR and blue signal CB, and also digital lumi-nanee si~nals YR and YB. The filter 8 is a two-dimensional spatial filter, which is used to eliminate an aliasing noise eaused by the line sequential television system. The filter 8 also effeets band limit for luminanee signal components and eolor signal eomponents, and further effeets vertical aperture correction.
The signal proeess system between the CCD chip 2 and tl~e filter device 6 is processed at a sampling rate of the 2S CCD 2. In this example, the sampling rate of the CCD 2 is selected as 3fSc(=Fs)~ so that the A-D converter 3, proeess eireuit 4 and filter deviee 6 are all processed at the sampling rate 3fse~ A eloek pulse CI~F of this sampling rate is supplied from a eloelc pulse generator 10. The following digital proeess eireuits will be proeessed based 6~
on a clock pulse CKB of 3~sc or ~lfsc,.
The digita]. color signal.s CR ancl C~3 ~rom the Ma-trix eireuit 9 are suppliecl to a diqital-to-(li.gital (D-D) eonverter 2n t~here the cli~i-tal eolour si(JIlals C~ and CB
processed at the samplincJ rate f 43~sc are converted into digital color signals CR and CB of samp].ing rate of 4fse~ Thus eonverted digi.tal eolor signals CR and CB are fed to a digital eolor modulator 21 where they are modulated to, for example, a quadrature 2-phase signal.
This modulated di~ital color sic~na]. CRB (= CR -~ ~B) is fed to a digita]. adder or mixer 23 where it is mixed with the digital luminance signal YR or YB which is delayed by a predetermined -tirne at a digital delay circuit 22. Thus, a digital video signal DVSl is derived Erom the digital adder 23.
Meanwhile, a cligital synchronizing signal generator 24 is applied with a pulse from the generator 10 to produce a digital burst signal SB and a composite synehronizing si~nal SYNC, which are then added to the digital video signal DVSl at an adder or mixer 25. The digital video signal DVSl is then eonverted into an analog signal at a digital-to-analoc3 (D-A) eonverter 102 and this analog signal is fed to an adder or mixer 103.
The green signal G derived from the CCD 1 is also subjected to a similar digital process through an A-D
eonverter 33,.a signal process eireuit 34, a filter deviee 36, a D-D eonverter 40 and a digital eolor modulator 41 to obtain a modulated digital signal CG. This signal CG is fed to an adder or mixer 43 where it ls added to a digital luminance signal YG from a digital delay eireuit 42 to ~g~6~
provide a cli~ital video signal DVS2. This dicJital video si~nal DVS2 is supplied throuc3h a 'lll/2 dl(~ital delay line 105 and a D-~ converter 104 to the adder 103, where it is addecl to the dig,ital video sicJnal DVSl to produce a standard analoc) television sic~nal TVS. In this case, the filter device 36 is not providecl with a simultarleous cir-euit. The IH/2 digital delay line 105 is provided Eollowing to the mixer ~3 in order to correct the time difference between digital video si~nals DVSl and DVS2 resultin~ from the offset 'r/2 of picture elements between the CCD chips 1 and 2 as shown in Fig. 1 in such a manner that the modulation axis advanced in phase at the clicJi-tal color modulator 41 is restored to be coincident with the spatial sampling phase of the green signal G. When the red and blue signals R and B are same in spa-tial sampling phase as the green signal G, the dlgital delay line 105 is not required.
Eaeh eireuit used in this invention will next be deseribed in detail.
At Eirs-t, a digital y-eorrection eircuit 50 provided in the signal process eireuit 4 is shown in Fig. 3. The di~ital y-eorreetion cireuit S0 consists of a read-only memory (ROM) 51 used as a look-up table, and lateh eircuits 52 and 53 provided at the input and outpu-t sides of the ROM-51. The ROM 51 stores therein a y-eorreeted output eode word eorresponding to an input eode word as shown in Fig. 4. Aecordingly, an 8-bit l-word input code word, which is the lateh output, i9 applied to the ROM 51 to address it so that the addressed code word is read out.
The latch circuits 52 and 53 are driven by the same clock ;Z64 pulse C~F and hence elements of low speed may be used therefor. Further, the ROM 51 has an input and output in a rate of 1:1 so that it can be constructed with-a relatively simplified logic circuit.
Fig. 5 shows tlle filter device 6, in which the simul-taneous circuit or switcher 7 includes a pair of cascade-connected delay elements 55 and 56 each having delay time of lH, an adder 57 and an attenuator 58. The digital color signal R or B from the signal process circuit 4 and that delayed by 211 through the delay circuits 55 and 56 are added together at the adder 57, and then the added signal is fed to the at-tenuator 58 where the level of the added signal is attenuated to 1/2 to perform vertical interpolation based on outputs of two horizon-tal lines with respect to the same color signal. This two-dimensional spatial filter acting as the ver-tical interpolator for the above has the following transfer function II(v).
H(v) = [1 + 12(~ 1 ~ ~)]
where ~ 1 is a delay element for two scanning lines in the ~0 vertical direction. Then, a switching circuit 59 following to the attenuator 58 effects switching operation at every line interval (11-1) to make the line-sequential digital color signals in a simultaneous mode.
The digital color signals R and B simul-taneously arranged by the switching circuit 59 are respectively supplied to digital filters 8R and 8B to provide desired filter characteristics. As the digital filters 8R and 8B, transversal type digital filters having symmetric impulse responses are employed in order to provide stabilized 30 . process and constant group delay characteristics.
6'~
Fig. 6 shows one example of the digital filter 8R
or 8B. This example is a scptenary digita:L filter formed as a low pass filter, in which six clelay operators 61 to 66, eacll havin~ a delay of l/Fs, are connectecl in series.
~n output oL, ~or example, the dekly operator 63 and outputs o~ three adders 67 to 69 are supplied through elements 70 ~o 73 having impulse response coef~icients ho to h3 to an adder 74 -to derive therefrom a digital color signal RL or BL having a frequency band limited to about 800 KIIz.
The operators 61 to 66 are supplied with the clock pulse CKF from the generator 10 and the delay time in the horizontal direction is l/Fs, so that the process at low speed can be eEfected. The filter wi-th the a~oresaid construction also has the constant gro~p delay charac-teristics and hence there is no error oE delay between R
or B channel and G channel. The other digi-tal Eilter 8B
is also constructed in the same manner as above so that its description will be omitted.
~0 Referring again to Fig. 5, the band-limited digital color signals RL and BL from the digital filters 8R and 8B
are suppliecl to the matrlx clrcult 9 toget}ler with band-unlimited digltal color slgnals ~ and BW so that the following dlgital luminance signals YR and YB are produced ~5 therefrom.
R 0.30 RL + 0.25 RH
B 0.11 BL + 0.25 sIl where RH and BH are hlgh frequency components of the digital color slgnals RW and Bw.
~46Z6'~
If the digital color slgnals RL and BL passed through the matrix circuit 9 are expressed as CR and CB~ these signals CR and CB are supplied to the D-D converter 20 (Fig. 2) where they are subjected to the rate conversion process. T}le D-D conversion is a kind oE interpolation so that the process rate of FS = ~3ESc can be converted to that of FS = 4fsc by newly interpolating -two samples between respective samples of the digital color signal CR or CB.
Fig. 7 sllows one example of the D-D converter 20, in which rate conversion is effected hy interpolation using linear approximation. Each of delay operators 80 and 81 composed of a n-type flip-flop or -the like is driven by the clock pulse CI~B of 4fsc and provided with delay of l/4fsc. The delay operators 80 and 81 are connected in a cascade manner. Outputs of respective steps are supplied to an adder 82 in which an original outpu-t, an output delayed by 4fl , and an output delayed by 2fl are added together. Thus added output of the adder 82 is then fed to a level shlft circuit 83 where its level is lowered to -.
By performing the above signal process, two samples are newly interpolated between two original samples at a period of 4fl so that conversion of process rate is carried out and an interval between two original samples is approximated to a straight line.
After matching of the process rate, the digital color signals CR and CB are subjected to balanced modulation at the digital modulator 21 to provide the modulated digital color signal CRB. That is, in this example is performed -- 11. --1~62~
quadrature 2-phase modulation. There~ore, the digital color sicJnals CR ~ncl C13 are resolvecl into a component VRB
ich is in-phase with R-axis ancl a componcrlt URB of quadrature axis. Fig. 8 shows the }~alanced moudlators 21 and 41, in W]~iCII the digital color signcll CB ls suppliecl to a circuit 90 to derive therefrom a color cornponent Bsin~ in-phase with the R-axis, where s is the level of a color signal and Q an angle between vector B of the color signal CB and tlle quadrature axis UR~ as shown in Fig. 9~.
In this example, G is about 30. The circuit 90 also performs suitable level adjustment of the color component.
Similarly, the digital color signal CB is fed to another circuit 91 to derive therefrom a color component BCos~
on the quadrature axis URB after bein~ sui-tably adjusted in level.
On the other hand, the cligital color signal CR is adjusted in level at a circuit 93 and then supplied to a subtracter 94 together with the output of the circuit 90 to derive therefrom a color component (R-Bsin~) on R-axis, or VRB-axis. These in-phase component VRB and quadrature component URB are alternately obtained at every 1/2fsc by a switchin~ circuit or data multiplexer 95 and thereafter supplied to a multiplier or sign inverter 96. The sign inverter 96 is supplied with a earrier fsc from the clock L
pulse generater 10, and performs multiplication of -1 at the former half of carrier period and multiplication of +l at the latter half of carrier period so that the eom-ponents VRB and URB are subjeeted to quadrature 2-phase modulation. L
The digital eolor modulation 41 provided in -the green ~ 12 ~
6~
signal system is also constructed as -the balanced modulator.
Accordingly, -the digita] color signal CG is supplied to circuits 97 and 98 where it is divided to a quadra-ture component URB and an in-phase component VI~B. These com-ponents are switched by a frequency 2fSC at a data multi-plexer 99 and then multiplied with the carrier ESc at a multiplier or sign inverter 100 to provide a digital modulated signal CG subjected to quadra-ture modulation.
A Eurther description for the above will be below given with reference to the modulator 41 of Fig. g, and Fig. 9B.
The input signal CG to the color modulator 41 (the signal CG has only an amplltude component and no phase component) is resolved into components on VRB-axis and URB-axis similarly as in Fig. 9A. In this case, the inpu-t signal CG provides video information which is advanced by T2 pitch of a color element from the signals CR and CB
delivered by -the R and B chips as shown in Fig. 1, so that it is expressed as ~' on the vector of ~`ig. 9B. That is, the signal G' is shown at a position which is delayed by 135 from the vector G of the actual green color. Accord-in~ly, in order to produce the green color signal CG
corresponding to the actual green color vector G, which is also actually subjected to quadrature 2-phase modulation, a delay time of TH/2 is necessary for ~R and CB. For this reason, as shown in Fig. 2, the delay line 105 of time TH/2, or 12-4f3 , is connected following to the mixer 43. In sc - this case, the clock pulse CKB from the clock pulse generator 10 is supplied to the D-A converter 102, while the same is supplied to a phase shifter 101 where it is phase-corrected by an amount for correcting ~/2 pitch and thus corrected - :13 -.
~L46~6~
pulse is fed to the D-A converter 109.
When producing the digital burst signal SB at the synchronizing signal generating circuit 24, since the burst signal is opposi-te in phase relative to U-axis, the burst signal is resolved into a component of R-axis ancl a com-ponent of its orthogonal axis and code words corresponding to respective axes are stored in a memory. Thus, if the above code words are selectively mixed at every l/4fsc, a desired digital burst signal SB can be produced. In the praetical case, a read-only memory is supplied with clock pulses of fsc and 2fSC, a burst flag pulse and a horizon-tal synchronizing pulse, the latter pulses being in synchronism with the former pulses. Thus, these pulses are logically operated to procluce the digital burst signal SB.
Figs. lOA through lOF are views used for explaining the operation of the modulator 21. That is, Fig. lOA shows the phase of a sub-carrier of NTSC signal. Fig. lOs illustrates the waveform of the signal of frequency 2fSC
for switching the multiplexer 95, ancl Fig. lOC shows-com-ponents of an output signal of the mul-tiplexer 95. ~aveform o~ a signal of frequency fsc for switching the sign inverter 96 is shown in Fig. lOD, and an output of the sign inverter 96 is depieted in Fig. lOE. It is noticed from Fig. lOE
that the output of the modulator 21 is a signal subjected to quadrature 2-phase modulation. Fig. lOE represents the phase of the digital burst signal fed to the mixer 25.
As deseribed above, aecording to this invention, the digital process eircuit system X from the CCD ehip 1 (or 2) to the filter device 6 (or 36) is proeessed by the sampling rate FS = ~3fse of CCD ehip 1 or 2, and the o-ther digital -- l'l -- .
~6~
process circuit system Y following to the circui-t system ~ is processed by the rate of FS' = ~fsc~ so that the digital process circuit system X wi-th low-s~eed operation can be used and hence a digital circuit which is inexpensive that much can be employed. Also, matchillg of process rates can be achieved by the D-D converter 20 which is relatively simple in circuit construction, so that there is no trouble in circuit design and i-t is quite suitable for the ;ntegrated circuit construction.
In the above eMbodiment, the process rate of the digital process circuit system Y is FS ~fsc' S sc also applicable. Also, in this embodiment, two-chip type television camera is used, but a single-chip type or three-chip type can a]so be used, that is, any television camera is applicable. Further, the semiconductor image sensing device is applicable not only to television cameras using CCD but also those using MOS-type sensor.
~ 15 -
an attention beiny paid to the above aspcct, t~e cliyital process circuit systems of process rate haviny th~ afore-said sampliny rate are increased in num~)e2^, and portions having uneven process rates are interposecl therebetween with a D-D converter for beiny coupled to ~ach other.
A further ob~ect oE -this invention is to provide a solid state digital television camera in which outputs of an ima~e sensinc~ device usiny a charcJe coupled device or the lil;e for procluciny a discrète imaye pickup signal are all treatecl by di~ital circuits to finally obtain a standard television signal, and -to ob-tain a video output which is less in siynal deterioration caused by the temperature drift, secular variation, noise, etc. oE the circuit.
The above and other objects, features and advanta~es of this invention will be apparent from the following description taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF TH~ DRAWINGS
Fig. 1 is a view showiny the relation of spatial sampling between two solid state imaye sensiny devices;
Fig. 2 is a block diayram showing one example of this invention;
Fig. 3 is a block diagram of a gamma correction cir-cuit of this invention;
Fig. 4 is a graph used for explaininy the operation of the circuit of Fig. 3;
Fig. 5 is a block diagram showiny a filter device used in this invention;
Fig. G is a block diagram showincJ a cligital fi]ter usecl in this i.nvention;
Fig. 7 is a block diacJram showing a D-D converter usecl in this invention;
Fig. 8 is a block diagram showincl cliqital modulators used in thi.s lnven-t1.on;
Figs. 9A and 9B are vector diagrams used for explain-ing this invention; and Fi.gs. ln~ to 10F are waveform diagrams used Eor e~plaininc3 the operation of the modulator of Fig. ~.
DETAII D D~SCRIPTIO~ OF T~IE PR~F~RR~D ~IBODI~I~NT
A description will hereinafter be given on one embodi-ment of this invention which is applied to a color television camera using a charge coupled device (CCD) as its image sensincJ devi.ce wi-th reference to Fig. 1 et seq. This embodiment uses a two-chip type color television camera, in which one CCD 1 provides a green sic~nal G only from its entire surface and the other CCD 2 provides a red signal R and a blue signal B alternately in a line sequential manner as`shown in Fig. 1. In order to prevent the aliasing noise from being generated and to improve the resolution in the horizontal direction, the spatial samp].ing phase be-t~7een the CCDs 1 and 2 iS shifted by T/2 where r is an arranging pitch of picture elements in the horizontal di-rection.
Referring to Fig. 2, the image pickup outpu-t, or the red and blue signals R and B, from the CCD chip 2 is first converted to a 1-sample 8-bi-t digital signal or a word signal by an analog-to-digital (A-D) converter 3 and thus 30~ converted sicJnal is suppli.ed to a signa]. process circuit 4 6~
for effecting a signal process. In ~his connection, since the input signal o:E this A-D converter 3, or the output itself of the CCD chip 2 is already sampled by the CCD
drive cloc~, the A-D converter 3 is sufEicient to have only a functi.on to quantize the ou-tput of CCD chip 2.
The aforesaid signal process implies a process for gamma (y)-correction, white clip, pedes-tal clamp or the like as ell known.
The digital signal subjected to the above si~nal proeess is supplied to a filter device 6. As shown, the filter device 6 consists of a simultaneous circuit 7 for making line sequential signals in a simultaneous form, a digital filter 8 for providing a clesired filter charac-teristic, and a matrix circuit 9. The matrix circuit 9 functions to produce band-limited digital color signals, or red signal CR and blue signal CB, and also digital lumi-nanee si~nals YR and YB. The filter 8 is a two-dimensional spatial filter, which is used to eliminate an aliasing noise eaused by the line sequential television system. The filter 8 also effeets band limit for luminanee signal components and eolor signal eomponents, and further effeets vertical aperture correction.
The signal proeess system between the CCD chip 2 and tl~e filter device 6 is processed at a sampling rate of the 2S CCD 2. In this example, the sampling rate of the CCD 2 is selected as 3fSc(=Fs)~ so that the A-D converter 3, proeess eireuit 4 and filter deviee 6 are all processed at the sampling rate 3fse~ A eloek pulse CI~F of this sampling rate is supplied from a eloelc pulse generator 10. The following digital proeess eireuits will be proeessed based 6~
on a clock pulse CKB of 3~sc or ~lfsc,.
The digita]. color signal.s CR ancl C~3 ~rom the Ma-trix eireuit 9 are suppliecl to a diqital-to-(li.gital (D-D) eonverter 2n t~here the cli~i-tal eolour si(JIlals C~ and CB
processed at the samplincJ rate f 43~sc are converted into digital color signals CR and CB of samp].ing rate of 4fse~ Thus eonverted digi.tal eolor signals CR and CB are fed to a digital eolor modulator 21 where they are modulated to, for example, a quadrature 2-phase signal.
This modulated di~ital color sic~na]. CRB (= CR -~ ~B) is fed to a digita]. adder or mixer 23 where it is mixed with the digital luminance signal YR or YB which is delayed by a predetermined -tirne at a digital delay circuit 22. Thus, a digital video signal DVSl is derived Erom the digital adder 23.
Meanwhile, a cligital synchronizing signal generator 24 is applied with a pulse from the generator 10 to produce a digital burst signal SB and a composite synehronizing si~nal SYNC, which are then added to the digital video signal DVSl at an adder or mixer 25. The digital video signal DVSl is then eonverted into an analog signal at a digital-to-analoc3 (D-A) eonverter 102 and this analog signal is fed to an adder or mixer 103.
The green signal G derived from the CCD 1 is also subjected to a similar digital process through an A-D
eonverter 33,.a signal process eireuit 34, a filter deviee 36, a D-D eonverter 40 and a digital eolor modulator 41 to obtain a modulated digital signal CG. This signal CG is fed to an adder or mixer 43 where it ls added to a digital luminance signal YG from a digital delay eireuit 42 to ~g~6~
provide a cli~ital video signal DVS2. This dicJital video si~nal DVS2 is supplied throuc3h a 'lll/2 dl(~ital delay line 105 and a D-~ converter 104 to the adder 103, where it is addecl to the dig,ital video sicJnal DVSl to produce a standard analoc) television sic~nal TVS. In this case, the filter device 36 is not providecl with a simultarleous cir-euit. The IH/2 digital delay line 105 is provided Eollowing to the mixer ~3 in order to correct the time difference between digital video si~nals DVSl and DVS2 resultin~ from the offset 'r/2 of picture elements between the CCD chips 1 and 2 as shown in Fig. 1 in such a manner that the modulation axis advanced in phase at the clicJi-tal color modulator 41 is restored to be coincident with the spatial sampling phase of the green signal G. When the red and blue signals R and B are same in spa-tial sampling phase as the green signal G, the dlgital delay line 105 is not required.
Eaeh eireuit used in this invention will next be deseribed in detail.
At Eirs-t, a digital y-eorrection eircuit 50 provided in the signal process eireuit 4 is shown in Fig. 3. The di~ital y-eorreetion cireuit S0 consists of a read-only memory (ROM) 51 used as a look-up table, and lateh eircuits 52 and 53 provided at the input and outpu-t sides of the ROM-51. The ROM 51 stores therein a y-eorreeted output eode word eorresponding to an input eode word as shown in Fig. 4. Aecordingly, an 8-bit l-word input code word, which is the lateh output, i9 applied to the ROM 51 to address it so that the addressed code word is read out.
The latch circuits 52 and 53 are driven by the same clock ;Z64 pulse C~F and hence elements of low speed may be used therefor. Further, the ROM 51 has an input and output in a rate of 1:1 so that it can be constructed with-a relatively simplified logic circuit.
Fig. 5 shows tlle filter device 6, in which the simul-taneous circuit or switcher 7 includes a pair of cascade-connected delay elements 55 and 56 each having delay time of lH, an adder 57 and an attenuator 58. The digital color signal R or B from the signal process circuit 4 and that delayed by 211 through the delay circuits 55 and 56 are added together at the adder 57, and then the added signal is fed to the at-tenuator 58 where the level of the added signal is attenuated to 1/2 to perform vertical interpolation based on outputs of two horizon-tal lines with respect to the same color signal. This two-dimensional spatial filter acting as the ver-tical interpolator for the above has the following transfer function II(v).
H(v) = [1 + 12(~ 1 ~ ~)]
where ~ 1 is a delay element for two scanning lines in the ~0 vertical direction. Then, a switching circuit 59 following to the attenuator 58 effects switching operation at every line interval (11-1) to make the line-sequential digital color signals in a simultaneous mode.
The digital color signals R and B simul-taneously arranged by the switching circuit 59 are respectively supplied to digital filters 8R and 8B to provide desired filter characteristics. As the digital filters 8R and 8B, transversal type digital filters having symmetric impulse responses are employed in order to provide stabilized 30 . process and constant group delay characteristics.
6'~
Fig. 6 shows one example of the digital filter 8R
or 8B. This example is a scptenary digita:L filter formed as a low pass filter, in which six clelay operators 61 to 66, eacll havin~ a delay of l/Fs, are connectecl in series.
~n output oL, ~or example, the dekly operator 63 and outputs o~ three adders 67 to 69 are supplied through elements 70 ~o 73 having impulse response coef~icients ho to h3 to an adder 74 -to derive therefrom a digital color signal RL or BL having a frequency band limited to about 800 KIIz.
The operators 61 to 66 are supplied with the clock pulse CKF from the generator 10 and the delay time in the horizontal direction is l/Fs, so that the process at low speed can be eEfected. The filter wi-th the a~oresaid construction also has the constant gro~p delay charac-teristics and hence there is no error oE delay between R
or B channel and G channel. The other digi-tal Eilter 8B
is also constructed in the same manner as above so that its description will be omitted.
~0 Referring again to Fig. 5, the band-limited digital color signals RL and BL from the digital filters 8R and 8B
are suppliecl to the matrlx clrcult 9 toget}ler with band-unlimited digltal color slgnals ~ and BW so that the following dlgital luminance signals YR and YB are produced ~5 therefrom.
R 0.30 RL + 0.25 RH
B 0.11 BL + 0.25 sIl where RH and BH are hlgh frequency components of the digital color slgnals RW and Bw.
~46Z6'~
If the digital color slgnals RL and BL passed through the matrix circuit 9 are expressed as CR and CB~ these signals CR and CB are supplied to the D-D converter 20 (Fig. 2) where they are subjected to the rate conversion process. T}le D-D conversion is a kind oE interpolation so that the process rate of FS = ~3ESc can be converted to that of FS = 4fsc by newly interpolating -two samples between respective samples of the digital color signal CR or CB.
Fig. 7 sllows one example of the D-D converter 20, in which rate conversion is effected hy interpolation using linear approximation. Each of delay operators 80 and 81 composed of a n-type flip-flop or -the like is driven by the clock pulse CI~B of 4fsc and provided with delay of l/4fsc. The delay operators 80 and 81 are connected in a cascade manner. Outputs of respective steps are supplied to an adder 82 in which an original outpu-t, an output delayed by 4fl , and an output delayed by 2fl are added together. Thus added output of the adder 82 is then fed to a level shlft circuit 83 where its level is lowered to -.
By performing the above signal process, two samples are newly interpolated between two original samples at a period of 4fl so that conversion of process rate is carried out and an interval between two original samples is approximated to a straight line.
After matching of the process rate, the digital color signals CR and CB are subjected to balanced modulation at the digital modulator 21 to provide the modulated digital color signal CRB. That is, in this example is performed -- 11. --1~62~
quadrature 2-phase modulation. There~ore, the digital color sicJnals CR ~ncl C13 are resolvecl into a component VRB
ich is in-phase with R-axis ancl a componcrlt URB of quadrature axis. Fig. 8 shows the }~alanced moudlators 21 and 41, in W]~iCII the digital color signcll CB ls suppliecl to a circuit 90 to derive therefrom a color cornponent Bsin~ in-phase with the R-axis, where s is the level of a color signal and Q an angle between vector B of the color signal CB and tlle quadrature axis UR~ as shown in Fig. 9~.
In this example, G is about 30. The circuit 90 also performs suitable level adjustment of the color component.
Similarly, the digital color signal CB is fed to another circuit 91 to derive therefrom a color component BCos~
on the quadrature axis URB after bein~ sui-tably adjusted in level.
On the other hand, the cligital color signal CR is adjusted in level at a circuit 93 and then supplied to a subtracter 94 together with the output of the circuit 90 to derive therefrom a color component (R-Bsin~) on R-axis, or VRB-axis. These in-phase component VRB and quadrature component URB are alternately obtained at every 1/2fsc by a switchin~ circuit or data multiplexer 95 and thereafter supplied to a multiplier or sign inverter 96. The sign inverter 96 is supplied with a earrier fsc from the clock L
pulse generater 10, and performs multiplication of -1 at the former half of carrier period and multiplication of +l at the latter half of carrier period so that the eom-ponents VRB and URB are subjeeted to quadrature 2-phase modulation. L
The digital eolor modulation 41 provided in -the green ~ 12 ~
6~
signal system is also constructed as -the balanced modulator.
Accordingly, -the digita] color signal CG is supplied to circuits 97 and 98 where it is divided to a quadra-ture component URB and an in-phase component VI~B. These com-ponents are switched by a frequency 2fSC at a data multi-plexer 99 and then multiplied with the carrier ESc at a multiplier or sign inverter 100 to provide a digital modulated signal CG subjected to quadra-ture modulation.
A Eurther description for the above will be below given with reference to the modulator 41 of Fig. g, and Fig. 9B.
The input signal CG to the color modulator 41 (the signal CG has only an amplltude component and no phase component) is resolved into components on VRB-axis and URB-axis similarly as in Fig. 9A. In this case, the inpu-t signal CG provides video information which is advanced by T2 pitch of a color element from the signals CR and CB
delivered by -the R and B chips as shown in Fig. 1, so that it is expressed as ~' on the vector of ~`ig. 9B. That is, the signal G' is shown at a position which is delayed by 135 from the vector G of the actual green color. Accord-in~ly, in order to produce the green color signal CG
corresponding to the actual green color vector G, which is also actually subjected to quadrature 2-phase modulation, a delay time of TH/2 is necessary for ~R and CB. For this reason, as shown in Fig. 2, the delay line 105 of time TH/2, or 12-4f3 , is connected following to the mixer 43. In sc - this case, the clock pulse CKB from the clock pulse generator 10 is supplied to the D-A converter 102, while the same is supplied to a phase shifter 101 where it is phase-corrected by an amount for correcting ~/2 pitch and thus corrected - :13 -.
~L46~6~
pulse is fed to the D-A converter 109.
When producing the digital burst signal SB at the synchronizing signal generating circuit 24, since the burst signal is opposi-te in phase relative to U-axis, the burst signal is resolved into a component of R-axis ancl a com-ponent of its orthogonal axis and code words corresponding to respective axes are stored in a memory. Thus, if the above code words are selectively mixed at every l/4fsc, a desired digital burst signal SB can be produced. In the praetical case, a read-only memory is supplied with clock pulses of fsc and 2fSC, a burst flag pulse and a horizon-tal synchronizing pulse, the latter pulses being in synchronism with the former pulses. Thus, these pulses are logically operated to procluce the digital burst signal SB.
Figs. lOA through lOF are views used for explaining the operation of the modulator 21. That is, Fig. lOA shows the phase of a sub-carrier of NTSC signal. Fig. lOs illustrates the waveform of the signal of frequency 2fSC
for switching the multiplexer 95, ancl Fig. lOC shows-com-ponents of an output signal of the mul-tiplexer 95. ~aveform o~ a signal of frequency fsc for switching the sign inverter 96 is shown in Fig. lOD, and an output of the sign inverter 96 is depieted in Fig. lOE. It is noticed from Fig. lOE
that the output of the modulator 21 is a signal subjected to quadrature 2-phase modulation. Fig. lOE represents the phase of the digital burst signal fed to the mixer 25.
As deseribed above, aecording to this invention, the digital process eircuit system X from the CCD ehip 1 (or 2) to the filter device 6 (or 36) is proeessed by the sampling rate FS = ~3fse of CCD ehip 1 or 2, and the o-ther digital -- l'l -- .
~6~
process circuit system Y following to the circui-t system ~ is processed by the rate of FS' = ~fsc~ so that the digital process circuit system X wi-th low-s~eed operation can be used and hence a digital circuit which is inexpensive that much can be employed. Also, matchillg of process rates can be achieved by the D-D converter 20 which is relatively simple in circuit construction, so that there is no trouble in circuit design and i-t is quite suitable for the ;ntegrated circuit construction.
In the above eMbodiment, the process rate of the digital process circuit system Y is FS ~fsc' S sc also applicable. Also, in this embodiment, two-chip type television camera is used, but a single-chip type or three-chip type can a]so be used, that is, any television camera is applicable. Further, the semiconductor image sensing device is applicable not only to television cameras using CCD but also those using MOS-type sensor.
~ 15 -
Claims (7)
1. A solid state digital television camera having a solid state image sensing device from which dot sequential picture signals are picked up, said camera comprising:
a. a solid state image sensing device (1, 2) for picking up a picture and producing electrical video signals, said device being driven at a first sampling rate;
b. an A-D converter (3, 33) for converting said picked-up video signals to digital video signals at said first sampling rate;
c. a digital filter (6, 36) for filtering said digital video signals from said A-D converter, said filter being driven at said first sampling rate;
d. a digital color modulator or encoder (21, 41) for modulating a subcarrier signal in the respective carrier phases with primary color components (CR, CB, CG) produced from said filter individually, said modulator being driven at a second sampling rate;
e. a D-A converter (102, 104) for converting the out-puts of said digital color modulator to analog video signals at said second sampling rate; and f. a D-D converter (20, 40) located between said digital filter and said digital color modulator for converting the sampling rate of said primary color component signals from said first sampling rate to said second sampling rate which is higher than said first sampling rate.
a. a solid state image sensing device (1, 2) for picking up a picture and producing electrical video signals, said device being driven at a first sampling rate;
b. an A-D converter (3, 33) for converting said picked-up video signals to digital video signals at said first sampling rate;
c. a digital filter (6, 36) for filtering said digital video signals from said A-D converter, said filter being driven at said first sampling rate;
d. a digital color modulator or encoder (21, 41) for modulating a subcarrier signal in the respective carrier phases with primary color components (CR, CB, CG) produced from said filter individually, said modulator being driven at a second sampling rate;
e. a D-A converter (102, 104) for converting the out-puts of said digital color modulator to analog video signals at said second sampling rate; and f. a D-D converter (20, 40) located between said digital filter and said digital color modulator for converting the sampling rate of said primary color component signals from said first sampling rate to said second sampling rate which is higher than said first sampling rate.
2. A solid state digital television camera having a solid state image sensing device from which dot sequential picture signals are picked up, said camera comprising:
a. a solid state image sensing device (1, 2) for picking up a picture and producing electrical video signals;
b. an A-D converter (3, 33) for converting said picked-up video signals to digital video signals;
e. a digital filter (6, 36) for filtering said digital video signals from said A-D ccoverter;
d. a digital color modulator or encoder (21, 41) for modulating a subcarrier signal in the respective carrier phases with primary color components (CR, CB, CG) pro-duced from said filter individually;
e. a D-A converter (102, 104) for converting the out-puts of said digital color modulator to analog video signals; and f. a D-D converter (20, 40) located between said digital filter and said digital color modulator for converting the outputs of said digital filter with a sampling drive rate of to the digital video signals with another sampling drive rate of p?fsc where fsc is a color subcarrier, p is 3 or 4, and m and n are substantially small numbers, in which said A-D converter (3, 33) and said digital filter (6, 36) are driven at a sampling rate of , while said D-D converter (20, 40), digital modulator (21, 41) and said D-A
converter (102, 104) are driven at a sampling rate of p?fsc.
a. a solid state image sensing device (1, 2) for picking up a picture and producing electrical video signals;
b. an A-D converter (3, 33) for converting said picked-up video signals to digital video signals;
e. a digital filter (6, 36) for filtering said digital video signals from said A-D ccoverter;
d. a digital color modulator or encoder (21, 41) for modulating a subcarrier signal in the respective carrier phases with primary color components (CR, CB, CG) pro-duced from said filter individually;
e. a D-A converter (102, 104) for converting the out-puts of said digital color modulator to analog video signals; and f. a D-D converter (20, 40) located between said digital filter and said digital color modulator for converting the outputs of said digital filter with a sampling drive rate of to the digital video signals with another sampling drive rate of p?fsc where fsc is a color subcarrier, p is 3 or 4, and m and n are substantially small numbers, in which said A-D converter (3, 33) and said digital filter (6, 36) are driven at a sampling rate of , while said D-D converter (20, 40), digital modulator (21, 41) and said D-A
converter (102, 104) are driven at a sampling rate of p?fsc.
3. A solid state digital television camera according to claim 2, wherein said digital filter (6, 36) is a two-dimensional spatial filter (7) acting as a vertical interpolator for the line alternating signal.
4. A solid state digital television camera according to claim 2, wherein said primary color components (CR, CB, CG) are rate-converted into 4fsc by said D-D converter while said numbers m and n are 3 and 1, respectively, and p is 4.
5. A solid state digital television camera according to claim 2, wherein said digital modulator is a quadrature-phase balanced modulator performed by alternately multi-plexing in-phase components (VRB) and quadrature components (URB) every 1/4 subcarrier period by the clock frequency 2fSC and by alternately inverting the sign of them every 1/2 subcarrier period by the clock frequency fsc.
6. A solid state digital television camera according to claim 2, further comprising a gamma correction circuit (50) using a read-only memory operated at the sampling drive rate of .
7. A solid state digital television camera according to claim 2, wherein said image sensing device (1, 2) is composed of two sensing images, one for picking-up red and blue color signals and the other for picking-up green color signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1066980A JPS56107682A (en) | 1980-01-31 | 1980-01-31 | Color image pickup equipment |
| JP10669/80 | 1980-01-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1146264A true CA1146264A (en) | 1983-05-10 |
Family
ID=11756644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000369623A Expired CA1146264A (en) | 1980-01-31 | 1981-01-29 | Solid state digital television camera |
Country Status (8)
| Country | Link |
|---|---|
| JP (1) | JPS56107682A (en) |
| AT (1) | AT380612B (en) |
| AU (1) | AU538956B2 (en) |
| CA (1) | CA1146264A (en) |
| DE (1) | DE3103216C2 (en) |
| FR (1) | FR2475337A1 (en) |
| GB (1) | GB2069795B (en) |
| NL (1) | NL191966C (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3482366D1 (en) * | 1983-07-21 | 1990-06-28 | Victor Company Of Japan | COLOR TELEVISION CAMERA WITH TWO OR MORE FIXED BODY IMAGING DEVICES. |
| JPS60204191A (en) * | 1984-02-29 | 1985-10-15 | ア−ルシ−エ− コ−ポレ−シヨン | Digital signal processor for color television cameracircuit |
| JP2611269B2 (en) * | 1987-10-23 | 1997-05-21 | ソニー株式会社 | Signal processing device for solid-state imaging device |
| JPH01227510A (en) * | 1988-03-07 | 1989-09-11 | Mitsubishi Electric Corp | Clamping device |
| JPH02152574A (en) * | 1988-12-02 | 1990-06-12 | Hirano Tecseed Co Ltd | Lip coater type coating device |
| AU641938B2 (en) * | 1989-10-04 | 1993-10-07 | Sony Corporation | Signal processing circuit for a solid state imaging apparatus |
| JP3272000B2 (en) * | 1991-07-23 | 2002-04-08 | キヤノン株式会社 | Signal processing device |
| JP2811647B2 (en) * | 1991-09-24 | 1998-10-15 | 日本ビクター株式会社 | Digital color difference signal modulation method |
| EP0592005B1 (en) * | 1992-10-09 | 1999-09-01 | Sony Corporation | Solid state image pick-up apparatus with digital output signal rate conversion |
| DE69429677T2 (en) * | 1993-03-19 | 2002-08-14 | Canon Kk | Digital video camera and recording device |
| JPH07327237A (en) * | 1994-05-31 | 1995-12-12 | Victor Co Of Japan Ltd | Video signal processing circuit |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5914949B2 (en) * | 1976-03-30 | 1984-04-06 | ソニー株式会社 | signal processing device |
| JPS5394824A (en) * | 1977-01-31 | 1978-08-19 | Sony Corp | Carrier chrominance signal generator |
| JPS5444424A (en) * | 1977-09-14 | 1979-04-07 | Sony Corp | Solid state pick up unit |
| JPS5455324A (en) * | 1977-10-13 | 1979-05-02 | Sony Corp | Color pickup unit |
-
1980
- 1980-01-31 JP JP1066980A patent/JPS56107682A/en active Granted
-
1981
- 1981-01-22 AU AU66546/81A patent/AU538956B2/en not_active Expired
- 1981-01-29 GB GB8102694A patent/GB2069795B/en not_active Expired
- 1981-01-29 NL NL8100439A patent/NL191966C/en not_active IP Right Cessation
- 1981-01-29 CA CA000369623A patent/CA1146264A/en not_active Expired
- 1981-01-29 FR FR8101747A patent/FR2475337A1/en active Granted
- 1981-01-30 AT AT0043181A patent/AT380612B/en not_active IP Right Cessation
- 1981-01-30 DE DE3103216A patent/DE3103216C2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| NL8100439A (en) | 1981-09-01 |
| AT380612B (en) | 1986-06-25 |
| AU538956B2 (en) | 1984-09-06 |
| DE3103216A1 (en) | 1981-11-26 |
| GB2069795A (en) | 1981-08-26 |
| FR2475337A1 (en) | 1981-08-07 |
| JPS56107682A (en) | 1981-08-26 |
| NL191966C (en) | 1996-11-04 |
| GB2069795B (en) | 1983-10-05 |
| AU6654681A (en) | 1981-08-06 |
| FR2475337B1 (en) | 1985-01-04 |
| JPS6312434B2 (en) | 1988-03-18 |
| ATA43181A (en) | 1985-10-15 |
| DE3103216C2 (en) | 1986-12-11 |
| NL191966B (en) | 1996-07-01 |
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