CA1128212A - Apparatus for reformating a binary number - Google Patents

Abstract

SPECIFICATION OF
JERRY L. KINDELL
for COMPUTER APPARATUS

ABSTRACT OF THE DISCLOSURE
Computer apparatus implementing a single computer instruction for moving a binary number of from one to four characters, with the characters of a given binary number having either eight or nine bits per character, from storage in memory to a register. The characters of the binary number are stored in a word addressable memory with each word of memory being divided into four 9-bit bytes.
The most significant character of the binary number can be stored in any designated byte position of a word location with the characters of the number stored in contiguous byte locations in descending order of significance. The apparatus causes the binary number to be stored in a designated addressable register with the binary number being right justified in that register. Higher order bit positions of the register not needed to store the bits of the binary number will have stored into them fill bits or the sign bit of the number.

Description

~L2~ 2 SPECIFICATION OF JERRY L. KINDELL FOR
COMPUTER APPARATUS
BACKGROUND OF THE INVENTION
Field of ~he Invention 05 This invention is in the field of digital data process-- ing systems and more particularly relate~ to apparatus implementing an instruction for moving a binary number stored in a word addressable memory in a for~ which may be incompatible with the binary number being used as a binary number in computations and for storing the binary number in an addressable register in a form compatible with its being used or operated on as a pure binary number.
Description of the Prior Art Digital data processing ~ystems are optimzed to handle groups of a given number of bits in parallel, or as an entity, with a group of bits being defined as a word, or a machine word. A word in turn can be defined as including a plurality of bytes with each byte containing a given number of bits. There is no agreed to standard for the number of ; bits to a byte. Some computer equipment manu~acturers have s~andardized their equipment to use an 8 bit byte and others ~ to use a 9 bit byte. In this Application the word byte when ; used WithQUt a prefix or modifier will mean a 9 bit byte.
Some data processing system~ organize their memories, or working store, on the basis that each addressable memory location ~ore a machine word. Others are organized so that aach addres~able memoYy location will ~tore a byte most co~monly an 8 bit byte. Either type of co~puting ~ys~em when re~uixed to operate on, or proces~, bina~y ~~ 52027~5 ,r ' ' ' ' ' ' ' :

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numbers will generally restrict Qr limit a binary number to a given number of characters where a character in an 8 bit byte machine will be 8 bits, an octet, and in a 9 bit byte machine will be 9 bits, a non~t. A word oriented data 05 processing system having a word addressable memory with a word length o 36 bits is divisible into 4 bykes. To increase the ability of such a word oriented computer to compete with 8 bit byte oriented computers, it is desirable that such a word oriented computer be ~ble to run applica-10 tion programs written to run on a 8 bit byte character addressable memory computer. Such a word oriented computer should be able to handl~ binary numbers of one to four characters either octets or nonets. An advan~age der~ved by a computer having this capability is that it saves users 15 replacing a byte oriented computer with such a word oriented computer fxom having to rewrite their application programs. Such a conversion can be expensive and time consuming. However to provide a word oriented computer with the capability of handling binary numbers havin~ characters 20 of either 8 or 9 bits per character requires that the computer have the ability to store a binary number in a word organized memory location with the most significant character of the binary number f the one that contains the most significant bit of the bina~y number, in any of the 25 four byte positions of a given word location in memory with the remaining characters of the binary number being stored in adjacent byte positions in decreasing order of signifi-cance. Where 8 bit characters are stored in a 9 bit byte position, the most significant bit position of each byte 30 will have a fill bit, normally a zero, s~ored in it.
Depending upon the numb~r of charac~ers in a binary number and the byte location in which the most signif~cant ~haracter i~ stored the less significant characters of the 3 binary number may be ~tored in a ~ontiguous w~rd location '` 35 in memory, or across a word boundary.
Given a biaary number of from one to four characters -~ 52027S5 , ~

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with ~ach character o~ a given number having either 8 or 9 bits per character and with the characters being stored in a word addressable memory with the most significant charac~ex in any one of the byte positions of the given - 05 memoxy location, the problem is how to eficiently move the binary number from its addressable memory location or locations to an addressable register in the central processor of the æystem with the binar~ number positioned in the register so that it is ready to be processed, or operated on; i.e., added, subtracted, multiplied, divided, etc. with the bits of the number right justified with the least significant bit of the number in the least signifi-- cant bit position of the register and the more significant bits of the bina~y number stored in ascending order of significance from right to left. In addition with respect to some binary numbers it is also necessary to fill the higher order bit positions of the register not having stored into them a bit of the binary number either a fill bit or the sign bit of the number where the sign bit is the bit in the most significant bi~ position of the binary number. Heretofore, the manner in which this particular function has been performed has been by a software program.
Such a program requires a significant number of instruc-tio~s, each of which will re~uire ~everal clock periods to perform so that a ~ignificant amount of time is required to fe ch from memory the binary number and position it in a designated register ready for subsequent processing. The penalty in p~rfo~mance, measured in terms of throughput of a data processing system which must make such transfor-mations~ obviously adversely affects the ability of such adata processing system to compete effectively particularly in performing such programs compared to a data processing system organiæed to directly address the characters of the binary number.

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SUMM~RY OF THE IN~ENTION
The present invention provides apparatus ~or implementing a s~ngle instruction for moving a binary number of from one to our chaxacters where a character 05 can consiRt of either 8 or 9 bits from a word address~hl~
memory having four byte locations per word. Each byte location has 9 bit positions with the most significan~
character of the binary number being stored in any one o the four byte locations of the word. The instruction stores the binary number in a designated register with the binary number being right justified, i.e., with the lers~t significant bit of the numb~r stored in the least significant bit position of the reg~ster and the more significant bits of the number are stored in the register in order of increasing significance from right to left.
Any higher order bit position of the register in which no bit of the binary number is stored will have stored into them a fill bit or the sign bit of the binary number.
In response to the receipt of an in~truction, the control logic circuit means of the processor of the data processing system will fetch from memory the word or words in which are stored the characters of the binary nu~ber and will store the words in a double word data in register. The instruction contains the following information: the addre~s of the word in memory containing the most significant character of the binary number, the numbar of characters in the binary number, the byte position of th~ most significant character, whether the characters are octets or nonets, and whether the sign ~it of the binary number should be extended.
From this information the magnitude, the number of bits, that the data word~ stored in the data in register must be shi~ted by a shifter so that the byte containing the most significant character of the binary number ~ill be left jus~ified i~ dPtenminedO Th~ byte containing khe most 6ignifica~t ~har~cter an~ ~he remasning characters of the binary n~mber in order of decrea~ing significance ' `' ` ;

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are stored in an intermediate register capable of storing - one machine word. Knowing the number of characters of the binary number, the number o~ bits per character 8 or 9, the register into which the binary number is to be 05 placed, and whether the sign bit of the binary number i5 to be extended, the contents of the intermediate register are applied to a multi-position gated format switch. The position of the switch which is gated on, or selected places the bit~ o~ the binary number ~rom the intermediate register on the format switch output bus for storage in the designated addressable register with the bits of the binary number being right justified from right to left in order of increasing significance. Higher order bit positions will have stored into them the sign bit of the binary number if the instruction so provides or fill bits i~ it doesn't. The binary number in the designated register is in a form ready to ~e processed.
It is therefore an object of this invention to provide apparatus for implementing a single instruction for moving a binary numher of from one to four characters of either 8 or 9 bits per character stored in one or two word memory locations of a word addressable memory from memory and for storing them in a designated register with the binary number right justified ready for subsequent processing.
It is another object of this invention to provide apparatus for implementing a single instruction in a synchronous digital data processing system for moving a binary number of from one to four character of either 8 or 9 bits per character stored in one or two word locations in a word addressable memory to an addressable register with the binary number being right jus~ified ready for sub3equent processingO
It is another object of this inventlon to prsvide in a synchronous digital data proces~ing 5y8tem an instruction ~` : that replaces a ~oftware program for movlng a binary ~ number ~ored in memory to a register ready or subsequen~
- proces~ing in the minimum period of time.
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BRIEF DESCRIPTION OF THE DRAWINGS
Other objects, features and advantages of the invention will be readily apparent from the following description of certain pre~erred embodiments thereof, taken in conjunction with the accompanying drawings.
05 Although vaxiations and modifications may be e~fective without departing from the spirit an~ scope of the no~el concepts of the disclosure, and in which:
Figure 1 is a schematic block diagram of a portion of a central processor of a data processing system illustrat-ing the invention.
Figure 2 is the format of an instruction.
Figure 3 is a schematic block diagram of a portion ofthe control logic circuit means.
Figures 4 A-~ illustrate an example of the changes in format of a binary number as it is moved to an addressable registex.
Figures 5 A L illustrate the formats of words including characters of a binary number as applied to a format switch and the format of the binary n~mber on the format switch output bus for each position of the format switch.
Figure 6 is a schematic block diagram of a switching unit of a one of ten gated select switch.

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%8212 )ETAILED DESCRIPTION OF T~IE INVENTION
In Figure 1 only those elements of central processing unit ~CPU) 10 that are utilized in the execution of the move to register (MTR) instruction are illustrated. CPU 10 05 is a subsystem of a data processing 3ystem such a5 that illustrated in U.S. Patent ~4,000,487 which issued on December 28, 1976. The first step in moving a binary number from memory to a designated r~gister is for the control logic circuit means 11 illustrated in Figure 3 to issue a read command to the memory locations where the MTR
instruction is stored through the data out register RDO 12.
Since memory instruction preparation circuits including circuits to prepare the address of a word in memory are conventional and well known and form no part of this invention they are not illustrated. In response to such a read instruction being issued, the MTR instruction, a dou-ble word is transmitted from memory over the memory service bus ZRMS 13 and is stored in a two word register comprisin~
an instruction buffer RIB 14 fox storing an instruction word and descriptor register RDES 16 for storing a second word of the instruction which is also sometimes referred to as a descriptor. Each of re~isters 14, 16 is capable of storing a 36 bit machine word. The format of an instruc-tion 17 and a descriptor 18 are illustxated in Figure 2.
The address field, Y, bit positions 0-17 of descriptor 17 stored in register 16 is ihe address in memory of the word in which the most significant character of the binary nu~ber to be moved to a designated addressable register is stored. Field C, bit position~ 18-20 of descriptor 18 identifies or designates the byte position, or byte, of the word stored a~ mem~ry location Y in which the most significant character of the binary number is stored~ In the move to regis~er instruction ~ield C ha~ four possible values since a 36 bit word i~ divisible, or can contain, four bytes. The number of characters making up the number is designated by ~ield L bit po~ition~ 32-35 of descriptor 18. In the MTR instruction the maximum value of L is 520275~

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The operational code field, bit positions 18-27 of instruction 17 designates the instruction to be performed.
When field 18-27 of instruction 17 has the value which 05 designates the instxuction as being the MTR instruction, the address field Y of descripkor 18 is transferred to conventional address preparation circuit means 19 of the controller 11 and a memory read instruction is trangmitted from data out register RDO 12 to the memory ~f the system.
In respon~e to such a memory command the memory will apply to the memory service bus ZRMS 13, the 36 bits of the word stored in memory at address, or location, Y as specified in descriptor 18. This word is stored into the upper half RDI-U of the double word data in register RDI 20 by enabling switch position ~RMS-U 0-35 of a conventional multi position, or condition switch 22. The other positions of switch 22 are not illustrated since they are not used in implementing the MTR instruction. When the memory is ready to transmit over the memory service bus ZRMS 13 the word at memory location Y, the begin execution of instruction flip flop FGIN 24 of controller 11 illustrated in Figure 3 will be set by signals from conventional sources indicating the presence of an instruction in registers 14, 16 and a word being stored in a memory service register in the memory subsystem of ~he computer ~ystem ready to be applied to the regist r service bus ZRMS 13~ Circuits for detecting the presence of a word in a register are well known in the art and therefore are not ill~strated herein to simplify the illustration and the description. When 30 flip flop FGIN 24 is set, the upper half of switch 22, bit positions 0-35, will be enabled which causes the word on bus ZRMS 13 to be ~tored into the upper half RDI-U of the data in register 20, bit positions 0-35. The operation cod2, bit po~i~ions 18-27, of the instruction word s~ored in instsuction buffer 14 will have been ~pplied to the ~nstruction decoder 26 which will select conduc~or 27 by applying a logical 1 ~ignal to it repre~enting that the instruction ~T~ ha~ ~een applied to and d coded by decoder 52~2755 , ,.

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26. While a logical 1 signal is present on conductor 27, a logical l signal will be applied to one input terminal of thr~e input terminal And gates 28 A-C~ Clock signals from a conventional clock 30 are ap~ d to a ~econd 05 input terminal of each o~ the And gates 28 A~C since processor lO is a synchronous processor. ~hen flip ~lop 24 is set, it will apply a logical 1 signal to the third input terminal of gate 28A. With fli.p 10p 24 set and with a logical 1 signal on line 27 indicating the MTR
instruction has been decoded, the next clock pulse or signal from clock 30 will cause a logical 1 signal to be applied to the set terminal of flip flop FGMTRA 32 which will cause i~ to set. When flip flop 32 is set, control circuit 11 will have sensed the byte position Field C of descriptor 18, of the word stored in memory location Y containing the most significant character of the binary number and the number of su~h characters comprising the number from Field L of descriptor 18. From this information, control circuit ll determines if the binary number is stored across a word boundary, i.e., are one or more characters of the number stored into the next memory location having the adjaçent address of ~Y + l),for example. If the binary number is stored acros~ a word boundary, then the address preparation circuit means l9 of controller ll will issue another read instruction with the address of Y incremented by 1, or (Y + l). This word will be ~tored in the lower half RDI-L of RDI register 20, bit pos ' tions 36-71, by the ~ower half position ZRM$-L, bit positions 36-71 of switch ZRMS 22 being enabled. On the next clock signal, flip flop FGMTRB 34 will be set by a pulse from And gate 28 B. The output pul~e from gate 28 B
is applied to the reset te~minal F~MTRA 32 wh~ch resets ~lip flop 32.
When flip flop 34 is set,i~ cau~es the words stored 5 in data in reg~ster 20 to be appli~d through position ZRD~
of switch 36 to conventional ~hifter 38. The word in - 52~2755 ,:

~12~3212 the upper half RDI-U of register 20, bit positions 0-35 will be applied to shift~r 38 through the B operand bus Z~B 40 and the word, if any, stored in the lower half 05 RDI~L of register 20, bit positions 36-71 will be applied over A operand bus Z0SA 42 to shiter 38. Knowing rom Field C of descriptor 18 the byke positions of the word stored in the upper hal~ RDI-U o~ register 20 in which the most signi~icant character of the binary number is stored, and knowing that the number of bits per byte position is 9, control circuit 11 determines the magnitude of the shift that must be applied to the words stored in data in register RDI 20 to left justify the bytes containing the characters of the binary number so that the most signifi-cant character occupies the highest order byte position onshifter output bus ZSHF 43. Bus ZSHF 43 is a one word bus, i.e., it has 36 conductors, for carrying or transmitting 36 bits of information in parallel. The amount of shift applied to the signals applied to shifter 38 is equal to 9 (C - 1). For example, if the most significant character of the binary number is stored in the second byte position, then to left justify the bytes in which the characters of the binary number are present, it is necessary to shift the contents of register RDI 20 by 9 bit positions to the left.
Signals representing ~he nec2ssary amount, or magnitudeJ
of the shift are applied to shiter 38 from the control circuit 11 ~ver conductors which are not illustrated since they are conventional and well known in the axt ~nd would tend to make the illustration o~ the invention more complex and difficult to understand. The words applied ko shifter over Z0PB and Z0PA buses are shifted to the ~eft so that the byte containing the most significant character of the binary number is left justified A maximum number o~ four bytes containing ~haracters of the number are arranged in !35 decreasing order of significance from left ~o right will be present on, or applied to~ the shift output huseg ZSHF 43 ~of 36 bits and ~hrough switch position ZSHF of gated select 5~02755 ~ .

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2~L2 switch 44 will be applied to intermediate register RIM 46 which is enabled to store them by control signals from controller 11.
When the next clock pulse is produced by clock 30, And 05 gate 28C will be enabled which will set ~lip flop ~GMTRC 48 and reset FGMTRB 34. Whsn flip flop FGMTRC 48 is s~t, khe word stored in intermediate register RIM 46 will be applied to the intermediate register bus ZRIM 50 which is connected to format switch 52. Format switch 52 is a one of ten gated select switch which will change the format of the signals of the machine word applied to it from bus ZRIM 50 in such a manner as to right justify the binary number contained therein on shifter output bus ZFS 54.
The formats designated RIM-0, Figure 5A, and RIM-1, Figure SF, are the two formats of a binary number on bus ZRIM 50. In Figures 5 B-E ~nd 5 G-L the formats produced by each of the ten positions FS 0-9 are illustrated.
The position of switch 52 en~bled is determined from the information in the instruction words stored in registers 14, 16 of controllex 11. The type of character C, whether it's an 8 bit or a 9 bit character is identified by Field B, bit position 22 of descriptor 18 and the number of characters comprising the binary number is specified by Field L, bit positions 32-35 of descriptor 18. The sign extended field SE, bit position 21 of descriptor 18 determines whether the sign bit, the most significant bit of the binary number is to be used to fill any higher order bit positions on bus ZFS 54 not needed or used to transmit the number. This information is used by control circuit 11 to select which switch position FS 0-9 is to be enabled.
In addition the addrassable register to which the binary number, ~he signals on format switch output ~us 54 is to be stored is ~pecified in Field RECR, bit positi~ns 14-17 of instructio~ 17. Eight of the ~en directly addressable registers in the preferre~ embodime~t are index registers RX 0-7 which are half word registers,; i.e., capable of g202755 ~ ~ .
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storing only 18 bits or a half word. The other addressable registers are the A register RA 60 and the Q register RQ 62 each a full word register. A further restriction is that if the binary number is to be stored in registers RX O, 1, 05 4, or 5 of register bank 56, then the binary number can have at most two characters C and these two characters must be placed on the conductors of the upper half ZFS-U of bus ZFS 54 bit positions 0-17. If the one or two characters of the binary number are to be stored in index registers RX 2, 3, 6, and 7, the characters have to be placed on the lower half ZFS-L of bus ZFS 54, bit positions 18-35. Thus, the register into which the binary number is to be placed, the number of characters in the number, and whether the characters are 8 or 9 bit char~cters determines which switch position of format switch 52 is to be enabled.
As the hinary numbers are applied to the format switch output bus 54 by the format switch 52, they are right justified to a word or half word boundary with the bits of the binary number in order and with the least significant bit in the least significant bit position whether the binary number is made up of 1, 2, 3 or 4 characters. If the sign extension field SE is a logical one, then the sign extension circuit 64 will provide a logical one in the higher bit position~ of bus ZFS 54, if the bit positions are not used to store bits of the binary number and if the most significant bit of the binary number is a 1. Circuit 64 will apply a 0 to these positions if the most significant bit of the binary number is a 0. If the sign extension bit is a 0 then the sign extension circu~t 64 will provide a 0 or a fill bit in any h~gher order bit position of bus 54 not naeded for applying the bits of a binary number to the re~isterO The signals on the format switch output bus 54 are appli~d through ,~ switch 6~ and bus ZB-67 to regi~ters RX 0-7, RA, and RQ.
The regi~ter des~gnate~ by field RECR of i~str-lction 17 - will be enabled by control signals from controller 11 to ' ~'~

l~Z82:~2 store the bits on the conductors of bus ZB 67. The binary number stored in registers RX 0-8, RA and RQ will be in the proper format so that it can be applied to the binary arithmetic unit of CPU 10 for examp~e. When the 05 next clock pulse is produced by clock 30, ~inish of in~truction flip flop FG0F 68 will be ~et by the clock pulse from clock 30 enabling ~nd gate 70 which resets FGMTRC 48 and the setting of FG0~ signals the completion of the instruction. Control logic circuit means 11 is then ready to implement the next instruction to be stored in instruction registers 14, 16.
In Figure 4 an example of the transformations that occux to words stored in two m~mory locations ~ and Y~l in implementing the move to register instruction until the lS binary number which was stored in these two locations in memory i~ stored in an addxessable register RA or RQ or RX 0-7 is illustrated. For the purposes of this explanation, it is assumed that a binary number having three characters C 0, C 1, and C 2 and that its most significant character C 0 is stored in byte location B2, bit positions 18 through 26. Since the number of characters C comprising the number is 3, in the example,the binary numher extends across a word ~oundary between words which had been stored at locati~ns Y and Y ~ 1. The 36 bit word from memory location Y will be stored in the upper half RDI-U of data in regi~ter RDI 20,bit positions 0-35,and the word from memory location Y ~ 1 will be stored in the lower half RDI-L of register RDI 20,b~t positions 36-71,as seen in Figure 4A. The characters o~
the binary numbers i~ this example have 8 bits, or are octets, and are designated by C. A 9 bit character will be designated by C'. The first ~t@p in implementing the m~e to register in~truction, left ju~tifie~ the bytes containing characters of the binary number 80 ~hat 35 the bytes are leflt justified when stored into intermediate -- regi~ter ~1~ 46, Figure 4B. Field C of descriptor 18 52027~5 .
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illustrated in Figure 2 designates the byte positions of the word stored at location Y which contains the most significa~t charact~r C O. The number of bit positions that the contents of data in r~gister RDI 20 must be 05 shifted to the left is equal to 9(C-l), or 18 bits in this example,~o that i the content5 o~ register RDI 20 are shifted to t~e left 18 bit positions, byte B 2 containing the most significant character C O will be left justified when stored in register RIM 46 as seen in Figure 4B. Up to this point in implementing the instruc-tion, no distinction is made whether the characters of the binary number are octets or nonets.
Knowing that the characters C of the binary number ar~ octets which is designated by the field B bit position 22 of descriptor 18, the number of charactexs designated by field L and the register into which the binary number is to be stored which i~ designated by bit positions 14-17 of instruction 17, controller 11 selects the 1 of 10 gated select format switch 52 position which when enabled or selected will cause the three characters C O, C 1, and C 2 of the binary number to be right justified on format switch output bus ZFS 54.
Referring to Figure 5, it is seen that this would be switch po.~ition FS-5 in the example illustrated in Figure 4. With switch position FS-5 being enabled by control signals from controller ll,the fill bits in bit positions 0, 9 and 18 of the word stored in regi~ter RIM
will be eliminated, i.e., not connected to output bus ZFS 54 and the character C 2 will be positianed so that when stored in register RA for example the least signi~icant bit of ~hara~ter,C'~, b~t 26, will be right justified, io2~ ~ will be in bit position 35 with the remaining bits of the characters C O, C 1, C 2 being arranged in order of increasing ~ignifi~ance from righ~
to left ~c illu~trated in ~igure 5H. If the sign exte~ion bit Field 5E, bit po~ition 21 o~ ~he descriptor , ~ ' .
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' --15- ~ 1 2 ~ 2.12 18 is a logical 1 then the balance of the more sig-nificant bit positions SX on bus ZFS 54, bit positions O through 11 in this example, will have the same binary ~alue as that of the most signiicant bit of the OS binary number; namely the bit in bit position 12. If the sign extension bit is a zero then the~sign extension bits 0 through 11 will have stored into them fill bits, logical zeroes.
The MTR instruction identifies the register into which the right justified binary signal is to be stored and controller 11 provides the necessary signals to enable the addressed register to store khe signals applied to it over bus ZB 67 as is well known. Registers RX O, 1, 4 and 5 are connected to bus ZB-U so that the conductors of the more significant bits on bus ZB 67, bit positions 0-18 can be stored into them. The lower half, ZB-L, the less significant bit positions of bus ZB-67, i.e., bit positions 18 through 35 are storable into registers RX 2, 3, 6 or 7.
In the example illustrated in Figure 4, the binary number has three characters, C 0, C 1, C 2 so that the binary number can only be stored into either of the full word registers RA~ RQ. When a binary number is stored into the addressed register, the binary number is right justified to either a full word or half word boundary with either a fill bit or the sign bit being stored into unused higher order bit positions of the addressed register depending upon the value of the sign extension bit in descriptor 18. The bi-nary number when stored in the register designated by the instruction word 17 is ready to b~ operated on by sub-sequent instruc~ions.
The need for the sign extension bit occurs becausethe binary arithm~tic units of processor 10 are designed to handle 36 bits in parallel. To avoid c~anging the internal structure of the processor, particularly ~uch units as the binary arit~metic unit when required to operate Oh binary numbers of less than 36 bits, ~nd ,:

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particularly if the binary numbers in the signed twos complement notation the uee of 8ign extension bits is necessary to avoid the introduction of possible computational errors as is well known.
05 The format of a 36 bit word identified as RIM-0 which is typical of the format of a word stored in the in~ermediate register RIM 46 when the binary number is composed of 9 bit characters is illustrated in Figure 5A.
When stored inko register RIM ~6 the binary number is left justified so that the characters C 0-3 will be positioned as illustrated in Figure SA. It should be noted that there are no fill bits present when the characters of the binary number are nonets. When the format switch 52 is placed in its 0 condition, FS-0, the contents of the intermediate register 46 are applied to the format ~witch output bus ZFS 54 without change. If the number of characters C' of the binary number is 3, then the control signals applied to switch 54 by control circuit 11 will enable or select position FS 1 with the result that only the three most significant characters C'0, C-~l, and C~2 will be applied to bus CFS 54 and be stored into a designated register RA or RQ. If the sign axtension bit is a 1, then bit positions 0 through 8 will be the same as the binary signals stored in bit position 9. If the binary numbers stored in register RIM has only two characters, C'O, and C'1 t~en format switch 52 will be put in its condition designated as FS-2 illustrated in Figure 5 D
which causes the two characters C~ 0 and Cl 1 to be right justified. If the sign extension bit is a 1 then bit positions 0 through 17 will have the same valu~ as bit position 18.
If only the first, or most signifi~ant, 9 bit character C~ 0 is to be u~ed and stored in a desi~nat~d regi~ter, then switch po~ition FS 3 will be enabled and the format of ~he ~ignals on bus F5 54 will be as illu trated in Figure 5 E. If the 8tgn sxten~ion bit is 520~755 .
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a 1 then bit positions 0-26 will ha~e the same value as that of the bit in position 27.
If the binary number consists of not more than two characters and if the characters are to be stored in a 05 registex of index register bank 56 RX 0, 1, 4 ~nd 5,then switch position FS-0 will be enabled i~ there are kwo characters in the number which causes the first two characters C~0 and C'l to be in the upper half of the word, bit positions 0-18. If only one chàracter is to be stored in one of these four registers, switch position FS-l will be enabled. If the characters are to be stored in the lower half b.lnk of index registers 58, RX 2, 3, 6 and 7, then the switch position to be enabled or selected will be FS-2 if the binary number has two characters to the number, and FS-3 if the binary number has but one.
The format designated RIM-l in Figure 5 F illustrates the arrangement of characters C which are octets as they exist in intermediate register RIM 46 or as they are applied to bus ZRIM 50 after being left justified so that the most significant character C O will be in the most sig-nificant byte position B 0. Since the characters are octets, a fill bit designated by a diagonal line slanting from left to right will be stored in the most significant bit position of each byte storing a character, i.e., bit positions 0, 9, 18 and 27 of Figure 5F. If the binary number consists o~ four octets C 0~3, then format switch 52 will be put into its position, or condition, designated as FS-4 which will cause the four octets C 0-3 to be right justified with the least significant bit bit 35 of the number in bit position 35 and the most significaht bit of the number being in bit position 4 when the binary number is placed in on bus ZFS 54. Fill bits present in regi~ter RIM 48 will be elimina~ed so that the bits of the binary number are rrang~d in order . 35 of in~rea~ing signifi~ance from right to left a~ illu~trated : in Figure 5Gu If ~he sign extension bit i~ present, then 520275~
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., , 1~L2~3212 bit positions 0-3 will have the same value as bit position 4. If the binary number consists of three octets C 0-2, then switch 52 will be placed in its conditi~n FS-5 which will cause the binary number to be right justiied 05 with the least si~nificant bit 26 of the binary numbex in bit position 35 and the most significant bit o~ the - most significant character C 0, blt 1, in bit position 12 as seen in Figure 5 H. If the sign extension bit is a 1, then bit positions 0 through 11 will have the same value ~` 10 as the bits stored in bit location 12. If the binary number consists of two octets C O and C 1 then switch 52 will be placed in its condition corresponding to ~S-6, illustrated in Figure 5 I and the two characters C 0, C 1 will occupy bit positions 20-35,and if ~he sign extension bit is a 1, bit positions 0 through 19 will be the same as the bit stored in bit location 20. If the binary number is a single character octet C O, switch 52 will be placed in its condition FS-7, see Figure 5 J,and the format of the signals on bus ZFS 54 will ~e as illustrated in Figure 5 JO If the sign extension bit is a 1, bit positions 0 through 27 will have the same value as bit position 28.
As pointed out above if one wants to store a half word into the bank of registers 56, the ~its of the half word must be placed on the conductors,bits 0 through 17, of buæ ZFS-54 and switch position FS-8 will be ~nabled which puts the t~o charac~ers C O, C 1 in the upper half of a word ready for storage in whichever one of registers RX O, 1~ 6, or 7 is enabled pursuant to the designation o~ th~ addressable register in field RECR of instruction 17.
If the sign extension bit is a 1 or is present, then when switch 52 is in condition ~S~8, bit positions 0 and 1 will have the same value as the bit s.ored in bit position . 2. If switch 52 i~ in condit~on FS-9, only a ~i~gle octet C O will be present and right justified against ; the half word boundary 71 between b~t positions 17 and 18.
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If the sign extension bit is a 1 the bit stored in bit locations 0 through 9 will be the same as that stored in bit position 10 as illustrated in Figure 5 L.
Figure 6 i9 a block diagram of a 1 o~ 10 gated select Os switching unit 72 of format switch 52 that selects which one of ten logic signals applied to the input terminals D 0-9 will be connected to and appear at switching units 72 outpu~ terminal Z0. Terminal Z0 is then connected to one conductor of switch output bus 54, the most significant bit position, bit position 0 for example.
Since a machine word in the preferred embodiment has 36 bits,switch 52 has 36 of switching units 72. Each unit 72 is provided with ten five input And gates 74 0-9.
Which one of And gates 74 0-9 will be enabled is determined by gate select control signals Sl, S2, S4 and S8 from the source of control signals 11. The signals Sl, S2, S4 and S8 are applied respectively to conventional amplifiers or buffer circuits 76 0-3. Amplifiers 76 0-3 produce as their output signals control signals Sl, S2, S4 and S~ and ~ and ~. Contr.ol signals Sl, S2, S4 and S8 and their complement~ ~, S2, ~ and ~ are applied to four of the input terminals of each of the five input And yates 74 0-9 so that only one of the gates 74 0-9 can be ~elected or enabled at any one time. Which one of the And gates 74 0-9 is enabled is determined by the binary value~ of Sl, S2, S4 and S8 at any given moment.
The other input terminals of each of And gates 74 0-9 is connected, respectively, to one of input terminals D 0-9 to which input termi~als are applied logic signals or bits on bus ZRIM 50 or signals from ~he ~ign extension circuits 64. In addition to the gate select control ~ignals Sl, S2, S4 and S8 applied to ~he amplifier rirCuits 76 0 3; enable logic signals E~ and EB are applied to enable And ~ate 78, the o~pu~ si ~ al of ~nable ga~e 70 is applied to an input terminal of ou~put And gate ~O. Gate~ 78 and 80 are, in ~he preferred embodiment, ~wo i~put terminal And ~a~es.
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' '' ' ' -20~ 2 Gate 80 produces as its output the signal ZO and its inverted or complemented output ZO. Depending upon ~he values of Sl, S2, S4 and S8 and if the enable signals EA
and EB are pre~ent, then the signal applied to the 05 selec~ed one of the input terminals D 0-9 o~ unlt 72 wlll be present or appear at output terminal ZO and khus in bit position 0, the most signi~icant bit position o shifter output bus ZSF54.
In Figures 5A-F the bits of a machine word are iden-tified. The bit positions of the characters of thebinary numbers on bus ZRIM 50 for each position of format switch 52 are located within the output formats, Figures 5 B-E and 5 G-L. The sign extension bits SX will be connected to the sign extension circuit 64. It is believed well within the capabilities of those skilled in the art based on the information provided that one can connect the input terminals D 0-9 of the circuit switching units 72 to the appropriate conductors of the inter~.ediate bus ZRIM 50 and to the sign axtension circuit 64 to produce the formats on the binary numbers of output bus ZFS 54 for each of the ten conditions or positions of switch 52 as illustrated in Figure 5.
From the foregoing it is beli~ved obvious that this invention provides hardwaEs for implementing an instruc-25 tion that will quickly and reliably move a binary numberof from 1 to 4 characters 9 where a character can have either 8 or 9 bits, and in which ~he most significant character of the number can be stored in any byte position of a word to an addressable register. The bina~y number will be moved to a designated addressable register with the binary number being right justified and arranged in order with the least 6ignificant bit in the least significant bit position of the ragister and remaining ~its in thè binary nu~r arranged in order o~ increa~ing 35 æignificance Yrom right to left. ~he ~i~ bit of the binary n~mber can be ex~ended to fill the higher order ~20~755 .
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bit positions in the register if the sign extension bit of the descriptor is set, While the principles of the invention have now been made clear in an illustrated preferred embodiment, there will be many obvious modifications of the circuits in the components whioh can be made wikhout departing rom that principle. The apending claims are intended to convey such modifications.
Wh~t is claimed is:

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Claims (14)

C L A I M S
1. Claim 1. Circuit means for reformating a pure binary number comprising:
   a data in register adapted to have stored into it a first and a second word of n bits, the n bits of each word being divisible into p bytes of q bits per byte, where n, p and q are each integers other than zero; each of the p bytes adapted to contain a character of the binary number with each character having q or q-1 bits, the number of charac-ters of the binary number not exceeding p, the first word stored in the data in register containing the most signif-icant character of the binary number which character is stored in an identified byte position of the word stored in said register, the other characters of the binary number being stored in byte locations of decreasing significance;
   shifting means connected to the data in register for shifting the words stored in the data in register so that the byte of the first word containing the most significant character of the binary number is left justified and for storing the bytes of the words containing the remaining characters of the binary number in an intermediate register capable of storing a single word, the bytes containing the characters of the binary number being arranged in order of decreasing significance from left to right;
   format switch means for reformating the words stored in the intermediate register so that the bits of the binary number are right justified and for storing the binary number as reformated by the format switch in an addressable register.
2. Claim 2. The circuit means of Claim 1 in which the format switch means includes means for providing sign extension bits to fill the higher bit positions of the addressable register not used to store bits of the binary number,
3. Claim 3. The circuit moves of Claim 1 in which n = 36, p = 4 and q = 9.
4. Claim 4. In combination:
   a data in register adapted to store a first and a second word with each word having n bits, each word being divided into p bytes with each byte having q bits per byte;
   the words stored in the data in register containing a binary number of up to q characters with each character having q or q-1 bits per character, the most significant character of the number being stored in a byte of the first word;
   a source of control signals;
   a shifter;
   circuit means for applying the words stored in the data in register to the shifter, said shifter in response to control signals applied to it from the source of control signals producing a shifter output word by shifting the bytes of the first and second words so that the byte containing the most significant character of the binary number is left justified in the shifter output word and for storing the shifter output word in an intermediate register;
   a format switch having r positions and an output bus;
   circuit means for applying the shifter output word stored in the intermediate register to the format switch, said format switch in response to control signals from the source of control signals changing the format of the binary signals of said. word stored in the intermediate register into a format switch output word on the format switch output bus, said format switch output word having a pre-determined relationship to that of the word applied to the format switch, the format of the format switch output word on the format switch output bus being right justified with the least significant bit of the binary number in the least significant bit of the binary number in the least significant bit position and the bits of the binary number arranged in order of increasing significance;
   addressable register means;
   circuit means for applying the format switch output word on the format switch output bus to the addressable register means;
   a designated one of said addressable register means, responsive to control signal from the source of control signals for storing the format switch output word on the format switch output bus in said designated addressable register; and, a sign extended circuit connected to the format switch, said sign extended circuit responsive to control signals from the source of control signals for causing the sign bit of the binary number to be stored in the higher order bit positions of the addressable register not needed for storing the bits of the binary number.
5. Claim 5. The combination of Claim 4 in which n = 36, p = 4, and q = 9.
6. Claim 6. The combination of Claim 5 in which r = 10.
7. Claim 7. In combination:
   a source of control signals;
   a data in register adapted to store the binary signals of a first and second word, each word containing n bits with the bits being divided into p bytes, of q kits per byte;
   said data in register storing a first and second word containing a binary number of not more than p characters, at least one character of the binary number being positioned in a designated byte location of the first word and the remaining characters of the number being stored in contig-uous byte positions in order of decreasing significance from left to right in the data in register;
   
   an intermediate register;
   a shifter circuit connected to the data in register and responsive to control signals from the source of con-trol signals for shifting the bytes containing the charac-ters of the binary number stored in said data in register so that the byte containing the most significant characters of the binary number is left justified and for storing the bytes containing characters of the binary number in the intermediate register with the bytes containing characters of the binary number arranged in descending order of signif-icance from left to right;
   circuit means for storing the output of the shifter circuit into the intermediate register;
   addressable register means for storing a data word;
   and, a format switch connected to the intermediate register and responsive to control signals from the source of control signals for changing the format of the data word stored in the intermediate register so that the binary number is right justified;
   circuit means for storing the binary number in one of the addressable registers with the bits of the binary number being in order of increasing significance from right to left.
8. Claim 8. The combination of Claim 7 in which sign extension circuit means are connected to the format switch which when enabled by a control signal from the source of control signals will apply the sign bit of the binary number to the higher order bit positions in the addressable register not used to store bits of the binary number.
9. Claim 9. The combination of Claim 7 in which n = 36, p = 4, and q = 9
10. Claim 10. In combination:
    a data in register adapted to have stored into it a first and a second word with each word having n bits divided into p bytes with each byte having q bits where n, p, and q are integers other than 0; a binary number having q or (q-1) bits per character stored in the words with one character per byte, the character containing the most significant bit of the binary number being the most significant character;
    an instruction register adapted to have stored into it a first and a second instruction word;
    control means connected to the instruction register for producing control signals to implement an instruction stored in said instruction register, said control means in response to an instruction for moving a binary number from memory to an addressable register, producing control signals to implement said instruction words;
    shifter means connected to the data in register and responsive to control signals from the control means for shifting words containing the binary number applied to the shifter from the data in register a predetermined amount and in a predetermined direction to produce a shifter output word;
    an intermediate register for storing the shifter output word;
    a format switch having a format switch output bus connected to the intermediate register having r conditions and an output bus, said format switch means reformating the shifter output word applied to the format switch means so that the format of the signals of the format switch output word on the conductors of the format switch output bus have a predetermined relationship to the shifter output word applied to the format switch as a function of the condition of the switch;
    
    addressable register means connected to the format switch output bus and to the control means for storing the signals of the format switch output word on the format switch output bus in the enabled addressable register;
    said control means producing signals to cause the words stored in the data in register to be shifted to the left to left justify the bytes of the words containing the characters of the binary number so that the byte of the shifter output word containing the most significant charac-ter of the binary number is left justified and to cause the intermediate register to store the shifter output word; for producing signals to cause the shifter output word stored in the intermediate register to be applied to the format switch, to cause the format switch to be placed in the condition in which the bits of the binary number contained in format switch output word are right justified at a word boundary and to cause the addressable register designated by the institution to store the format switch output word on the format switch output bus.
11. Claim 11. The combination of Claim 10 in which the word boundary is a half-word boundary.
12. Claim 12. The combination of Claim 10 in which n = 36, p = 4, and q = 9.
13. Claim 13. The combination of Claim 12 in which r = 10.
14. Claim 14. The combination of Claim 10 in which a sign extension circuit is connected to the format switch for applying when enabled by a control signal from the control means the sign bit of the binary number to the conductors of high order bits of the format switch output bus not used to conduct bits of the binary number.