CA1121515A - Cache memory location selection mechanism - Google Patents
Cache memory location selection mechanismInfo
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- CA1121515A CA1121515A CA000317477A CA317477A CA1121515A CA 1121515 A CA1121515 A CA 1121515A CA 000317477 A CA000317477 A CA 000317477A CA 317477 A CA317477 A CA 317477A CA 1121515 A CA1121515 A CA 1121515A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
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- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
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Abstract
ABSTRACT
Apparatus and method for improving the operation of the assignment of the cache memory locations for data to be utilized by the central processing unit. In normal operation, sequential assignment of memory locations can designate a memory location which is unavailable for data storage, causing the reassignment of the data to the next storage location in the sequence. This potential multiple step assignment process can be eliminated by simultaneous examination of status signals, indicating memory location availability, and signals, identifying the last assigned memory location, to provide the next available memory location in the memory location sequence.
Apparatus and method for improving the operation of the assignment of the cache memory locations for data to be utilized by the central processing unit. In normal operation, sequential assignment of memory locations can designate a memory location which is unavailable for data storage, causing the reassignment of the data to the next storage location in the sequence. This potential multiple step assignment process can be eliminated by simultaneous examination of status signals, indicating memory location availability, and signals, identifying the last assigned memory location, to provide the next available memory location in the memory location sequence.
Description
52E2~i ~121~i15 BACKGROUND OF THE INVENTION
Field of the Invention This invention relates generally to a cache memory unit utilized by a data processing system and more particularly to an improved method of determining a location for the storage of data in the cache memory.
~escript~on of the Prior Art It is known in the prior art to utilize cache memories to provide improved performance in a data processing system. The performance of a data processing system is determined, at least in part, by the time required to retrieve data from a main memory location for use by the central processing unit. However, high speed memory units can be prohibitively expensive for storage of large amounts of data. As a compromise, a data processiny system can have a large and relatively inexpensive main memory for bulk storage of data and a smaller high speed memory, readily available to the centra1 processinunit. The small memory, referred to as the cache memory, stores only the data for which the central processing unit has an immediate requirement in order to continue operation.
The organization of the cache memory locations can be such that a group of memory locations is not completely defined until the entire main memory address of the data currently stored in the cache memory has been designated.
Thus a data group retrieved from memory is placed in one of a plurality of redundant (insofar as the cache memory address format is concerned) locations.
Eventually the redundant cache memory locations will all contain data and new data, required by the computer~ will begin to replace the old data.
In the prior art, there are two possible strategies for replacement of data in groups of locations in the cache memory. One strategy is to replace data which has remained unused in the group of memory ~ocations for the longest time. A less complicated strategy is to replace the data in the group by a sequential or "round-robin" technique. The present invention relates to the latter method.
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In the sequential or "round-robin" replacement algorithm~ the next memory location in the normal sequence may be unavai1able, for example, because of the detection of errors being introduced into the data as a result of being stored in that portion of the memory. This location unavailability would result in the necessity for de~ermining the next location address in the sequence. The determination of a new location can provide a delay, impacting the performance of the data processing unit.
It is therefore an object of the present invention to provide an improved apparatus for the assignment of a storage location in a cache memory unit.
It is a further object of the present invention to provide a group assignment for a cache memory apparatus that skips unavailable groups.
It is yet another object of the present invention to provide an assign-ment of a cache memory group based on a combination of sequential and of group availability signals.
It is still a further object of the present invention to manipulate simultaneously status signals, indicating the availability of cache memory groups, and signals indicating the sequential order of cache memory groups to determine the group in the sequence available for storage of data.
It is a more particular object of the present invention to provicle apparatus for the selection oF a sequential group in a cache memory unit, while simultaneously determining the next available location in the memory group to be utilized when the sequential group is unavailable.
Summary of the Invention The aforementioned and other objects are accomplished, according to the present invention, by apparatus associated with a data processing system which combines signals designating a sequential ordering of groups of cache memory cells with status signals, thereby selecting the next group in the sequence which is available for the storage of data.
The apparatus for performing this combining of signals consists of a storage unit, identifying the designated current cache memory storage group, a unit responsive to external status signals for designating any unavailable cache memory group, apparatus for determining the next available sequential storage group in the cache memory and means for replacing the former designated current cache memory group with the newly determined memory group designation.
The cache memory can have a multiplicity of locations 9 each location having a plurality of groups. Upon the addressing by the data processing sys-tem of a location in the cache memory unit, the apparatus provides the means for selecting the next group into which data can be stored.
The apparatus contains a network for sequential storage of data in the groups of a memory location after initiali~ations of the cache memory unit has erased all data stored therein.
In accordance with the present invention, there is provided in a data processing system including a cache memory unit having a multip]icity of addressable locations, all of said addressab]e locations including a plurality of circularly ordered memory element groups, apparatus for selecting a next ordered memory element group in said cache memory location for storage of data processing system signals, wherein said data processing system includes appara-tus for generating signals identifying an unavailable element group of said cache memory unit, comprising: first storage means coupled to said unavail-able group identification apparatus for storing said unavailable group signals identifying said unavailable group; second storage means coupled to said cache memory unit for storing signals identifying a most recently used memory group of s~id plurality of memory element groups; first means coupled to said first storage and to said second storage means for producing signals identifying ~3 Z~ >15 said unavailable element group location, wherein said unavailable memory ele-ment group signals are ordered with respect to said most recently used memory element group: second means coupled to said first means for identifying an available memory element group location ordered with respect to said most recently used memory element group location; and third means coupled to said second means and said most recently used group signal storage location means for providing signals specifying a next available memory element group in said memory element group sequential order.
In accordance with the present invention, there is further provided apparatus associated with a cache memory unit in a data processing system for selecting a next availab.le memory location from a plurality of sequential cache memory element locations having a common address, said data processing system including apparatus for developing signals identifying a location of unavailable groups of memory elements at a cache memory address location, comprising: first storage means coupled to said unavailable element location apparatus for storing said unavailable location signals identifying locations having unavailable elements; second storage means for storing signals identify-ing a most recently activated address location; incrementing means coupled to said second s:torage means for providing signals identifying a next sequential address location after said most recently activated address location; and availab.ility means coupled to said first storage means and said second storage means for combining signals from said first storage means and second storage means to provide signals identifying unavailable memory address locations in said location sequence, said unavailable location identifying signals applied to said incrementing meansy said incrementing means combining said availability means and signals from said second storage means to provide signals identifying a next available memory element location in said sequence.
In accordance with the present invention, there is further provided in association with a cache memory unit of a data processing system, said cache memory unit having a multiplicity of ordered memory element groups, said cac~e unit including apparatus for addressing a preselected one of said memory element groups, apparatus for selection a next memory element group into which ~, . , - 6a -~lZ~S~5 data processing signals are to be entered, said data processing system includ-ing apparatus for producing status signals relating to identified groups of each of said memory element groups, said status signals indicating the avail-ability of said identified element groups, comprising: means coupled to said addressing apparatus for storing signals identifying a most recently utilized memory element group in said sequence by said addressing apparatus; means coupled to said status signal apparatus for storing status signals relating to an availability of each memory element groups; and means coupled to said identifying signal storage means and said status signal storage means for com-bining said stored most recently utilized group signals and said stored status signals, said combining means identifying available memory element groups in said addressed sequence; and means coupled to said identiPying signal storage means, said combining means for producing signals addressing a next available sequential memory element group for storing said data processing system signals.
These and other features of the invention will be understood uponreading of the following description along with the drawings.
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BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a schematic block diagram of a data processing system utilizing a cache memory unit.
Fig. 2 is a schematic diagram of the address format utilized by the data processing system as organized for use in the cache memory unit.
Fig. 3 is a schematic block diagram of the cache memory storage unit showing the general organizational structure.
Fig. 4 is a schematic diagram of the selection apparatus for the cache memory locations.
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1~1515 DESCRIPTION OF THE PREFERRED EMBODIMENT
Detailed Description of the Figures Referring now to Figure 1, the general organization of a data processing system utilizing a cache memory unit is shown. A central processing unit 50 is coupled to a cache memory unit 100 and to a system interface unit 60.
The system interface unit is coupled to memory unit 70. The central processing unit 50, the memory unit 70, and the system interface unit 60 can be comprised of a plurality of individual units, all appropriately coupled and controlled for accurate execution of signal manipulation.
~0 Referring next to Figure 2, the format of a data address, comprised of 24 binary bits of data, utilized by a data processing system is shown. The first 15 most significant bits identify a page address of data. Each page address of data is comprised of 512 data words. In the present embodiment each word is composed of 40 binary data bits, this number beiny a matter of design choice.Of the 512 data words identified by the remaining 11 binary bits of each data page, each group of the next 7 binary bits of data is associated with a location of groups of memory storage cells in the cache memory and is a location address in the cache memory. That is, there are 128 memory locations in the cache memory, and each location is identified with a combination of binary bits in the second most significant bit assemblage. The four least significant bit assemblages of the address format, in the present embodiment, are not utilized in identifying a word address in the cache memory unit.
For efficient exchange of data between the cache memory unit and the memory unit, a block of four data words is transferred with each data transfer operation. Because the data transfer occurs in blocks, there is no need to utilize the least significant bits in identifying the transferred information to the main memory. The four words comprising the block will, in normal data transfer, always be present in any event. In the illustration in Fig. 2, the address format begins at bit position zero. However, this is a matter of design choice and other address formats can be utilized. Similarly, the address format can contain additional information, such as parity or status designations, when the address format is larger (i.e., than 24~ group of binary data bits.
5~5i Referring next to Fig. ~, a schematic block diagram of the principal components of a cache memory unit of a data processing system is shown. The data signals in the cache memory unit are stored in cache memory storage unit 101. This memory is comprised of random access memory devices in ~hich data signals can be both read or stored into addressed memory cells and extracted from addressed memory cells. The organization of the cache memory storage unit 101 is such that there are 128 locations, LOCATION O through LOCATION 127.
For each location, there are l~our groups of blocks of memory cells labelled BLOCK O through BLOQK 3. Each of the four blocks can contain four memory words labelled WORD O through WORD 3. Four data words from a selected block of a selected location in the memory storage unit 101 can be applied to the instruction buffer circuit 300 and for subsequent transfer to the data processing unit. Data signals are entered into the storage unit 101 by a data register 140, which is under the control of the cache memory control circuits 200. The cache memory control circuits 200 also control the address register 130. Address register 130 is coupled to the cache memory storage unit 101, the cache memory directory 102, and the cache memory directory control circuits 150. The cache memory directory 102 is divided into four blocks and each block contains 1~8 storage cells and structure in a manner similar to the storage unit 101, without, however, the additional WO~D structureThe cache memory directory i5 also comprised of random access memory circuits.
The contents of the blocks of an addressed location in the memory directory 102 are applied respectively to four comparison networks 111 through 114. The output signals of the comparison networks are applied to the data status decision network 120. The output signals of the data status decision network 120 can be applied to the four blocks of storage cells in the cache memory storage unit and to the four blocks of storage cells located in the cache memory directory in order to activate the block receivin~ the appropriate signals. The output siynals of data status decision network 120 are also 3Q applied to the cache memory directory control circuits 150. The address register 130 is also coupled to the four blocks of memory s~ells of the cache memory directory 102 and to the comparison networks 111 through 114. The .~9_ ~LZ ~ 5 ~LS
cache memory directory contro1 circuits 150 are divided into a directory control register and directory control circuits.
Referring next to Figure 4, the block selection network which is a part of the cache memory directory control circuit 150, is shown. The directory control register 151 is comprised of a plurality of address circuits 151A
which permits the addressing of 128 locations each capable of storing a plurality of data signals. The cache memory directory contro1 register is partitioned in groups which contain status information relating to the cache storage unit. The status signals include four signals assigned to full/empty indicators, (151B), four signals assigned to pending transfer indicators (151C),and two signals identifying the most recent or last access address (151D).
- These signals provide information concerning the four blocks of memory cells in the cache memory storage unit for each of the 128 locations.
The output circuits, with signals relating to the last access pointers, are coupled to the pointer register 152. The output signals of the pointer register 152 are applied to availability circuit 153 and to an incrementing circuit 155. The input terminals of the address block availability circuit 153 are also coupled to the output terminals of OR gate 154. The output signals of availability circuit 153 are coupled to a most significant zero detector circuit2- 156, and the output signals of the most significant zero detector circuit 156, are applied to an encoder 157. The output signals of encoder 157 are coupled to incrementing circuit 155. The output signals of the incrementing circuit 155 are coupled to switch 158. The output signals of switch 158 are applied to input circuits of the current pointer section 151D in the directory control register and also provide a directory write address enable signal.
In addition to the status bits stored in the directory control register, the block selection circuit also contains a four bit register 159 indicating the presence of a failing block of memory storage units. The failing block register 159 is coupled to OR gate 160 and to OR gate 154. The section of the control register 151 having the pending transfer indicators is also coupled to OR gate 154. The section of control registers 151 having the ~ull/empty indicators is coupled to OR gate 160. OR gate 160 ls coupled to initial ~Z~15~S
~11 availability register 161, while output signals of the initial availability register 161 is applied to the mos~ significant zero detector circuit 162 and while other output signals o~ register 161 are applied to switch 15~.
The most significant zero detector 162 is coupled to encoder 163 which in turn is coupled to switch 158. Switch 158 has control signals applied there-to to accommodate those operations where the results of block selection circuit are not need. Externally de~eloped signals are also applied to the pending transfer indicator section and the full/empty indicator section of the directory control register to provide the status information. The location address signal is received from address regis+er 130.
Operation of the Preferred Embodiment The basic use of a cache memory unit is to make available to the central processing unit data stored in the main memory unit without the wait normally associated with retrieval of the memory unit data. The cache memory is there-fore a high speed memory which contains data required with some immediacy by the central processing unit for uninterrupted operation. As shown in Fig. 1, the cache memory is electrically coupled to a central processing unit and to the system interface unit. Similarly, the central processing unit can be coupled directly to the system interface unit in certain data processing systems. The actual utilization of the electrical paths coupling the system components is dependent on the method of operation, for example, in some data processing systems data can be delivered directly to the central processing unit in certain circumstances. In other systems, the data required by the central processing unit must always be delivered to 'che cache memory unit before being transferred to the central processing unit. As will be clear to those s~illed in the art, there are a variety of methods by ~Ihich the data processing unit can utilize the cache memory for more eFfective operation.
In the preferred embodiment, an address format of the form shown in Fig. 2 is utilized for defining an address in the main memory unit. The most significant (15) bits, indicate a page address, the second most significant (~) bits indicate a location address, while the 2 least significant bits in con-junction with the other 22 bits identify a specific word or group of data signals stored in main memory. In the preferred embodiment, the least 52~
llZ1515 significant bits are not used by the main memory unit in normal operation. In the typical data transfer, four data yroups or words are transferred with the issuance of one instruction. Thus a-fter the central processing unit has developed the main memory address, only the 22 mcst significant bits are utilized and all of the four words thereby identified are transferred.
After the central processing unit has developed the address of the required data in main memory, that main memory address is delivered to the cache memory control circuits 200 and entered in address register 130.
At this point the cache memory control circuits 200 begin a directory search cycle. The directory search cycle searches for the address of the data requested by the central processing unit in the cache memory unit.
The main memory address is entered in address register 130 as the most significant 15 bits, the page address portion of the address is applied to ; 15 the four comparison registers 111 - 114.
Simultaneously the 7 bits of the location address portion of the main memory address are applied to the related one of the 128 locations in the cache memory storage unit, the cache memory directory 102 and the cache memory directory control register of the directory control circuits. The location address enables circuits containing four blocks of data in the cache directory and the directory contents are applied to comparison circuits 111 - 114. The contents of the 4 blocks of the cache directory are 15 bit page main memory addresses. Thus, when the page address portion of the ~ain memory address in the address register is found in one of the four blocks of the cache directory, a "hit" signal is applied to the data status decision network 12C. The "hit"
signal indicates that the desired data is stored in the related block of the same location address in the memory storage unit.
The location address portion of address register 130 , when applied to the directory control circuits 150, enables the resister cell storing status signals and applies these status signals to the decision network 120. In the preferred embodiment, types of status signals utilized are as fGllows: 1) a full/empty indicator whlch is a positive signal when valid data is stored in S~5 the corresponding cache memory storage unit; 2) a pending bit indicator which is positive when data is in the process of being transferred from main memory to the cache mernory storage unit so that page address has already been entered in the cache menlory directory; and 3) a failing block indicator ~Ihich is positive when the related one of the four blocks of memory storage ce11s has been identified as producing errors in data stored therein.
Assuming that the status signals are appropriate when a "hit" is determined by data status decision network, then the valid data is in the cache memory storage unit. The location address of address register 130 has enabled four blocks of data (each containing 4 words), related to the location address in the cache memory directory. The "hit" in page address one of the four blocks of the cache memory directory indicates that the four data words are located in the related block of the cache memory data storage unit. The data status decision network applies a signal to the appropriate block of the storage unit. The four required data words are deposited in the instruction buffer and are retrieved by the central processing unit.
The application of the location address signals to the directory control circuit causes this circuit to select the next block into which the data requested by the main memory should be stored. This determination is based on a first-in first-out replacement algorithm modified by the possible unavailabilit of memory locations as determined by the status signals. In the case of "hit", the block determination is not utilized. However, when a "miss" or absence of the requested data is identified by the data status decision network, the block identified by the cache memory directory control circuit is enabled by the data status decision network 120. The page address is then stored in the identified and enabled block of the directory and the appropriate pending bit signal is set in the directory control register 150. The cache memory control circuits then retrieve the four data words from the main memory address identified in address register 130 and the retrieved data is entered in data register 140. When the data words are available, the data is entered in the block of memory cells in the cache memory storage unit selected by the directory control circuits. Then the related pending bit signal is set to zero -13~
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in the directory control register. Depending on the requirements of the central processing unit, the data words can be immediately entered in the instruction buffer circuits for delivery to the central processing unit. If the data request was a pre-read, the data will remain in the cache storage unit until required by the central processing unit.
The selection circuit for determining the block of memory cells into which the data words retrieved from memory should be stored is shown in Fig. 4 and forms a portion of the cache memory directory control circuit.
The various status indicators are stored in the directory control register 151.
The current pointer 151D is a combination of two bits which identifies the address of the blocks (of the four~ in the sequential order last addressed and data stored therein. For each of the four blocks of the 128 locations, a register position is devoted to storing a pending transfer indicator bit (151C),and each of the four blocks of the 12~ locations has a full/empty indication bit position (151B) associated therewith. The failing block register has four positions to indicate when the usage of one of the four blocks (including any of the 128 location addresses of the block) is producing erroneous data.
When a directory search cycle is initiated, the location address portion of the address portion activates the location address in directory control register 151. For that location, the last access pointer indica-tors are transferred to pointer register 152. The pending transfer indicators and the failing block signals are combined in OP gates 154 and the combination is applied to availability circuit 153. The failing block signals and pending bit signals, if any, are entered in the availability circuit at appropriate locations. Pointer register 152 transfers to the availability circuit the block identification used for the most recent previous storage of data to the availability circuit.
The first most significant zero detector 15fi identifies the first zero in the circuit position following the position indicated by the last access pointer, the non-zero position identifying unavailable block identifications.
The displacement of this first zero position from the position indicated by the pointer is encoded and applied to the incrementing circuit 155. The position ~z~
(and therefore the block) identified by the pointer register to the incrementing circuit 155 is incremented by the number received from the encoder 157, and the resulting position is the block address (0-3~ applied through switch 158 to enable the directory to store the page address in the 05 selected block and to enable the storage unit to store the four words from main memory in the selected block address. Thus, the selection apparatus provides a sequential first-in first-out selection of the next block of rnemory cells to be utilized at an addressed location. Should the next sequential block be unavailable, the next available block in the sequence will be identified by the incrementing circuit.
After initialization~ the block selection is determined in a somewhat different manner. The failing block register 151 contents and the full/empty indicator signals are combined in OR gates 160 and applied to initial avail-ability register 161. If any of the four (combined) signals is a zero, then the switch 158 is enabled to transmit the block address determined by encoder 163. The address determined by encoder 163 is determined from the position of the most significant zero in register 161. This position identifies the address of the block to be utilized in storage of data, and is transmitted to the last access pointer 151D portion of the cache directory control register, to the cache directory, and the cache data storage unit. As will be clear, in the absence of a failiny block the path involving the initial availability register 161 will be utilized after initialization until all of the full/empty bits have been set, then the alternate path to switch 158 will be utilized to select the next memory block for a given location.
It will be clear to those skilled in the art that the number of blocks of memory cells need not be limited to four, nor need the number of memory locations be limited to 128. Nor is there a requirement that the number of blocks be equalto the number of words transferred between the cache and the main memory for each operation.
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The above description is included to illustrate the operation of the preferred embodiment and is not meant to limit the scope of the invention.
The scope of the inventiDn is to be limited only by the following claims.
From the above discussion, many variations will be apparent to one skilled 05 in the art that would yet be encompassed by the spirit and scope of the invention.
What is claimed is:
Field of the Invention This invention relates generally to a cache memory unit utilized by a data processing system and more particularly to an improved method of determining a location for the storage of data in the cache memory.
~escript~on of the Prior Art It is known in the prior art to utilize cache memories to provide improved performance in a data processing system. The performance of a data processing system is determined, at least in part, by the time required to retrieve data from a main memory location for use by the central processing unit. However, high speed memory units can be prohibitively expensive for storage of large amounts of data. As a compromise, a data processiny system can have a large and relatively inexpensive main memory for bulk storage of data and a smaller high speed memory, readily available to the centra1 processinunit. The small memory, referred to as the cache memory, stores only the data for which the central processing unit has an immediate requirement in order to continue operation.
The organization of the cache memory locations can be such that a group of memory locations is not completely defined until the entire main memory address of the data currently stored in the cache memory has been designated.
Thus a data group retrieved from memory is placed in one of a plurality of redundant (insofar as the cache memory address format is concerned) locations.
Eventually the redundant cache memory locations will all contain data and new data, required by the computer~ will begin to replace the old data.
In the prior art, there are two possible strategies for replacement of data in groups of locations in the cache memory. One strategy is to replace data which has remained unused in the group of memory ~ocations for the longest time. A less complicated strategy is to replace the data in the group by a sequential or "round-robin" technique. The present invention relates to the latter method.
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In the sequential or "round-robin" replacement algorithm~ the next memory location in the normal sequence may be unavai1able, for example, because of the detection of errors being introduced into the data as a result of being stored in that portion of the memory. This location unavailability would result in the necessity for de~ermining the next location address in the sequence. The determination of a new location can provide a delay, impacting the performance of the data processing unit.
It is therefore an object of the present invention to provide an improved apparatus for the assignment of a storage location in a cache memory unit.
It is a further object of the present invention to provide a group assignment for a cache memory apparatus that skips unavailable groups.
It is yet another object of the present invention to provide an assign-ment of a cache memory group based on a combination of sequential and of group availability signals.
It is still a further object of the present invention to manipulate simultaneously status signals, indicating the availability of cache memory groups, and signals indicating the sequential order of cache memory groups to determine the group in the sequence available for storage of data.
It is a more particular object of the present invention to provicle apparatus for the selection oF a sequential group in a cache memory unit, while simultaneously determining the next available location in the memory group to be utilized when the sequential group is unavailable.
Summary of the Invention The aforementioned and other objects are accomplished, according to the present invention, by apparatus associated with a data processing system which combines signals designating a sequential ordering of groups of cache memory cells with status signals, thereby selecting the next group in the sequence which is available for the storage of data.
The apparatus for performing this combining of signals consists of a storage unit, identifying the designated current cache memory storage group, a unit responsive to external status signals for designating any unavailable cache memory group, apparatus for determining the next available sequential storage group in the cache memory and means for replacing the former designated current cache memory group with the newly determined memory group designation.
The cache memory can have a multiplicity of locations 9 each location having a plurality of groups. Upon the addressing by the data processing sys-tem of a location in the cache memory unit, the apparatus provides the means for selecting the next group into which data can be stored.
The apparatus contains a network for sequential storage of data in the groups of a memory location after initiali~ations of the cache memory unit has erased all data stored therein.
In accordance with the present invention, there is provided in a data processing system including a cache memory unit having a multip]icity of addressable locations, all of said addressab]e locations including a plurality of circularly ordered memory element groups, apparatus for selecting a next ordered memory element group in said cache memory location for storage of data processing system signals, wherein said data processing system includes appara-tus for generating signals identifying an unavailable element group of said cache memory unit, comprising: first storage means coupled to said unavail-able group identification apparatus for storing said unavailable group signals identifying said unavailable group; second storage means coupled to said cache memory unit for storing signals identifying a most recently used memory group of s~id plurality of memory element groups; first means coupled to said first storage and to said second storage means for producing signals identifying ~3 Z~ >15 said unavailable element group location, wherein said unavailable memory ele-ment group signals are ordered with respect to said most recently used memory element group: second means coupled to said first means for identifying an available memory element group location ordered with respect to said most recently used memory element group location; and third means coupled to said second means and said most recently used group signal storage location means for providing signals specifying a next available memory element group in said memory element group sequential order.
In accordance with the present invention, there is further provided apparatus associated with a cache memory unit in a data processing system for selecting a next availab.le memory location from a plurality of sequential cache memory element locations having a common address, said data processing system including apparatus for developing signals identifying a location of unavailable groups of memory elements at a cache memory address location, comprising: first storage means coupled to said unavailable element location apparatus for storing said unavailable location signals identifying locations having unavailable elements; second storage means for storing signals identify-ing a most recently activated address location; incrementing means coupled to said second s:torage means for providing signals identifying a next sequential address location after said most recently activated address location; and availab.ility means coupled to said first storage means and said second storage means for combining signals from said first storage means and second storage means to provide signals identifying unavailable memory address locations in said location sequence, said unavailable location identifying signals applied to said incrementing meansy said incrementing means combining said availability means and signals from said second storage means to provide signals identifying a next available memory element location in said sequence.
In accordance with the present invention, there is further provided in association with a cache memory unit of a data processing system, said cache memory unit having a multiplicity of ordered memory element groups, said cac~e unit including apparatus for addressing a preselected one of said memory element groups, apparatus for selection a next memory element group into which ~, . , - 6a -~lZ~S~5 data processing signals are to be entered, said data processing system includ-ing apparatus for producing status signals relating to identified groups of each of said memory element groups, said status signals indicating the avail-ability of said identified element groups, comprising: means coupled to said addressing apparatus for storing signals identifying a most recently utilized memory element group in said sequence by said addressing apparatus; means coupled to said status signal apparatus for storing status signals relating to an availability of each memory element groups; and means coupled to said identifying signal storage means and said status signal storage means for com-bining said stored most recently utilized group signals and said stored status signals, said combining means identifying available memory element groups in said addressed sequence; and means coupled to said identiPying signal storage means, said combining means for producing signals addressing a next available sequential memory element group for storing said data processing system signals.
These and other features of the invention will be understood uponreading of the following description along with the drawings.
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BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a schematic block diagram of a data processing system utilizing a cache memory unit.
Fig. 2 is a schematic diagram of the address format utilized by the data processing system as organized for use in the cache memory unit.
Fig. 3 is a schematic block diagram of the cache memory storage unit showing the general organizational structure.
Fig. 4 is a schematic diagram of the selection apparatus for the cache memory locations.
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1~1515 DESCRIPTION OF THE PREFERRED EMBODIMENT
Detailed Description of the Figures Referring now to Figure 1, the general organization of a data processing system utilizing a cache memory unit is shown. A central processing unit 50 is coupled to a cache memory unit 100 and to a system interface unit 60.
The system interface unit is coupled to memory unit 70. The central processing unit 50, the memory unit 70, and the system interface unit 60 can be comprised of a plurality of individual units, all appropriately coupled and controlled for accurate execution of signal manipulation.
~0 Referring next to Figure 2, the format of a data address, comprised of 24 binary bits of data, utilized by a data processing system is shown. The first 15 most significant bits identify a page address of data. Each page address of data is comprised of 512 data words. In the present embodiment each word is composed of 40 binary data bits, this number beiny a matter of design choice.Of the 512 data words identified by the remaining 11 binary bits of each data page, each group of the next 7 binary bits of data is associated with a location of groups of memory storage cells in the cache memory and is a location address in the cache memory. That is, there are 128 memory locations in the cache memory, and each location is identified with a combination of binary bits in the second most significant bit assemblage. The four least significant bit assemblages of the address format, in the present embodiment, are not utilized in identifying a word address in the cache memory unit.
For efficient exchange of data between the cache memory unit and the memory unit, a block of four data words is transferred with each data transfer operation. Because the data transfer occurs in blocks, there is no need to utilize the least significant bits in identifying the transferred information to the main memory. The four words comprising the block will, in normal data transfer, always be present in any event. In the illustration in Fig. 2, the address format begins at bit position zero. However, this is a matter of design choice and other address formats can be utilized. Similarly, the address format can contain additional information, such as parity or status designations, when the address format is larger (i.e., than 24~ group of binary data bits.
5~5i Referring next to Fig. ~, a schematic block diagram of the principal components of a cache memory unit of a data processing system is shown. The data signals in the cache memory unit are stored in cache memory storage unit 101. This memory is comprised of random access memory devices in ~hich data signals can be both read or stored into addressed memory cells and extracted from addressed memory cells. The organization of the cache memory storage unit 101 is such that there are 128 locations, LOCATION O through LOCATION 127.
For each location, there are l~our groups of blocks of memory cells labelled BLOCK O through BLOQK 3. Each of the four blocks can contain four memory words labelled WORD O through WORD 3. Four data words from a selected block of a selected location in the memory storage unit 101 can be applied to the instruction buffer circuit 300 and for subsequent transfer to the data processing unit. Data signals are entered into the storage unit 101 by a data register 140, which is under the control of the cache memory control circuits 200. The cache memory control circuits 200 also control the address register 130. Address register 130 is coupled to the cache memory storage unit 101, the cache memory directory 102, and the cache memory directory control circuits 150. The cache memory directory 102 is divided into four blocks and each block contains 1~8 storage cells and structure in a manner similar to the storage unit 101, without, however, the additional WO~D structureThe cache memory directory i5 also comprised of random access memory circuits.
The contents of the blocks of an addressed location in the memory directory 102 are applied respectively to four comparison networks 111 through 114. The output signals of the comparison networks are applied to the data status decision network 120. The output signals of the data status decision network 120 can be applied to the four blocks of storage cells in the cache memory storage unit and to the four blocks of storage cells located in the cache memory directory in order to activate the block receivin~ the appropriate signals. The output siynals of data status decision network 120 are also 3Q applied to the cache memory directory control circuits 150. The address register 130 is also coupled to the four blocks of memory s~ells of the cache memory directory 102 and to the comparison networks 111 through 114. The .~9_ ~LZ ~ 5 ~LS
cache memory directory contro1 circuits 150 are divided into a directory control register and directory control circuits.
Referring next to Figure 4, the block selection network which is a part of the cache memory directory control circuit 150, is shown. The directory control register 151 is comprised of a plurality of address circuits 151A
which permits the addressing of 128 locations each capable of storing a plurality of data signals. The cache memory directory contro1 register is partitioned in groups which contain status information relating to the cache storage unit. The status signals include four signals assigned to full/empty indicators, (151B), four signals assigned to pending transfer indicators (151C),and two signals identifying the most recent or last access address (151D).
- These signals provide information concerning the four blocks of memory cells in the cache memory storage unit for each of the 128 locations.
The output circuits, with signals relating to the last access pointers, are coupled to the pointer register 152. The output signals of the pointer register 152 are applied to availability circuit 153 and to an incrementing circuit 155. The input terminals of the address block availability circuit 153 are also coupled to the output terminals of OR gate 154. The output signals of availability circuit 153 are coupled to a most significant zero detector circuit2- 156, and the output signals of the most significant zero detector circuit 156, are applied to an encoder 157. The output signals of encoder 157 are coupled to incrementing circuit 155. The output signals of the incrementing circuit 155 are coupled to switch 158. The output signals of switch 158 are applied to input circuits of the current pointer section 151D in the directory control register and also provide a directory write address enable signal.
In addition to the status bits stored in the directory control register, the block selection circuit also contains a four bit register 159 indicating the presence of a failing block of memory storage units. The failing block register 159 is coupled to OR gate 160 and to OR gate 154. The section of the control register 151 having the pending transfer indicators is also coupled to OR gate 154. The section of control registers 151 having the ~ull/empty indicators is coupled to OR gate 160. OR gate 160 ls coupled to initial ~Z~15~S
~11 availability register 161, while output signals of the initial availability register 161 is applied to the mos~ significant zero detector circuit 162 and while other output signals o~ register 161 are applied to switch 15~.
The most significant zero detector 162 is coupled to encoder 163 which in turn is coupled to switch 158. Switch 158 has control signals applied there-to to accommodate those operations where the results of block selection circuit are not need. Externally de~eloped signals are also applied to the pending transfer indicator section and the full/empty indicator section of the directory control register to provide the status information. The location address signal is received from address regis+er 130.
Operation of the Preferred Embodiment The basic use of a cache memory unit is to make available to the central processing unit data stored in the main memory unit without the wait normally associated with retrieval of the memory unit data. The cache memory is there-fore a high speed memory which contains data required with some immediacy by the central processing unit for uninterrupted operation. As shown in Fig. 1, the cache memory is electrically coupled to a central processing unit and to the system interface unit. Similarly, the central processing unit can be coupled directly to the system interface unit in certain data processing systems. The actual utilization of the electrical paths coupling the system components is dependent on the method of operation, for example, in some data processing systems data can be delivered directly to the central processing unit in certain circumstances. In other systems, the data required by the central processing unit must always be delivered to 'che cache memory unit before being transferred to the central processing unit. As will be clear to those s~illed in the art, there are a variety of methods by ~Ihich the data processing unit can utilize the cache memory for more eFfective operation.
In the preferred embodiment, an address format of the form shown in Fig. 2 is utilized for defining an address in the main memory unit. The most significant (15) bits, indicate a page address, the second most significant (~) bits indicate a location address, while the 2 least significant bits in con-junction with the other 22 bits identify a specific word or group of data signals stored in main memory. In the preferred embodiment, the least 52~
llZ1515 significant bits are not used by the main memory unit in normal operation. In the typical data transfer, four data yroups or words are transferred with the issuance of one instruction. Thus a-fter the central processing unit has developed the main memory address, only the 22 mcst significant bits are utilized and all of the four words thereby identified are transferred.
After the central processing unit has developed the address of the required data in main memory, that main memory address is delivered to the cache memory control circuits 200 and entered in address register 130.
At this point the cache memory control circuits 200 begin a directory search cycle. The directory search cycle searches for the address of the data requested by the central processing unit in the cache memory unit.
The main memory address is entered in address register 130 as the most significant 15 bits, the page address portion of the address is applied to ; 15 the four comparison registers 111 - 114.
Simultaneously the 7 bits of the location address portion of the main memory address are applied to the related one of the 128 locations in the cache memory storage unit, the cache memory directory 102 and the cache memory directory control register of the directory control circuits. The location address enables circuits containing four blocks of data in the cache directory and the directory contents are applied to comparison circuits 111 - 114. The contents of the 4 blocks of the cache directory are 15 bit page main memory addresses. Thus, when the page address portion of the ~ain memory address in the address register is found in one of the four blocks of the cache directory, a "hit" signal is applied to the data status decision network 12C. The "hit"
signal indicates that the desired data is stored in the related block of the same location address in the memory storage unit.
The location address portion of address register 130 , when applied to the directory control circuits 150, enables the resister cell storing status signals and applies these status signals to the decision network 120. In the preferred embodiment, types of status signals utilized are as fGllows: 1) a full/empty indicator whlch is a positive signal when valid data is stored in S~5 the corresponding cache memory storage unit; 2) a pending bit indicator which is positive when data is in the process of being transferred from main memory to the cache mernory storage unit so that page address has already been entered in the cache menlory directory; and 3) a failing block indicator ~Ihich is positive when the related one of the four blocks of memory storage ce11s has been identified as producing errors in data stored therein.
Assuming that the status signals are appropriate when a "hit" is determined by data status decision network, then the valid data is in the cache memory storage unit. The location address of address register 130 has enabled four blocks of data (each containing 4 words), related to the location address in the cache memory directory. The "hit" in page address one of the four blocks of the cache memory directory indicates that the four data words are located in the related block of the cache memory data storage unit. The data status decision network applies a signal to the appropriate block of the storage unit. The four required data words are deposited in the instruction buffer and are retrieved by the central processing unit.
The application of the location address signals to the directory control circuit causes this circuit to select the next block into which the data requested by the main memory should be stored. This determination is based on a first-in first-out replacement algorithm modified by the possible unavailabilit of memory locations as determined by the status signals. In the case of "hit", the block determination is not utilized. However, when a "miss" or absence of the requested data is identified by the data status decision network, the block identified by the cache memory directory control circuit is enabled by the data status decision network 120. The page address is then stored in the identified and enabled block of the directory and the appropriate pending bit signal is set in the directory control register 150. The cache memory control circuits then retrieve the four data words from the main memory address identified in address register 130 and the retrieved data is entered in data register 140. When the data words are available, the data is entered in the block of memory cells in the cache memory storage unit selected by the directory control circuits. Then the related pending bit signal is set to zero -13~
52~
~lZi~
in the directory control register. Depending on the requirements of the central processing unit, the data words can be immediately entered in the instruction buffer circuits for delivery to the central processing unit. If the data request was a pre-read, the data will remain in the cache storage unit until required by the central processing unit.
The selection circuit for determining the block of memory cells into which the data words retrieved from memory should be stored is shown in Fig. 4 and forms a portion of the cache memory directory control circuit.
The various status indicators are stored in the directory control register 151.
The current pointer 151D is a combination of two bits which identifies the address of the blocks (of the four~ in the sequential order last addressed and data stored therein. For each of the four blocks of the 128 locations, a register position is devoted to storing a pending transfer indicator bit (151C),and each of the four blocks of the 12~ locations has a full/empty indication bit position (151B) associated therewith. The failing block register has four positions to indicate when the usage of one of the four blocks (including any of the 128 location addresses of the block) is producing erroneous data.
When a directory search cycle is initiated, the location address portion of the address portion activates the location address in directory control register 151. For that location, the last access pointer indica-tors are transferred to pointer register 152. The pending transfer indicators and the failing block signals are combined in OP gates 154 and the combination is applied to availability circuit 153. The failing block signals and pending bit signals, if any, are entered in the availability circuit at appropriate locations. Pointer register 152 transfers to the availability circuit the block identification used for the most recent previous storage of data to the availability circuit.
The first most significant zero detector 15fi identifies the first zero in the circuit position following the position indicated by the last access pointer, the non-zero position identifying unavailable block identifications.
The displacement of this first zero position from the position indicated by the pointer is encoded and applied to the incrementing circuit 155. The position ~z~
(and therefore the block) identified by the pointer register to the incrementing circuit 155 is incremented by the number received from the encoder 157, and the resulting position is the block address (0-3~ applied through switch 158 to enable the directory to store the page address in the 05 selected block and to enable the storage unit to store the four words from main memory in the selected block address. Thus, the selection apparatus provides a sequential first-in first-out selection of the next block of rnemory cells to be utilized at an addressed location. Should the next sequential block be unavailable, the next available block in the sequence will be identified by the incrementing circuit.
After initialization~ the block selection is determined in a somewhat different manner. The failing block register 151 contents and the full/empty indicator signals are combined in OR gates 160 and applied to initial avail-ability register 161. If any of the four (combined) signals is a zero, then the switch 158 is enabled to transmit the block address determined by encoder 163. The address determined by encoder 163 is determined from the position of the most significant zero in register 161. This position identifies the address of the block to be utilized in storage of data, and is transmitted to the last access pointer 151D portion of the cache directory control register, to the cache directory, and the cache data storage unit. As will be clear, in the absence of a failiny block the path involving the initial availability register 161 will be utilized after initialization until all of the full/empty bits have been set, then the alternate path to switch 158 will be utilized to select the next memory block for a given location.
It will be clear to those skilled in the art that the number of blocks of memory cells need not be limited to four, nor need the number of memory locations be limited to 128. Nor is there a requirement that the number of blocks be equalto the number of words transferred between the cache and the main memory for each operation.
-15_ lS
The above description is included to illustrate the operation of the preferred embodiment and is not meant to limit the scope of the invention.
The scope of the inventiDn is to be limited only by the following claims.
From the above discussion, many variations will be apparent to one skilled 05 in the art that would yet be encompassed by the spirit and scope of the invention.
What is claimed is:
Claims (8)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. In a data processing system including a cache memory unit having a multiplicity of addressable locations, all of said addressable locations including a plurality of circularly ordered memory element groups, apparatus for selecting a next ordered memory element group in said cache memory loca-tion for storage of data processing system signals, wherein said data process-ing system includes apparatus for generating signals identifying an unavail-able element group of said cache memory unit, comprising:
first storage means coupled to said unavailable group identification apparatus for storing said unavailable group signals identifying said unavail-able group:
second storage means coupled to said cache memory unit for storing signals identifying a most recently used memory group of said plurality of memory element groups:
first means coupled to said first storage and to said second storage means for producing signals identifying said unavailable element group loca-tion, wherein said unavailable memory element group signals are ordered with respect to said most recently used memory element group:
second means coupled to said first means for identifying an avail-able memory element group location ordered with respect to said most recently used memory element group location; and third means coupled to said second means and said most recently used group signal storage location means for providing signals specifying a next available memory element group in said memory element group sequential order.
first storage means coupled to said unavailable group identification apparatus for storing said unavailable group signals identifying said unavail-able group:
second storage means coupled to said cache memory unit for storing signals identifying a most recently used memory group of said plurality of memory element groups:
first means coupled to said first storage and to said second storage means for producing signals identifying said unavailable element group loca-tion, wherein said unavailable memory element group signals are ordered with respect to said most recently used memory element group:
second means coupled to said first means for identifying an avail-able memory element group location ordered with respect to said most recently used memory element group location; and third means coupled to said second means and said most recently used group signal storage location means for providing signals specifying a next available memory element group in said memory element group sequential order.
2. The apparatus of claim 1, further including means selecting memory element groups after initialization of said apparatus until all of said avail-able memory element groups contain data processing system signals.
3. The apparatus of claim 1 wherein said first storage means stores signals identifying a memory element group location for which there is an incomplete activity.
4. Apparatus associated with a cache memory unit in a data processing system for selecting a next available memory location from a plurality of sequential cache memory element locations having a common address, said data processing system including apparatus for developing signals identifying a location of unavailable groups of memory elements at a cache memory address location, comprising:
first storage means coupled to said unavailable element location apparatus for storing said unavailable location signals identifying locations having unavailable elements;
second storage means for storing signals identifying a most recently activated address location;
incrementing means coupled to said second storage means for provid-ing signals identifying a next sequential address location after said most recently activated address location; and availability means- coupled to said first storage means and said second storage means for combining signals from said first storage means and second storage means to provide signals identifying unavailable memory address locations in said location sequence, said unavailable location identifying signals applied to said incrementing means, said incrementing means combining said availability means-and signals from said second storage means to provide signals identifying a next available memory element location in said sequence.
first storage means coupled to said unavailable element location apparatus for storing said unavailable location signals identifying locations having unavailable elements;
second storage means for storing signals identifying a most recently activated address location;
incrementing means coupled to said second storage means for provid-ing signals identifying a next sequential address location after said most recently activated address location; and availability means- coupled to said first storage means and said second storage means for combining signals from said first storage means and second storage means to provide signals identifying unavailable memory address locations in said location sequence, said unavailable location identifying signals applied to said incrementing means, said incrementing means combining said availability means-and signals from said second storage means to provide signals identifying a next available memory element location in said sequence.
5. The apparatus of claim 4 further comprising:
means coupled to said cache memory unit for storing signals when a cache memory location has at least one failing element associated therewith, wherein said location failing element identifying means is coupled to said availability means, said availability means identifying a next available sequential cache memory address location at a location not having a failing element.
means coupled to said cache memory unit for storing signals when a cache memory location has at least one failing element associated therewith, wherein said location failing element identifying means is coupled to said availability means, said availability means identifying a next available sequential cache memory address location at a location not having a failing element.
6. In association with a cache memory unit of a data processing system, said cache memory unit having a multiplicity of ordered memory element groups, said cache unit including apparatus for addressing a preselected one of said memory element groups, apparatus for selection a next memory element group into which data processing signals are to be entered, said data processing system including apparatus for producing status signals relating to identified groups of each of said memory element groups, said status signals indicating the availability of said identified element groups, comprising:
means coupled to said addressing apparatus for storing signals identifying a most recently utilized memory element group in said sequence by said addressing apparatus;
means coupled to said status signal apparatus for storing status signals relating to an availability of each memory element groups; and means coupled to said identifying signal storage means and said status signal storage means for combining said stored most recently utilized group signals and said stored status signals, said combining means identifying available memory element groups in said addressed sequence; and means coupled to said identifying signal storage means, said combin-ing means for producing signals addressing a next available sequential memory element group for storing said data processing system signals.
means coupled to said addressing apparatus for storing signals identifying a most recently utilized memory element group in said sequence by said addressing apparatus;
means coupled to said status signal apparatus for storing status signals relating to an availability of each memory element groups; and means coupled to said identifying signal storage means and said status signal storage means for combining said stored most recently utilized group signals and said stored status signals, said combining means identifying available memory element groups in said addressed sequence; and means coupled to said identifying signal storage means, said combin-ing means for producing signals addressing a next available sequential memory element group for storing said data processing system signals.
7. The apparatus of claim 6 wherein said status signals can indicate a failing element at a cache memory group, an incomplete activity at a cache memory group, and a presence of valid data in a cache memory group.
8. In association with a directory control unit for use in a cache mem-ory unit of a data processing system, wherein said cache memory unit has a multiplicity of memory locations associated therewith, each of said memory locations having sequential groups of memory elements, said data processing system including apparatus producing status signals relating to each of said memory location groups, each location having first status signals identifying a memory group having valid signals from said data processing unit stored therein, second status signals identifying when a cache memory element loca-tion group is reserved for storage of data processing unit signals;
and third status signals identifying a failing group of cache memory elements, apparatus for determining a next memory element group in a cache memory location comprising:
first storage means coupled to said status signal producing appara-tus for storing said first, second and third status signals;
second storage means coupled to said cache memory elements location group for storing signals identifying a most recently used cache memory ele-ment location group;
first means coupled to said first storage means for combining said first and said third status signals describing a status of memory element groups associated with a preselected cache memory location, said first combin-ing means-producing signals identifying location groups available for storage of data processing system signals;
second means coupled to said second storage means and to said first combining means for combining signals identifying an available location group and signals identifying said most recently used location group said second combining means determining a next available location group in said memory element group sequence, when said first combining means identifies a group in said location group which is not available; and third means coupled to said first storage means for identifying an available memory element location group for replacing said most recently used location group signals with said available or said next available location group signals which does not contain valid data processing signals.
and third status signals identifying a failing group of cache memory elements, apparatus for determining a next memory element group in a cache memory location comprising:
first storage means coupled to said status signal producing appara-tus for storing said first, second and third status signals;
second storage means coupled to said cache memory elements location group for storing signals identifying a most recently used cache memory ele-ment location group;
first means coupled to said first storage means for combining said first and said third status signals describing a status of memory element groups associated with a preselected cache memory location, said first combin-ing means-producing signals identifying location groups available for storage of data processing system signals;
second means coupled to said second storage means and to said first combining means for combining signals identifying an available location group and signals identifying said most recently used location group said second combining means determining a next available location group in said memory element group sequence, when said first combining means identifies a group in said location group which is not available; and third means coupled to said first storage means for identifying an available memory element location group for replacing said most recently used location group signals with said available or said next available location group signals which does not contain valid data processing signals.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US85857577A | 1977-12-08 | 1977-12-08 | |
| US858,575 | 1977-12-08 |
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| CA1121515A true CA1121515A (en) | 1982-04-06 |
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| CA000317477A Expired CA1121515A (en) | 1977-12-08 | 1978-12-06 | Cache memory location selection mechanism |
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| JP (1) | JPS5489438A (en) |
| AU (1) | AU523670B2 (en) |
| CA (1) | CA1121515A (en) |
| DE (1) | DE2853165A1 (en) |
| FR (1) | FR2411465B1 (en) |
| GB (1) | GB2009982B (en) |
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| US4322795A (en) * | 1980-01-24 | 1982-03-30 | Honeywell Information Systems Inc. | Cache memory utilizing selective clearing and least recently used updating |
| JPS60181942A (en) * | 1984-02-29 | 1985-09-17 | Fujitsu Ltd | Memory control device |
| DE19543193C1 (en) * | 1995-11-20 | 1997-02-13 | Daimler Benz Ag | Stem for a passenger car with a support structure |
| JP3940148B2 (en) * | 2002-11-20 | 2007-07-04 | 富士通株式会社 | Memory control device and cache replacement control method |
| US7673102B2 (en) | 2006-05-17 | 2010-03-02 | Qualcomm Incorporated | Method and system for maximum residency replacement of cache memory |
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| BE620922A (en) * | 1961-08-08 | |||
| GB1124017A (en) * | 1964-12-17 | 1968-08-14 | English Electric Computers Ltd | Data storage apparatus |
| US3840862A (en) * | 1973-09-27 | 1974-10-08 | Honeywell Inf Systems | Status indicator apparatus for tag directory in associative stores |
| JPS5090259A (en) * | 1973-12-10 | 1975-07-19 |
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- 1978-12-06 AU AU42245/78A patent/AU523670B2/en not_active Expired
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- 1978-12-07 FR FR7834550A patent/FR2411465B1/en not_active Expired
- 1978-12-07 GB GB7847553A patent/GB2009982B/en not_active Expired
- 1978-12-08 DE DE19782853165 patent/DE2853165A1/en active Granted
- 1978-12-08 JP JP15188878A patent/JPS5489438A/en active Pending
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| GB2009982B (en) | 1982-03-24 |
| AU523670B2 (en) | 1982-08-12 |
| AU4224578A (en) | 1980-06-12 |
| DE2853165A1 (en) | 1979-06-13 |
| GB2009982A (en) | 1979-06-20 |
| FR2411465A1 (en) | 1979-07-06 |
| DE2853165C2 (en) | 1989-09-21 |
| JPS5489438A (en) | 1979-07-16 |
| FR2411465B1 (en) | 1986-05-30 |
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